Texas Instruments TMS320C67 DSP Series, Reference Manual

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Addressing Modes
3-23 TMS320C62x/C67x Fixed-Point Instruction Set
3.8.3 Syntax for Load/Store Address Generation
The ’C62x and ’C67x CPUs have a load/store architecture, which means that
the only way to access data in memory is with a load or store instruction.
Table 3–7 shows the syntax of an indirect address to a memory location.
Sometimes a large offset is required for a load/store. In this case you can use
the B14 or B15 register as the base register, and use a 15-bit constant (
ucst15)
as the offset.
Table 3–7. Indirect Address Generation for Load/Store
Addressing Type
No Modification of
Address Register
Preincrement or
Predecrement of
Address Register
Postincrement or
Postdecrement of
Address Register
Register indirect *R *++R
*– –R
*R++
*R– –
Register relative *+R[ ucst5]
*–R[ ucst5]
*+ +R[ ucst5]
*– –R[ ucst5]
*R+ +[ ucst5]
*R– –[ ucst5]
Register relative with
15-bit constant offset *+B14/B15[ ucst15] not supported not supported
Base + index *+R[ offsetR]
*–R[ offsetR]
*++R[ offsetR]
*– –R[ offsetR]
*R+ +[ offsetR]
*R– –[ offsetR]