Texas Instruments TMS320C6670, Data Manual

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78 Device Configuration Copyright 2012 Texas Instruments Incorporated
SPRS689D—March 2012
Multicore Fixed and Floating-Point System-on-Chip
TMS320C6670
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3.3.12 IPC Generation (IPCGRx) Registers
IPCGRx are the IPC interrupt generation registers to facilitate inter CorePac interrupts.
The C6670 has four IPCGRx registers (IPCGR0 through IPCGR3) registers. This can be used by external hosts or
CorePacs to generate interrupts to other CorePacs. A write of 1 to IPCG field of IPCGRx register will generate an
interrupt pulse to CorePacx (0 <= x <= 3).
These registers also provide a Source ID facility by which up to 28 different sources of interrupts can be identified.
Allocation of source bits to source processor and meaning is entirely based on software convention. The register field
descriptions are given in the following tables. Virtually anything can be a source for these registers as this is
completely controlled by software. Any master that has access to BOOTCFG module space can write to these
registers. The IPC Generation Register is shown in
Figure 3-11 and described in Table 3-13 .
Table 3-12 NMI Generation Register Field Descriptions
Bit Field Description
31-1 Reserved Reserved
0 NMIG Reads return 0
Writes:
0 = No effect
1 = Creates NMI pulse to the corresponding CorePac — CorePac0 for NMIGR0, etc.
End of Table 3-12
Figure 3-11 IPC Generation Registers (IPCGRx)
31 30 29 28 27 8 7 6 5 4 3 1 0
SRCS27 SRCS26 SRCS25 SRCS24 SRCS23 – SRCS4 SRCS3 SRCS2 SRCS1 SRCS0 Reserved IPCG
RW +0 RW +0 RW +0 RW +0 RW +0 (per bit field) RW +0 RW +0 RW +0 RW +0 R, +000 RW +0
Legend: R = Read only; RW = Read/Write; - n = value after reset
Table 3-13 IPC Generation Registers Field Descriptions
Bit Field Description
31-4 SRCSx Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Sets both SRCSx and the corresponding SRCCx.
3-1 Reserved Reserved
0 IPCG Reads return 0.
Writes:
0 = No effect
1 = Creates an inter-DSP interrupt.
End of Table 3-13