Texas Instruments TMS320C6670, Data Manual

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212 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated
SPRS689D—March 2012
Multicore Fixed and Floating-Point System-on-Chip
TMS320C6670
www.ti.com
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7.26 Bit Rate Coprocessor (BCP)
The BCP is a hardware accelerator for wireless infrastructure. It performs most of the uplink and downlink layer 1
bit processing for 3G and 4G wireless standards. It supports LTE, FDD WCDMA, TD-SCDMA, and WiMAX
802.16-2009 standards. It supports various downlink processing blocks like CRC attachment, turbo encoding, rate
matching, code block concatenation, scrambling, and modulation. It supports various uplink processing blocks like
soft slicer, de-scrambler, de-concatenation, rate de-matching and LLR combining. For more information, see the Bit
Coprocessor (BCP) for KeyStone Devices User Guide in
2.9 ‘‘Related Documentation from Texas Instruments’’ on
page 66 .
7.27 Serial RapidIO (SRIO) Port
The SRIO port on the device is a high-performance, low pin-count SerDes interconnect. The use of the RapidIO
interconnect in a baseband board design can create a homogeneous interconnect environment, providing
connectivity and control among the components. RapidIO is based on the memory and device addressing concepts
of processor buses in which the transaction processing is managed completely by hardware. This enables the
RapidIO interconnect to lower the system cost by providing lower latency, reduced overhead of packet data
processing, and higher system bandwidth, all of which are key for wireless interfaces. For more information, see the
Serial RapidIO (SRIO) for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’
on page 66 .
7.28 General-Purpose Input/Output (GPIO)
7.28.1 GPIO Device-Specific Information
On the TMS320C6670, the GPIO peripheral pins GP[15:0] are also used to latch configuration pins. For more
detailed information on device/peripheral configuration and the C6670 device pin muxing, see
‘‘Device
Configuration’’ on page 67.
7.28.2 GPIO Electrical Data/Timing
Table 7-81 GPIO Input Timing Requirements
(1)
(see Figure 7-53 )
1 C = 1/SYSCLK1 clock frequency in ns
No. Min Max Unit
1 t
w(GPOH)
Pulse duration, GPOx high 12C ns
2 t
w(GPOL)
Pulse duration, GPOx low 12C ns
End of Table 7-81
Table 7-82 GPIO Output Switching Characteristics
(1)
(see Figure 7-53 )
1 C = 1/SYSCLK1 clock frequency in ns
No. Parameter Min Max Unit
3 t
w(GPOH)
Pulse duration, GPOx high 36C - 8 ns
4 t
w(GPOL)
Pulse duration, GPOx low 36C - 8 ns
End of Table 7-82