Texas Instruments TMS320C6670, Data Manual

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Multicore Fixed and Floating-Point System-on-Chip
Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications 149
SPRS689D—March 2012
TMS320C6670
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• Debug visibility
– Queue watermarking/threshold allows detection of maximum usage of event queues
– Error and status recording to facilitate debug
7.8.1 EDMA3 Device-Specific Information
The EDMA supports two addressing modes: constant addressing and increment addressing mode. Constant
addressing mode is applicable to a very limited set of use cases; for most applications increment mode can be used.
On the C6670 SoC, the EDMA can use constant addressing mode only with the enhanced Viterbi decoder
coprocessor (VCP) and the enhanced turbo decoder coprocessor (TCP). Constant addressing mode is not supported
by any other peripheral or internal memory in the DSP. Note that increment mode is supported by all peripherals,
including VCP and TCP. For more information on these two addressing modes, see the
Enhanced Direct Memory
Access 3 (EDMA3) for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on
page 66 .
For the range of memory addresses that include EDMA3 channel controller (EDMA3CC) control registers and
EDMA3 transfer controller (EDMA3TC) control register see Section 2.2
‘‘Memory Map Summary’’ on page 21.
For memory offsets and other details on EDMA3CC and EDMA3TC Control Registers entries, see the Enhanced
Direct Memory Access 3 (EDMA3) for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas
Instruments’’ on page 66 .
7.8.2 EDMA3 Channel Controller Configuration
Table 7-33 provides the configuration for each of the EDMA3 channel controllers present on the device.
7.8.3 EDMA3 Transfer Controller Configuration
Each transfer controller on the device is designed differently based on considerations like performance
requirements, system topology (like main TeraNet bus width, external memory bus width), etc. The parameters that
determine the transfer controller configurations are:
•
FIFOSIZE:
Determines the size in bytes for the data FIFO that is the temporary buffer for the in-flight data.
The data FIFO is where the read return data read by the TC read controller from the source endpoint is stored
and subsequently written out to the destination endpoint by the TC write controller.
• BUSWIDTH: The width of the read and write data buses in bytes, for the TC read and write controller,
respectively. This is typically equal to the bus width of the main TeraNet interface.
•
Default Burst Size (DBS):
The DBS is the maximum number of bytes per read/write command issued by a
transfer controller.
• DSTREGDEPTH: This determines the number of destination FIFO register set. The number of destination
FIFO register set for a transfer controller determines the maximum number of outstanding transfer requests.
Table 7-33 EDMA3 Channel Controller Configuration
Description EDMA3 CC0 EDMA3 CC1 EDMA3 CC2
Number of DMA channels in channel controller 16 64 64
Number of QDMA channels 8 8 8
Number of interrupt channels 16 64 64
Number of PaRAM set entries 128 512 512
Number of event queues 2 4 4
Number of transfer controllers 2 4 4
Memory protection existence Yes Yes Yes
Number of memory protection and shadow regions 8 8 8
End of Table 7-33