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2.11 Reset Considerations

DDR2

memory

controller

registers

Hard

Reset from

PLLC1

State

machine

VRST

VCTL_RST

DDR

PSC

Peripheral Architecture

Once in self-refresh mode, the DDR2 memory controller input clocks (VCLK and X2_CLK) may be gated
off or changed in frequency. Stable clocks must be present before exiting self-refresh mode. See

Section 2.16

for more information describing the proper procedure to follow when shutting down DDR2

memory controller input clocks.

The DDR2 memory controller has two reset signals, VRST and VCTL_RST. The VRST is a module-level
reset that resets both the state machine as well as the DDR2 memory controller memory-mapped
registers. The VCTL_RST resets the state machine only. If the DDR2 memory controller is reset
independently of other peripherals, the user's software should not perform memory, as well as register
accesses, while VRST or VCTL_RST are asserted. If memory or register accesses are performed while
the DDR2 memory controller is in the reset state, other masters may hang. Following the rising edge of
VRST or VCTL_RST, the DDR2 memory controller immediately begins its initialization sequence.
Command and data stored in the DDR2 memory controller FIFOs are lost.

Table 13

describes the different

methods for asserting each reset signal. The Power and Sleep Controller (PSC) acts as a master
controller for power management for all of the peripherals on the device. For detailed information on
power management procedures using the PSC, see the

TMS320C642x DSP Power and Sleep Controller

(PSC) User's Guide

(

SPRUEN8

).

Figure 15

shows the DDR2 memory controller reset diagram.

Table 13. Reset Sources

Reset Signal

Reset Source

VRST

Hardware/device reset

VCTL_RST

Power and sleep controller

Figure 15. DDR2 Memory Controller Reset Block Diagram

DDR2 Memory Controller

30

SPRUEM4A – November 2007

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Summary of Contents for TMS320C642 Series

Page 1: ...TMS320C642x DSP DDR2 Memory Controller User s Guide Literature Number SPRUEM4A November 2007 ...

Page 2: ...2 SPRUEM4A November 2007 Submit Documentation Feedback ...

Page 3: ...tion Considerations 35 3 Supported Use Cases 36 3 1 Connecting the DDR2 Memory Controller to DDR2 Memory 36 3 2 Configuring Memory Mapped Registers to Meet DDR2 400 Specification 36 4 DDR2 Memory Controller Registers 41 4 1 SDRAM Status Register SDRSTAT 42 4 2 SDRAM Bank Configuration Register SDBCR 43 4 3 SDRAM Refresh Control Register SDRCR 45 4 4 SDRAM Timing Register SDTIMR 46 4 5 SDRAM Timing...

Page 4: ...ontroller Diagram 34 17 Connecting DDR2 Memory Controller for 32 Bit Connection 37 18 Connecting DDR2 Memory Controller for 16 Bit Connection 37 19 SDRAM Status Register SDRSTAT 42 20 SDRAM Bank Configuration Register SDBCR 43 21 SDRAM Refresh Control Register SDRCR 45 22 SDRAM Timing Register SDTIMR 46 23 SDRAM Timing Register 2 SDTIMR2 47 24 Peripheral Bus Burst Priority Register PBBPR 48 25 Int...

Page 5: ...DDR2 Memory Controller Registers Relative to Base Address 2000 0000h 41 23 DDR2 Memory Controller Registers Relative to Base Address 01C4 2000h 41 24 DDR2 Memory Controller Registers Relative to Base Address 01C4 0000h 41 25 SDRAM Status Register SDRSTAT Field Descriptions 42 26 SDRAM Bank Configuration Register SDBCR Field Descriptions 43 27 SDRAM Refresh Control Register SDRCR Field Descriptions...

Page 6: ...llateral is available in the C6000 DSP product folder at www ti com c6000 SPRUEM3 TMS320C642x DSP Peripherals Overview Reference Guide Provides an overview and briefly describes the peripherals available on the TMS320C642x Digital Signal Processor DSP SPRAA84 TMS320C64x to TMS320C64x CPU Migration Guide Describes migrating from the Texas Instruments TMS320C64x digital signal processor DSP to the T...

Page 7: ... location for program and data storage The DDR2 memory controller supports the following features JESD79D 2A standard compliant DDR2 SDRAM 256 Mbyte memory space Data bus width of 32 or 16 bits see the device specific data manual for the mode s that are supported CAS latencies 2 3 4 and 5 Internal banks 1 2 4 and 8 Burst length 8 Burst type sequential 1 CS signal Page sizes 256 512 1024 and 2048 S...

Page 8: ...s to DDR2 Memory Controller The DDR2 memory controller supports JESD79D 2A DDR2 400 SDRAM memories utilizing either 32 bit or 16 bit of the DDR2 memory controller data bus See Section 3 for more details The DDR2 memory controller is compliant with the JESD79D 2A DDR2 SDRAM standard with the exception of the following feature list On Die Termination ODT The DDR2 memory controller does not include a...

Page 9: ...n version of the DSP clock PLL2_SYSCLK1 should be configured to clock at the frequency of the desired data rate or stated similarly it should operate at twice the frequency of the desired DDR2 memory clock DDR_CLK and DDR_CLK are the two output clocks of the DDR2 memory controller providing the interface clock to the DDR2 SDRAM memory These two clocks operate at a frequency of PLL2_SYSCLK1 2 SYSCL...

Page 10: ...MHZ Divider Ratio X2_CLK Frequency MHZ DDR2 Clock Frequency MHZ 28 756 3 252 126 19 513 2 256 6 128 3 29 783 3 261 130 5 20 540 2 270 135 31 837 3 279 139 5 21 567 2 283 5 141 8 32 864 3 288 144 22 594 2 297 148 5 23 621 2 310 155 3 24 648 2 324 162 25 675 2 337 5 168 8 There are two clock domains within the DDR2 memory controller The two clock domains are driven by VCLK and a divided down by 2 ve...

Page 11: ...Clock enable Active high DDR_CS O Z Chip select Active low DDR_WE O Z Write enable strobe Active low command output DDR_RAS O Z Row address strobe Active low command output DDR_CAS O Z Column address strobe Active low command output DDR_DQM 3 0 O Z Data mask Output mask signal for write data DDR_DQS 3 0 I O Z Data strobe Active high bi directional signals Output with write data input with read dat...

Page 12: ...f refresh mode WRT Inputs the starting column address and begins the write operation WRT with Inputs the starting column address and begins the write operation The write operation is followed by a autoprecharge precharge Table 4 Truth Table for DDR2 SDRAM Commands DDR2 SDRAM CKE CS RAS CAS WE BA 2 0 A 12 11 9 0 A10 DDR2 memory controller DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_BA 2 0 DDR_A 12 11...

Page 13: ...B command the DDR2 memory controller begins performing refreshes at a rate defined by the refresh rate RR bit in the SDRAM refresh control register SDRCR Page information is always invalid before and after a REFR command thus a refresh cycle always forces a page miss This type of refresh cycle is often called autorefresh Autorefresh commands may not be disabled within the DDR2 memory controller Se...

Page 14: ...fter a reset to the DDR2 memory controller or following the initialization sequence DDR2 SDRAMs also require this cycle prior to a refresh REFR and mode set register commands MRS and EMRS During a DCAB command DDR_A 10 is driven high to ensure the deactivation of all banks Figure 5 shows the timing diagram for a DCAB command Figure 5 DCAB Command 14 DDR2 Memory Controller SPRUEM4A November 2007 Su...

Page 15: ...AC DDR_A 10 DDR_CAS DDR_CLK Peripheral Architecture The DEAC command closes a single bank of memory specified by the bank select signals Figure 6 shows the timings diagram for a DEAC command Figure 6 DEAC Command SPRUEM4A November 2007 DDR2 Memory Controller 15 Submit Documentation Feedback ...

Page 16: ...he value of DDR_BA 2 0 selects the bank and the value of A 12 0 selects the row When the DDR2 memory controller issues an ACTV command a delay of tRCD is incurred before a read or write command is issued Figure 7 shows an example of an ACTV command Reads or writes to the currently active row and bank of memory can achieve much higher throughput than reads or writes to random areas because every ti...

Page 17: ...e CAS latency is three cycles in Figure 8 Read latency is equal to CAS latency plus additive latency The DDR2 memory controller always configures the memory to have an additive latency of 0 so read latency equals CAS latency Since the default burst size is 8 the DDR2 memory controller returns 8 pieces of data for every read command If additional accesses are not pending to the DDR2 memory controll...

Page 18: ...ency minus 1 All writes have a burst length of 8 The use of the DDR_DQM outputs allows byte and halfword writes to be executed Figure 9 shows the timing for a write on the DDR2 memory controller If the transfer request is for less than 8 words depending on the scheduling result and the pending commands the DDR2 memory controller can Mask out the additional data using DDR_DQM outputs Terminate the ...

Page 19: ...y controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands When the MRS or EMRS command is executed the value on DDR_BA 1 0 selects the mode register to be written and the data on DDR_A 12 0 is loaded into the register Figure 10 shows the timing for an MRS and EMRS command The DDR2 memory controller only issues MRS and EMRS commands during the DD...

Page 20: ...er See the device specific data manual for the memory widths that are supported Both big endian and little endian formats are supported Figure 11 shows the byte lanes used on the DDR2 memory controller The external memory is always right aligned on the data bus Table 5 Addressable Memory Ranges Memory Width Maximum addressable bytes per CS space Description 16 128 Mbytes Halfword address 32 256 Mb...

Page 21: ...l memory in both big endian and little endian modes See the device specific data manual for the memory widths that are supported Since the endianness mode must be determined prior to bootloading the endian mode selection is latched in the Boot Configuration BOOTCFG register when the device is reset This endianness mode selection is also reflected in the BE bit in the SDRAM status register SDRSTAT ...

Page 22: ... bits whereas the number of column and bank bits are determined by the IBANK and PAGESIZE fields Table 9 and Table 10 show how the logical address bits map to the DDR2 SDRAM row column and bank bits for combinations of IBANK and PAGESIZE values The same DDR2 memory controller pins provide the row and column address to the DDR2 SDRAM thus the DDR2 memory controller appropriately shifts the address ...

Page 23: ...mn address bits nrb number of row address bits nbb number of bank address bits Table 10 Logical Address to DDR2 SDRAM Address Map for 16 bit SDRAM SDBCR Bit Logical Address 1 IBANK PAGESIZE 31 30 29 28 27 26 25 24 23 22 21 15 14 13 12 11 10 9 8 1 0 0 0 nrb 13 ncb 8 1 0 nrb 13 nbb 1 ncb 8 2h 0 nrb 13 nbb 2 ncb 8 3h 0 nrb 13 nbb 3 ncb 8 0 1 nrb 13 ncb 9 1 1 nrb 13 nbb 1 ncb 9 2h 1 nrb 13 nbb 2 ncb 9...

Page 24: ... N bank 1 Row N bank 0 Row N bank P Peripheral Architecture Figure 12 Logical Address to DDR2 SDRAM Address Map NOTE M is number of columns as determined by PAGESIZE minus 1 P is number of banks as determined by IBANK minus 1 and N is number of rows as determined by both PAGESIZE and IBANK minus 1 24 DDR2 Memory Controller SPRUEM4A November 2007 Submit Documentation Feedback ...

Page 25: ... Row 2 Row 0 Row 1 Bank P 0 1 2 3 M C C l l 3 M o o o C o C o C o C Peripheral Architecture Figure 13 DDR2 SDRAM Column Row and Bank Access NOTE M is number of columns as determined by PAGESIZE minus 1 P is number of banks as determined by IBANK minus 1 and N is number of rows as determined by both PAGESIZE and IBANK minus 1 SPRUEM4A November 2007 DDR2 Memory Controller 25 Submit Documentation Fee...

Page 26: ...diagram of the DDR2 memory controller FIFOs Commands write data and read data arrive at the DDR2 memory controller parallel to each other The same peripheral bus is used to write and read data from external memory as well as internal memory mapped registers Table 11 DDR2 Memory Controller FIFO Description FIFO Description Depth 64 bit doublewords Command Stores all commands coming from on chip req...

Page 27: ... writes selects writes to rows already open Selects the highest priority command from pending reads and writes to open rows If multiple commands have the highest priority then the DDR2 memory controller selects the oldest command The DDR2 memory controller may now have a final read and write command If the Read FIFO is not full then the read command will be performed before the write command other...

Page 28: ...placing high bandwidth masters on the highest priority levels These bits can be left as FEh unless advanced bandwidth prioritization control is required A race condition may exist when certain masters write data to the DDR2 memory controller For example if master A passes a software message via a buffer in DDR2 memory and does not wait for indication that the write completes when master B attempts...

Page 29: ...he REFR command Refresh Release Backlog count is greater than 3 Indicates the level at which enough REFR commands have been performed and the DDR2 memory controller may service new memory access requests Refresh Need Backlog count is greater than 7 Indicates the DDR2 memory controller should raise the priority level of a REFR command above servicing a new memory access Refresh Must Backlog count i...

Page 30: ...memory as well as register accesses while VRST or VCTL_RST are asserted If memory or register accesses are performed while the DDR2 memory controller is in the reset state other masters may hang Following the rising edge of VRST or VCTL_RST the DDR2 memory controller immediately begins its initialization sequence Command and data stored in the DDR2 memory controller FIFOs are lost Table 13 describ...

Page 31: ...er up and device reset If the DDR2 memory controller is reset via the Power and Sleep Controller PSC and the VTP input clock is disabled accesses to the DDR2 memory controller will not complete To re enable accesses to the DDR2 memory controller enable the VTP input clock and then perform the VTP calibration sequence again The DDR2 SDRAM contains mode and extended mode registers that configure the...

Page 32: ...m Exit OCD calibration DDR_A 6 0 6 ODT Value Rtt Cleared to 0 to select 75 ohms This feature is not supported because the DDR_ODT signal is not pinned out DDR_A 5 3 0 5 3 Additive Latency 0 cycles of additive latency DDR_A 2 1 2 ODT Value Rtt Set to 1 to select 75 ohms This feature is not supported because the DDR_ODT signal is not pinned out DDR_A 1 1 1 Output Driver Impedance DDR2 drive strength...

Page 33: ...reset program the PSC to place the DDR2 memory controller into the Enable state 6 Enable VTP manual calibration by writing to the VTP IO control register VTPIOCR See Section 4 12 for details on VTPIOCR a With a single write set the EN bit field bit 13 to 1 and the RECAL bit field bit 15 to 0 by writing a value of 0000 201Fh b Set the RECAL bit field bit 15 to 1 making sure the value written to the...

Page 34: ...ay be managed by two methods Self refresh mode see Section 2 10 Gating input clocks to the module off Gating input clocks off to the DDR2 memory controller achieves higher power savings when compared to the power savings of self refresh mode The input clocks are turned off outside of the DDR2 memory controller through the use of the Power and Sleep Controller PSC and the PLL controller 2 PLLC2 Fig...

Page 35: ...the DDR2 memory controller DLL 5 Poll the PHYRDY bit in the SDRAM status register SDRSTAT to be a logic low indicating that the MCLK has been stopped and the DLL is powered down 6 Program DDR2 memory controller LPSC to disable VCLK 7 Program PLLC2 registers to stop PLL2_SYSCLK1 which disables X2_CLK of the DDR2 memory controller as well as DDR_CLK and DDR_CLK To turn clocks back on 1 Program PLLC2...

Page 36: ...e 17 displays a 32 bit interface therefore two 16 bit DDR2 devices are connected to the DDR2 memory controller From Figure 17 you can see that the data bus data strobe and data mask byte enable signals are point to point where as all other address control and clocks are not Figure 18 displays a 16 bit interface therefore all signals are point to point See the device specific data manual for the da...

Page 37: ...bit UDM LDM CAS RAS WE CS CKE CK CK 200 Ω 200 Ω controller DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_WE DDR_RAS DDR_CAS DDR_DQM 0 DDR_DQM 1 DDR_DQS 0 DDR_DQS 1 DDR_BA 2 0 DDR_A 12 0 DDR_D 15 0 DDR_ZN DDR_ZP CK CK CKE CS WE RAS CAS LDM UDM LDQS UDQS BA 2 0 A 12 0 DQ 15 0 DDR2 memory x16 bit 200 Ω 200 Ω DDR2 memory controller Supported Use Cases Figure 17 Connecting DDR2 Memory Controller for 32 Bit Connec...

Page 38: ...AGESIZE 2h To select 1024 word page size The SDRAM refresh control register SDRCR configures the DDR2 memory controller to meet the refresh requirements of the attached DDR2 device SDRCR also allows the DDR2 memory controller to enter and exit self refresh and enable and disable the MCLK stopping In this example we assume that the DDR2 memory controller is not is in self refresh mode and that MCLK...

Page 39: ...rge command to 20 tRP fDDR2_CLK 1 2 refresh or activate command T_RCD tRCD Activate command to 20 tRCD fDDR2_CLK 1 2 read write command T_WR tWR Write recovery time 15 tWR fDDR2_CLK 1 1 T_RAS tRAS Active to precharge 45 tRAC fDDR2_CLK 1 5 command T_RC tRC Activate to Activate 65 tRC fDDR2_CLK 1 8 command in the same bank T_RRD tRRD Activate to Activate 10 4 tRRD 2 tCK 4 tCK 1 1 command in a differ...

Page 40: ...ls DDR_CLK and DDR_CLK and data strobe signals DDR_DQS For these signals calculate the round trip board delay from the DDR2 memory controller to the memory and then choose the maximum delay to determine the READLAT value In this example we will assume the round trip board delay is 1 DDR_CLK cycle therefore READLAT can be calculated as follows READLAT CAS latency round trip board delay 1 4 1 1 4 Ta...

Page 41: ...esh control register SDRCR SDRAM bank configuration register SDBCR Big Endian SDRAM bank configuration register SDBCR SDRAM refresh control register SDRCR Table 22 DDR2 Memory Controller Registers Relative to Base Address 2000 0000h Offset Acronym Register Description Section 4h SDRSTAT SDRAM Status Register Section 4 1 8h SDBCR SDRAM Bank Configuration Register Section 4 2 Ch SDRCR SDRAM Refresh ...

Page 42: ...ate after reset Table 25 SDRAM Status Register SDRSTAT Field Descriptions Bit Field Value Description 31 BE Big endian Reflects the endianness mode for the device 0 Little endian mode 1 Big endian mode 30 3 Reserved 0 Reserved 2 PHYRDY DDR2 memory controller DLL ready Reflects whether the DDR2 memory controller DLL is powered up and locked 0 DLL is not ready either powered down in reset or not loc...

Page 43: ...3 BOOTUNLOCK Boot unlock Controls the write permission settings for the DDRDRIVE bit To change the DDRDRIVE bit value use the following sequence 1 Write a 1 to the BOOTUNLOCK bit 2 Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDRDRIVE bit 0 DDRDRIVE bit may not be changed 1 DDRDRIVE bit may be changed 22 19 Reserved 2h Reserved Always write a value of 2h to these bits 18 DDR...

Page 44: ...s the number of internal banks on the external DDR2 memory 0 1 bank 1h 2 banks 2h 4 banks 3h 8 banks 4h 7h Reserved 3 Reserved 0 Reserved Always write a 0 to this bit 2 0 PAGESIZE 0 7h DDR2 page size Defines the page size of each page of the external DDR2 memory 0 256 word page requiring 8 column address bits 1h 512 word page requiring 9 column address bits 2h 1024 word page requiring 10 column ad...

Page 45: ...scriptions Bit Field Value Description 31 SR Self refresh 0 DDR2 memory controller exits the self refresh mode 1 DDR2 memory controller enters the self refresh mode 30 MCLKSTOPEN MCLK stop enable 0 Disables MCLK stopping MCLK may not be stopped 1 Enables MCLK stopping MCLK may be stopped The SR bit must be set to 1 before setting the MCLKSTOPEN bit to 1 29 24 Reserved 0 Reserved 23 Reserved 0 Rese...

Page 46: ...mmand to a read or write command minus 1 Corresponds to the trcd AC timing parameter in the DDR2 data sheet Calculate by T_RCD trcd DDR_CLK period 1 18 16 T_WR 0 7h Specifies the minimum number of DDR_CLK cycles from the last write transfer to a precharge command minus 1 Corresponds to the twr AC timing parameter in the DDR2 data sheet Calculate by T_WR twr DDR_CLK period 1 When the value of this ...

Page 47: ...0 Reserved 24 23 Reserved x Reserved Reset value is indeterminate 22 16 T_XSNR 0 7Fh Specifies the minimum number of DDR_CLK cycles from a self refresh exit to any other command except a read command minus 1 Corresponds to the txsnr AC timing parameter in the DDR2 data sheet Calculate by T_XSNR txsnr DDR_CLK period 1 15 8 T_XSRD 0 FFh Specifies the minimum number of DDR_CLK cycles from a self refr...

Page 48: ...Figure 24 Peripheral Bus Burst Priority Register PBBPR 31 16 Reserved R 0 15 8 7 0 Reserved PR_OLD_COUNT R 0 R W FFh LEGEND R W Read Write R Read only n value after reset Table 30 Peripheral Bus Burst Priority Register PBBPR Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 PR_OLD_COUNT 0 FFh Priority raise old counter Specifies the number of memory transfers after which ...

Page 49: ...R 0 15 3 2 1 0 Reserved LT Reserved R 0 R W1C 0 R 0 LEGEND R W Read Write R Read only W1C Write 1 to clear writing 0 has no effect n value after reset Table 31 Interrupt Raw Register IRR Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 LT Line trap Write a 1 to clear LT and the LTM bit in the interrupt masked register IMR a write of 0 has no effect 0 A line trap condition ...

Page 50: ...r IMR 31 16 Reserved R 0 15 3 2 1 0 Reserved LTM Reserved R 0 R W1C 0 R 0 LEGEND R W Read Write R Read only W1C Write 1 to clear writing 0 has no effect n value after reset Table 32 Interrupt Masked Register IMR Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 LTM Line trap masked Write a 1 to clear LTM and the LT bit in the interrupt raw register IRR a write of 0 has no e...

Page 51: ...t Register IMSR 31 16 Reserved R 0 15 3 2 1 0 Reserved LTMSET Reserved R 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 33 Interrupt Mask Set Register IMSR Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 LTMSET Line trap interrupt set Write a 1 to set LTMSET and the LTMCLR bit in the interrupt mask clear register IMCR a write of 0 has no effect 0 ...

Page 52: ...terrupt Mask Clear Register IMCR 31 16 Reserved R 0 15 3 2 1 0 Reserved LTMCLR Reserved R 0 R W1C 0 R 0 LEGEND R W Read Write R Read only W1C Write 1 to clear writing 0 has no effect n value after reset Table 34 Interrupt Mask Clear Register IMCR Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 LTMCLR Line trap interrupt clear Write a 1 to clear LTMCLR and the LTMSET bit i...

Page 53: ...ld Value Description 31 16 Reserved 5000h Reserved Always write 5000h to these bits 15 6 Reserved 190h Reserved Always write 190h to these bits 5 DLLRESET Reset DLL 0 DLL is out of reset 1 Places the DLL in reset 4 DLLPWRDN Power down DLL 0 DLL is powered up 1 DLL is powered down if DLLPWRDN and the SR bit and MCLKSTOPEN bit in the SDRAM refresh control register SDRCR are set to 1 3 Reserved 1 Res...

Page 54: ... Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 RECAL Start VTP IO calibration 0 Normal operation 1 Transition from 0 to 1 starts VTP IO calibration 14 Reserved 0 Reserved Always write a 0 to this bit 13 EN VTP enable 0 VTP IO calibration is disabled 1 VTP IO calibration is enabled 12 11 Reserved 0 Reserved Always write a 0 to this bit 10 Reserved 0 Reserved 9 5 PCH 0 1Fh P ...

Page 55: ...nel value for IO impedance calibration Following the VTP calibration sequence this value should be read and written to the PCH field in the VTP IO control register VTPIOCR 4 0 NCH 0 1Fh N channel value for IO impedance calibration Following the VTP calibration sequence this value should be read and written to the NCH field in the VTP IO control register VTPIOCR The DDR VTP enable register DDRVTPER...

Page 56: ...lock and Bank address Section 2 4 3 Changed third sentence Figure 7 Changed signal name for Clock and Bank address Section 2 4 4 Changed third sentence in first paragraph Figure 8 Changed signal names Figure 9 Changed signal names Section 2 4 6 Changed second sentence in second paragraph Figure 10 Changed signal name for Clock and Bank address Table 15 Changed DDR_A 10 value Figure 16 Changed figu...

Page 57: ...ice and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyer...

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