Memory Banks
6-121
Optimizing Assembly Code via Linear Assembly
In the case of the FIR filter, scheduling the even and odd elements of the same
array on the same loop cycle cannot be done in a 2-cycle loop, as shown in
Figure 6–24. In this example, a valid 2-cycle software-pipelined loop without
memory constraints is ruled by the following constraints:
-
LDH h0 and LDH h1 are on the same loop cycle.
-
LDH x0 and LDH x1 are on the same loop cycle.
-
MPY p00 must be scheduled three or four cycles after LDH x0, because
it must read x0 from the previous iteration of LDH x0.
-
All MPYs must be five or six cycles after their LDH parents.
-
No MPYs on the same side (A or B) can be on the same loop cycle.
Figure 6–24. Dependency Graph of FIR Filter (With Even and Odd Elements of
Each Array on Same Loop Cycle)
2
7
6
1
0
?
6
1
A side
B side
2
MPY
5
5
5
LDH
LDH
5
MPY
5
LDH
5
MPY
MPY
5
5
LDH
h0
p10
p00
x0
x1
h1
p01
p11
Note:
Numbers in bold represent the cycle the instruction is scheduled on.
The scenario in Figure 6–24
almost works. All nodes satisfy the above
constraints except MPY p10. Because one parent is on cycle 1 (LDH h0) and
another on cycle 0 (LDH x1), the only cycle for MPY p10 is cycle 6. However,
another MPY on the A side is also scheduled on cycle 6 (MPY p00). Other
combinations of cycles for this graph produce similar results.
