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1.3.1 Emulation Logic

1.3.2 Memory Map

1.3.3 On-Chip Program and Data

1.3.4 CPU Interrupt Vectors

1.4

Memory Interface

Memory Interface

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The emulation logic is identical to that on the C28x fixed-point CPU. This logic includes the following

features. For more details about these features, refer to the

TMS320C28x DSP CPU and Instruction Set

Reference Guide

(literature number

SPRU430

•

Debug-and-test direct memory access (DT-DMA). A debug host can gain direct access to the content

of registers and memory by taking control of the memory interface during unused cycles of the

instruction pipeline.

•

A counter for performance benchmarking.

•

Multiple debug events. Any of the following debug events can cause a break in program execution:
– A breakpoint initiated by the ESTOP0 or ESTOP1 instruction.
– An access to a specified program-space or data-space location.

When a debug event causes the C28x to enter the debug-halt state, the event is called a break event.

•

Real-time mode of operation.

Like the C28x, the C28x+FPU uses 32-bit data addresses and 22-bit program addresses. This allows for a

total address reach of 4G words (1 word = 16 bits) in data space and 4M words in program space.

Memory blocks on all C28x+FPU designs are uniformly mapped to both program and data space. For

specific details about each of the map segments, see the data sheet for your device.

All C28x+FPU based devices contain at least two blocks of single access on-chip memory referred to as

M0 and M1. Each of these blocks is 1K words in size. M0 is mapped at addresses 0x0000 – 0x03FF and

M1 is mapped at addresses 0x0400 – 0x07FF. Like all other memory blocks on the C28x+FPU devices,

M0 and M1 are mapped to both program and data space. Therefore, you can use M0 and M1 to execute

code or for data variables. At reset, the stack pointer is set to the top of block M1. Depending on the

device, it may also have additional random-access memory (RAM), read-only memory (ROM), external

interface zones, or flash memory.

The C28x+FPU interrupt vectors are identical to those on the C28x CPU. Sixty-four addresses in program

space are set aside for a table of 32 CPU interrupt vectors. The CPU vectors can be mapped to the top or

bottom of program space by way of the VMAP bit. For more information about the CPU vectors, see

TMS320C28x DSP CPU and Instruction Set Reference Guide

(literature number

SPRU430

). For devices

with a peripheral interrupt expansion (PIE) block, the interrupt vectors will reside in the PIE vector table

and this memory can be used as program memory.

The C28x+FPU memory interface is identical to that on the C28x. The C28x+FPU memory map is

accessible outside the CPU by the memory interface, which connects the CPU logic to memories,

peripherals, or other interfaces. The memory interface includes separate buses for program space and

data space. This means an instruction can be fetched from program memory while data memory is being

accessed. The interface also includes signals that indicate the type of read or write being requested by the

CPU. These signals can select a specified memory block or peripheral for a given bus transaction. In

addition to 16-bit and 32-bit accesses, the C28x+FPU supports special byte-access instructions that can

access the least significant byte (LSByte) or most significant byte (MSByte) of an addressed word. Strobe

signals indicate when such an access is occurring on a data bus.

Introduction

SPRUEO2A – June 2007 – Revised August 2008

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Summary of Contents for TMS320C28 series

Page 1: ...TMS320C28x Floating Point Unit and Instruction Set Reference Guide Literature Number SPRUEO2A June 2007 Revised August 2008 ...

Page 2: ...2 SPRUEO2A June 2007 Revised August 2008 Submit Documentation Feedback ...

Page 3: ...es to Even Addresses 11 2 CPU Register Set 13 2 1 CPU Registers 14 2 1 1 Floating Point Status Register STF 16 2 1 2 Repeat Block Register RB 18 3 Pipeline 21 3 1 Pipeline Overview 22 3 2 General Guidelines for Floating Point Pipeline Alignment 22 3 3 Moves from FPU Registers to C28x Registers 23 3 4 Moves from C28x Registers to FPU Registers 23 3 5 Parallel Instructions 24 3 6 Invalid Delay Instr...

Page 4: ...U Pipeline 22 List of Tables 2 1 28x Plus Floating Point CPU Register Summary 15 2 2 Floating point Unit Status STF Register Field Descriptions 16 2 3 Repeat Block RB Register Field Descriptions 18 4 1 Operand Nomenclature 30 4 2 Summary of Instructions 32 A 1 Technical Changes Made in This Revision 137 List of Figures 4 SPRUEO2A June 2007 Revised August 2008 Submit Documentation Feedback ...

Page 5: ...232 Digital Signal Controllers DSCs Data Manual contains the pinout signal descriptions as well as electrical and timing specifications for the F2833x 2823x devices SPRZ272 TMS320F28335 F28334 F28332 TMS320F28235 F28234 F28232 Digital Signal Controllers DSCs Silicon Errata describes the advisories and usage notes for different versions of silicon CPU User s Guides SPRU430 TMS320C28x DSP CPU and In...

Page 6: ...ms It includes the module description and registers SPRUEU1 TMS320x2833x 2823x Enhanced Controller Area Network eCAN Reference Guide describes the eCAN that uses established protocol to communicate serially with other controllers in electrically noisy environments SPRUFZ5 TMS320F2833x 2823x Serial Communication Interface SCI Reference Guide describes the SCI which is a two wire asynchronous serial...

Page 7: ...er MCU with the processing power and C efficiency of TI s leading DSP technology This chapter provides an overview of the architectural structure and components of the C28x plus floating point unit CPU Topic Page 1 1 Introduction to the Central Processing Unit CPU 8 1 2 Compatibility with the C28x Fixed Point CPU 8 1 3 Components of the C28x plus Floating Point CPU 9 1 4 Memory Interface 10 SPRUEO...

Page 8: ...r features include ease of use through an intuitive instruction set byte packing and unpacking and bit manipulation The modified Harvard architecture of the CPU enables instruction and data fetches to be performed in parallel The CPU can read instructions and data while it writes data simultaneously to maintain the single cycle instruction operation across the pipeline The CPU does this over six s...

Page 9: ...ing data and program memory addresses decoding and executing instructions performing arithmetic logical and shift operations and controlling data transfers among CPU registers data memory and program memory A floating point unit for IEEE single precision floating point operations Emulation logic for monitoring and controlling various parts and functions of the device and for testing device operati...

Page 10: ...he C28x FPU devices M0 and M1 are mapped to both program and data space Therefore you can use M0 and M1 to execute code or for data variables At reset the stack pointer is set to the top of block M1 Depending on the device it may also have additional random access memory RAM read only memory ROM external interface zones or flash memory The C28x FPU interrupt vectors are identical to those on the C...

Page 11: ...eously because both use the DWDB Transactions that use different buses can happen simultaneously For example the CPU can read from program space using PAB and PRDB read from data space using DRAB and DRDB and write to data space using DWAB and DWDB at the same time This behavior is identical to the C28x CPU The C28x FPU CPU expects memory wrappers or peripheral interface logic to align any 32 bit ...

Page 12: ...Introduction 12 SPRUEO2A June 2007 Revised August 2008 Submit Documentation Feedback ...

Page 13: ... as the C28x CPU with an extended register and instruction set to support IEEE single precision floating point operations This section describes the extensions to the C28x architecture Topic Page 2 1 CPU Registers 14 SPRUEO2A June 2007 Revised August 2008 CPU Register Set 13 Submit Documentation Feedback ...

Page 14: ... set plus an additional set of floating point unit registers The additional floating point unit registers are the following Eight floating point result registers RnH where n 0 7 Floating point Status Register STF Repeat Block Register RB All of the floating point registers except the repeat block register are shadowed This shadowing can be used in high priority interrupts for fast context save and...

Page 15: ...egister 0x0000 DBGIER Yes Yes 16 bits Debug interrupt enable register 0x0000 P Yes Yes 32 bits Product register 0x00000000 PH Yes Yes 16 bits High half of P 0x0000 PL Yes Yes 16 bits Low half of P 0x0000 PC Yes Yes 22 bits Program counter 0x3FFFC0 RPC Yes Yes 22 bits Return program counter 0x00000000 SP Yes Yes 16 bits Stack pointer 0x0400 ST0 Yes Yes 16 bits Status register 0 0x0000 ST1 Yes Yes 1...

Page 16: ... the respective bits of ST0 When this instruction executes it will also clear the latched overflow and underflow flags if those flags are specified Example 2 1 Moving STF Flags to the ST0 Register Loop MOV32 R0H XAR4 MOV32 R1H XAR3 CMPF32 R1H R0H MOVST0 ZF NF Move ZF and NF to ST0 BF Loop GT Loop if R1H R0H Figure 2 2 Floating point Unit Status Register STF 31 30 16 SHDWS Reserved R W 0 R 0 15 10 ...

Page 17: ...e used to modify this flag 0 The floating point value is not zero 1 The floating point value is zero 2 NF Negative Floating Point Flag 1 2 The following instructions modify this flag based on the floating point value stored in the destination register MOV32 MOVD32 MOVDD32 ABSF32 NEGF32 The CMPF32 MAXF32 and MINF32 instructions modify this flag based on the result of the operation The SETFLG and SA...

Page 18: ...t occurs the repeat active RA bit is copied to the RAS bit and the RA bit is cleared When an interrupt return instruction occurs the RAS bit is copied to the RA bit and RAS is cleared 0 A repeat block was not active when the interrupt was taken 1 A repeat block was active when the interrupt was taken 30 RA Repeat Block Active Bit 0 This bit is cleared when the repeat counter RC reaches zero When a...

Page 19: ...t Count 0 The block will not be repeated it will be executed only once In this case the repeat active RA bit will not be set 1 This 16 bit value determines how many times the block will repeat The counter is initialized when the 0xFFFF RPTB instruction is executed and is decremented when the PC reaches the end of the block When the counter reaches zero the repeat active bit is cleared and the bloc...

Page 20: ...CPU Register Set 20 SPRUEO2A June 2007 Revised August 2008 Submit Documentation Feedback ...

Page 21: ... by taking advantage of the delay slots and filling them with non conflicting instructions This section describes the key characteristics of the pipeline with regards to floating point instructions The rules for avoiding pipeline conflicts are small in number and simple to follow and the C28x FPU assembler will help you by issuing errors for conflicts Topic Page 3 1 Pipeline Overview 22 3 2 Genera...

Page 22: ...have a p after their cycle count For example 2p stands for 2 pipelined cycles This means that an instruction can be started every cycle but the result of the instruction will only be valid one instruction later There are three general guidelines to determine if an instruction needs a delay slot 1 Floating point math operations multiply addition subtraction 1 x and MAC require 1 delay slot 2 Conver...

Page 23: ... two delay slots are required between a write to the floating point register and the transfer instruction as shown in Example 3 3 Example 3 3 Floating Point to C28x Register Software Pipeline Alignment ADDF32 32 bit floating point addition 2p operation An alignment cycle is required before copying R0H to ACC ADDF32 R0H R1H 2 R0H R1H 2 2 pipeline cycle instruction NOP 1 delay cycle or non conflicti...

Page 24: ...must be inserted to align the both math operations An example of a multiply with parallel add instruction is shown in Example 3 5 Example 3 6 2p 2p Parallel Instruction Software Pipeline Alignment MPYF32 ADDF32 instruction 32 bit floating point multiply with parallel add MPYF32 is a 2p operation ADDF32 is a 2p cycle operation MPYF32 R0H R1H R3H R0H R1H R3H 2 pipeline cycle operation ADDF32 R1H R2H...

Page 25: ...his conflict can be resolved by using a register other than R2H or by inserting a non conflicting instruction between the MPYF32 and ADDF32 instructions Since the SUBF32 does not use R2H this instruction can be moved before the ADDF32 as shown in Example 3 10 Example 3 9 Destination Source Register Conflict Invalid delay instruction ADDF32 should not use R2H as a source operand MPYF32 R2H R1H R0H ...

Page 26: ...tes R1H valid MPYF32 R2H valid Note Operations within parallel instructions cannot use the same destination register When two parallel operations have the same destination register the result is invalid For example see Example 3 13 If both operations within a parallel instruction try to update the same destination register as shown in Example 3 13 the assembler will issue an error Example 3 13 Inv...

Page 27: ...ion MOV32 R0H B1 Load R0H with B1 single cycle NOP Wait for MPYF32 to complete MPYF32 completes R1H is valid ADDF32 R1H R1H R0H R1H R1H R0H 2p operation NOP Wait for ADDF32 to complete ADDF32 completes R1H is valid MOV32 Y1 R1H Save R1H in Y1 single cycle Calculate Y2 MOV32 R0H M2 Load R0H with M2 single cycle MOV32 R1H X2 Load R1H with X2 single cycle MPYF32 R1H R1H R0H R1H M2 X2 2p operation MOV...

Page 28: ...gle cycle MOV32 R1H X2 Load R1H with X2 single cycle MPYF32 completes R3H is valid MPYF32 R0H R1H R0H R0H M2 X2 2p operation MOV32 R4H B1 Load R4H with B1 single cycle MOV32 completes R4H is valid ADDF32 R1H R4H R3H R1H B1 M1 X1 2p operation MOV32 R2H B2 Load R2H with B2 single cycle MPYF32 completes R0H is valid ADDF32 R0H R2H R0H R0H B2 M2 X2 2p operation ADDF32 completes R1H is valid MOV32 Y1 R...

Page 29: ... operations resource constraints and addressing modes The instructions listed here are an extension to the standard C28x instruction set For information on standard C28x instructions see the TMS320C28x DSP CPU and Instruction Set Reference Guide literature number SPRU430 Topic Page 4 1 Instruction Descriptions 30 4 2 Instructions 32 SPRUEO2A June 2007 Revised August 2008 Instruction Set 29 Submit ...

Page 30: ...sumed to be zero 16FHiHex 16 bit immediate hex value that represents the upper 16 bits of an IEEE 32 bit floating point value Lower 16 bits of the mantissa are assumed to be zero 16FLoHex A 16 bit immediate hex value that represents the lower 16 bits of an IEEE 32 bit floating point value 32Fhex 32 bit immediate value that represents an IEEE 32 bit floating point value 32F Immediate float value re...

Page 31: ...ption of the instruction execution is described Any constraints on the operands imposed by the processor or the assembler are discussed Restrictions Any constraints on the operands or use of the instruction imposed by the processor are discussed Pipeline This section describes the instruction in terms of pipeline cycles as described in Chapter 3 Example Examples of instruction execution If applica...

Page 32: ...6TOF32 RaH mem16 Convert 16 bit Integer to 32 bit Floating Point Value 59 I32TOF32 RaH mem32 Convert 32 bit Integer to 32 bit Floating Point Value 60 I32TOF32 RaH RbH Convert 32 bit Integer to 32 bit Floating Point Value 61 MACF32 R3H R2H RdH ReH RfH 32 bit Floating Point Multiply with Parallel Add 62 MACF32 R3H R2H RdH ReH RfH MOV32 RaH mem32 32 bit Floating Point Multiply and Accumulate with Par...

Page 33: ...allel Move 107 MPYF32 RdH ReH RfH MOV32 mem32 RaH 32 bit Floating Point Multiply with Parallel Move 109 MPYF32 RaH RbH RcH SUBF32 RdH ReH RfH 32 bit Floating Point Multiply with Parallel Subtract 110 NEGF32 RaH RbH CNDF Conditional Negation 111 POP RB Pop the RB Register from the Stack 112 PUSH RB Push the RB Register onto the Stack 113 RESTORE Restore the Floating Point Registers 114 RPTB label l...

Page 34: ...bH Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No Yes Yes No No The STF register flags are modified as follows NF 0 ZF 0 if RaH 30 23 0 ZF 1 Pipeline This is a single cycle instruction Example MOVIZF32 R1H 2 0 R1H 2 0 0xC0000000 ABSF32 R1H R1H R1H 2 0 0x40000000 ZF NF 0 MOVIZF32 R0H 5 0 R0H 5 0 0x40A00000 ABSF32 R0H R0H R0H 5 0...

Page 35: ...BFC0 RaH RbH 16FHi 0 This instruction can also be written as ADDF32 RaH RbH 16FHi Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No No No Yes Yes The STF register flags are modified as follows LUF 1 if ADDF32 generates an underflow condition LVF 1 if ADDF32 generates an overflow condition Pipeline This is a 2 pipeline cycle instru...

Page 36: ... 16FHi ADDF32 RaH RbH RcH ADDF32 RdH ReH RfH MOV32 RaH mem32 ADDF32 RdH ReH RfH MOV32 mem32 RaH MACF32 R3H R2H RdH ReH RfH MPYF32 RaH RbH RcH ADDF32 RdH ReH RfH Instruction Set 36 SPRUEO2A June 2007 Revised August 2008 Submit Documentation Feedback ...

Page 37: ...BFC0 RaH RbH 16FHi 0 This instruction can also be written as ADDF32 RaH 16FHi RbH Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No No No Yes Yes The STF register flags are modified as follows LUF 1 if ADDF32 generates an underflow condition LVF 1 if ADDF32 generates an overflow condition Pipeline This is a 2 pipeline cycle instru...

Page 38: ...Hi RbH ADDF32 RaH RbH RcH ADDF32 RdH ReH RfH MOV32 RaH mem32 ADDF32 RdH ReH RfH MOV32 mem32 RaH MACF32 R3H R2H RdH ReH RfH MPYF32 RaH RbH RcH ADDF32 RdH ReH RfH Instruction Set 38 SPRUEO2A June 2007 Revised August 2008 Submit Documentation Feedback ...

Page 39: ...completes RaH updated NOP Any instruction in the delay slot must not use RaH as a destination register or use RaH as a source operand Example Calculate Y M1 X1 B1 This example assumes that M1 X1 B1 and Y are all on the same data page MOVW DP M1 Load the data page MOV32 R0H M1 Load R0H with M1 MOV32 R1H X1 Load R1H with X1 MPYF32 R1H R1H R0H Multiply M1 X1 MOV32 R0H B1 and in parallel load R0H with...

Page 40: ...No No Yes Yes The STF register flags are modified as follows LUF 1 if ADDF32 generates an underflow condition LVF 1 if ADDF32 generates an overflow condition Pipeline ADDF32 is a 2 pipeline cycle instruction 2p and MOV32 takes a single cycle That is ADDF32 RdH ReH RfH 2 pipeline cycles 2p MOV32 mem32 RaH 1 cycle MOV32 completes mem32 updated NOP 1 cycle delay or non conflicting instruction ADDF32 ...

Page 41: ...RaH 16FHi RbH ADDF32 RaH RbH 16FHi ADDF32 RaH RbH RcH MACF32 R3H R2H RdH ReH RfH MPYF32 RaH RbH RcH ADDF32 RdH ReH RfH ADDF32 RdH ReH RfH MOV32 RaH mem32 SPRUEO2A June 2007 Revised August 2008 Instruction Set 41 Submit Documentation Feedback ...

Page 42: ...pported by the C28x CPU RdH ReH RfH RaH mem32 Restrictions The destination register for the ADDF32 and the MOV32 must be unique That is RaH and RdH cannot be the same register Any instruction in the delay slot must not use RdH as a destination register or use RdH as a source operand Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No Yes ...

Page 43: ...Load R2H with C MOV32 complete MOVL XAR4 Y ADDF32 complete SUBF32 R0H R0H R2H Subtract C from A B NOP SUBF32 completes MOV32 XAR4 R0H Store the result See also ADDF32 RaH 16FHi RbH ADDF32 RaH RbH 16FHi ADDF32 RaH RbH RcH ADDF32 RdH ReH RfH MOV32 mem32 RaH MACF32 R3H R2H RdH ReH RfH MPYF32 RaH RbH RcH ADDF32 RdH ReH RfH SPRUEO2A June 2007 Revised August 2008 Instruction Set 43 Submit Documentation ...

Page 44: ...y Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No Yes Yes No No The STF register flags are modified as follows If RaH RbH ZF 1 NF 0 If RaH RbH ZF 0 NF 0 If RaH RbH ZF 0 NF 1 Pipeline This is a single cycle instruction Example Behavior of ZF and NF flags for different comparisons MOVIZF32 R1H 2 0 R1H 2 0 0xC0000000 MOVIZF32 R0H 5...

Page 45: ...al compare operation This is possible because of the IEEE floating point format offsets the exponent Basically the bigger the binary number the bigger the floating point value Special cases for inputs Negative zero will be treated as positive zero Denormalized value will be treated as positive zero Not a Number NaN will be treated as infinity Flags This instruction modifies the following flags in ...

Page 46: ... following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No Yes Yes No No The STF register flags are modified as follows If RaH 0 0 ZF 1 NF 0 If RaH 0 0 ZF 0 NF 0 If RaH 0 0 ZF 0 NF 1 Pipeline This is a single cycle instruction Example Behavior of ZF and NF flags for different comparisons MOVIZF32 R0H 5 0 R0H 5 0 0x40A00000 MOVIZF32 R1H 2 0 R1H 2 0 0xC0000000 MOVIZF32 R2H 0 ...

Page 47: ...ing point format On each iteration the mantissa bit accuracy approximately doubles The EINVF32 operation will not generate a negative zero DeNorm or NaN value RaH Estimate of 1 RbH Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No No No Yes Yes The STF register flags are modified as follows LUF 1 if EINVF32 generates an underflow ...

Page 48: ...F32 R2H R1H R2H Ye Estimate 1 B CMPF32 R0H 0 0 Check if A 0 MPYF32 R3H R2H R1H R3H Ye B NOP SUBF32 R3H 2 0 R3H R3H 2 0 Ye B NOP MPYF32 R2H R2H R3H R2H Ye Ye 2 0 Ye B NOP MPYF32 R3H R2H R1H R3H Ye B CMPF32 R1H 0 0 Check if B 0 0 SUBF32 R3H 2 0 R3H R3H 2 0 Ye B NEGF32 R0H R0H EQ Fixes sign for A 0 0 MPYF32 R2H R2H R3H R2H Ye Ye 2 0 Ye B NOP MPYF32 R0H R0H R2H R0H Y A Ye A B LRETR See also EISQRTF32 ...

Page 49: ...loating point format On each iteration the mantissa bit accuracy approximately doubles The EISQRTF32 operation will not generate a negative zero DeNorm or NaN value RaH Estimate of 1 sqrt RbH Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No No No Yes Yes The STF register flags are modified as follows LUF 1 if EISQRTF32 generates ...

Page 50: ...H R1H R3H Ye Ye NOP MPYF32 R3H R3H R2H R3H Ye Ye X 0 5 NOP SUBF32 R3H 1 5 R3H R3H 1 5 Ye Ye X 0 5 NOP MPYF32 R1H R1H R3H R2H Ye Ye 1 5 Ye Ye X 0 5 NOP MPYF32 R3H R1H R2H R3H Ye X 0 5 NOP MPYF32 R3H R1H R3H R3H Ye Ye X 0 5 NOP SUBF32 R3H 1 5 R3H R3H 1 5 Ye Ye X 0 5 CMPF32 R0H 0 0 Check if X 0 MPYF32 R1H R1H R3H R2H Ye Ye 1 5 Ye Ye X 0 5 NOP MOV32 R1H R0H EQ If X is zero change the Ye estimate to 0 ...

Page 51: ...H 2 pipeline cycles 2p NOP 1 cycle delay or non conflicting instruction F32TOI16 completes RaH updated NOP Any instruction in the delay slot must not use RaH as a destination register or use RaH as a source operand Example MOVIZF32 R0H 5 0 R0H 5 0 0x40A00000 F32TOI16 R1H R0H R1H 15 0 F32TOI16 R0H R1H 31 16 Sign extension of R1H 15 MOVIZF32 R2H 5 0 R2H 5 0 0xC0A00000 F32TOI16 complete R1H 15 0 5 0x...

Page 52: ...cycles 2p NOP 1 cycle delay or non conflicting instruction F32TOI16R completes RaH updated NOP Any instruction in the delay slot must not use RaH as a destination register or use RaH as a source operand Example MOVIZ R0H 0x3FD9 R0H 31 16 0x3FD9 MOVXI R0H 0x999A R0H 15 0 0x999A R0H 1 7 0x3FD9999A F32TOI16R R1H R0H R1H 15 0 F32TOI16round R0H R1H 31 16 Sign extension of R1H 15 MOVF32 R2H 1 7 R2H 1 7 ...

Page 53: ...2p instruction That is F32TOI32 RaH RbH 2 pipeline cycles 2p NOP 1 cycle delay or non conflicting instruction F32TOI32 completes RaH updated NOP Any instruction in the delay slot must not use RaH as a destination register or use RaH as a source operand Example MOVF32 R2H 11204005 0 R2H 11204005 0 0x4B2AF5A5 F32TOI32 R3H R2H R3H F32TOI32 R2H MOVF32 R4H 11204005 0 R4H 11204005 0 0xCB2AF5A5 F32TOI32 ...

Page 54: ... is a 2 pipeline cycle 2p instruction That is F32TOUI16 RaH RbH 2 pipeline cycles 2p NOP 1 cycle delay or non conflicting instruction F32TOUI16 completes RaH updated NOP Any instruction in the delay slot must not use RaH as a destination register or use RaH as a source operand Example MOVIZF32 R4H 9 0 R4H 9 0 0x41100000 F32TOUI16 R5H R4H R5H 15 0 F32TOUI16 R4H R5H 31 16 0x0000 MOVIZF32 R6H 9 0 R6H...

Page 55: ... instruction That is F32TOUI16R RaH RbH 2 pipeline cycles 2p NOP 1 cycle delay or non conflicting instruction F32TOUI16R completes RaH updated NOP Any instruction in the delay slot must not use RaH as a destination register or use RaH as a source operand Example MOVIZ R5H 0x412C R5H 0x412C MOVXI R5H 0xCCCD R5H 0xCCCD R5H 10 8 0x412CCCCD F32TOUI16R R6H R5H R6H 15 0 F32TOUI16round R5H R6H 31 16 0x00...

Page 56: ...ipeline cycle 2p instruction That is F32TOUI32 RaH RbH 2 pipeline cycles 2p NOP 1 cycle delay or non conflicting instruction F32TOUI32 completes RaH updated NOP Any instruction in the delay slot must not use RaH as a destination register or use RaH as a source operand Example MOVIZF32 R6H 12 5 R6H 12 5 0x41480000 F32TOUI32 R7H R6H R7H F32TOUI32 R6H MOVIZF32 R1H 6 5 R1H 6 5 0xC0D00000 F32TOUI32 com...

Page 57: ... TF ZI NI ZF NF LUF LVF Modified No No No No No No No Pipeline This is a 2 pipeline cycle 2p instruction That is FRACF32 RaH RbH 2 pipeline cycles 2p NOP 1 cycle delay or non conflicting instruction FRACF32 completes RaH updated NOP Any instruction in the delay slot must not use RaH as a destination register or use RaH as a source operand Example MOVIZF32 R2H 19 625 R2H 19 625 0x419D0000 FRACF32 R...

Page 58: ...eline cycles 2p NOP 1 cycle delay or non conflicting instruction I16TOF32 completes RaH updated NOP Any instruction in the delay slot must not use RaH as a destination register or use RaH as a source operand Example MOVIZ R0H 0x0000 R0H 31 16 0 0 0x0000 MOVXI R0H 0x0004 R0H 15 0 4 0 0x0004 I16TOF32 R1H R0H R1H I16TOF32 R0H MOVIZ R2H 0x0000 R2H 31 16 0 0 0x0000 I16TOF32 complete R1H 4 0 0x40800000 ...

Page 59: ...instruction That is I16TOF32 RaH mem16 2 pipeline cycles 2p NOP 1 cycle delay or non conflicting instruction I16TOF32 completes RaH updated NOP Any instruction in the delay slot must not use RaH as a destination register or use RaH as a source operand Example MOVW DP 0x0280 DP 0x0280 MOV 0 0x0004 0x00A000 4 0 0x0004 I16TOF32 R0H 0 R0H I16TOF32 0x00A000 MOV 1 0xFFFC 0x00A001 4 0 0xFFFC I16TOF32 com...

Page 60: ...dified No No No No No No No Pipeline This is a 2 pipeline cycle 2p instruction That is I32TOF32 RaH mem32 2 pipeline cycles 2p NOP 1 cycle delay or non conflicting instruction I32TOF32 completes RaH updated NOP Any instruction in the delay slot must not use RaH as a destination register or use RaH as a source operand Example MOVW DP 0x0280 DP 0x0280 MOV 0 0x1111 0x00A000 4369 0x1111 MOV 1 0x1111 0...

Page 61: ...cycle 2p instruction That is I32TOF32 RaH RbH 2 pipeline cycles 2p NOP 1 cycle delay or non conflicting instruction I32TOF32 completes RaH updated NOP Any instruction in the delay slot must not use RaH as a destination register or use RaH as a source operand Example MOVIZ R2H 0x1111 R2H 31 16 4369 0x1111 MOVXI R2H 0x1111 R2H 15 0 4369 0x1111 Value of the 32 bit signed integer present in R2H is 286...

Page 62: ...uction is an alias for the parallel multiply and add MACF32 ADDF32 instruction RdH ReH RfH R3H R3H R2H Restrictions The destination register for the MPYF32 and the ADDF32 must be unique That is RdH cannot be R3H Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No No No Yes Yes The STF register flags are modified as follows LUF 1 if ...

Page 63: ...lel R0H X3 MOV32 R0H XAR4 MOV32 R1H XAR5 R1H Y3 R3H A B C R2H D X3 Y3 MACF32 R3H R2H R2H R0H R1H In parallel R0H X4 MOV32 R0H XAR4 MOV32 R1H XAR5 R1H Y4 The next MACF32 is an alias for MPYF32 ADDF32 R2H E X4 Y4 MACF32 R3H R2H R2H R0H R1H in parallel R3H A B C D NOP Wait for MPYF32 ADDF32 to complete ADDF32 R3H R3H R2H R3H A B C D E NOP Wait for ADDF32 to complete MOV32 Result R3H Store the result ...

Page 64: ...tion registers for the MACF32 R3H R3H R2H RdH ReH RfH RaH mem32 Restrictions The destination registers for the MACF32 and the MOV32 must be unique That is RaH cannot be R3H and RaH cannot be the same register as RdH Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No Yes Yes Yes Yes Yes Yes The STF register flags are modified as follows L...

Page 65: ...H R2H R2H R0H R1H In parallel R0H X3 MOV32 R0H XAR4 MOV32 R1H XAR5 R1H Y3 R3H A B C R2H D X3 Y3 MACF32 R3H R2H R2H R0H R1H In parallel R0H X4 MOV32 R0H XAR4 MOV32 R1H XAR5 R1H Y4 R2H E X4 Y4 MPYF32 R2H R0H R1H in parallel R3H A B C D ADDF32 R3H R3H R2H NOP Wait for MPYF32 ADDF32 to complete ADDF32 R3H R3H R2H R3H A B C D E NOP Wait for ADDF32 to complete MOV32 Result R3H Store the result See also ...

Page 66: ...ply Cycle 1 R3H R3H R2H R2H mem32 XAR7 Cycle 2 R7H R7H R6H R6H mem32 XAR7 Cycle 3 R3H R3H R2H R2H mem32 XAR7 Cycle 4 R7H R7H R6H R6H mem32 XAR7 etc Restrictions R2H and R6H will be used as temporary storage by this instruction Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No No No Yes Yes The STF register flags are modified as fo...

Page 67: ...ading of RPT MACF32 is allowed as long as the first and subsequent counts are even Cascading is useful for creating interruptible windows so that interrupts are not delayed too long by the RPT instruction For example ZERO R2H Zero the accumulation registers ZERO R3H and temporary multiply storage registers ZERO R6H ZERO R7H RPT 3 Execute MACF32 N 1 4 times MACF32 R7H R3H XAR6 XAR7 RPT 5 Execute MA...

Page 68: ...uction is an alias for the parallel multiply and add MACF32 ADDF32 instruction RdH RaH RbH R7H R6H R6H Restrictions The destination register for the MPYF32 and the ADDF32 must be unique That is RdH cannot be R7H Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No No No Yes Yes The STF register flags are modified as follows LUF 1 if ...

Page 69: ...allel R0H X3 MOV32 R0H XAR4 MOV32 R1H XAR5 R1H Y3 R7H A B C R6H D X3 Y3 MACF32 R7H R6H R6H R0H R1H In parallel R0H X4 MOV32 R0H XAR4 MOV32 R1H XAR5 R1H Y4 Next MACF32 is an alias for MPYF32 ADDF32 MACF32 R7H R6H R6H R0H R1H R6H E X4 Y4 in parallel R7H A B C D NOP Wait for MPYF32 ADDF32 to complete ADDF32 R7H R7H R6H R7H A B C D E NOP Wait for ADDF32 to complete MOV32 Result R7H Store the result Se...

Page 70: ...tion register for the MOV32 cannot be the same as the destination registers for the MACF32 R7H R7H R6H RdH ReH RfH RaH mem32 Restrictions The destination registers for the MACF32 and the MOV32 must be unique That is RaH cannot be R7H and RaH cannot be the same register as RdH Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No Yes Yes Yes...

Page 71: ...H A B R6H C X2 Y2 MACF32 R7H R6H R6H R0H R1H In parallel R0H X3 MOV32 R0H XAR4 MOV32 R1H XAR5 R1H Y3 R7H A B C R6H D X3 Y3 MACF32 R7H R6H R6H R0H R1H In parallel R0H X4 MOV32 R0H XAR4 MOV32 R1H XAR5 R1H Y4 R6H E X4 Y4 MPYF32 R6H R0H R1H in parallel R7H A B C D ADDF32 R7H R7H R6H NOP Wait for MPYF32 ADDF32 to complete ADDF32 R7H R7H R6H R7H A B C D E NOP Wait for ADDF32 to complete MOV32 Result R7H...

Page 72: ...Modified No No No Yes Yes No No The ZF and NF flags are configured on the result of the operation not the result stored in the destination register if RaH RbH ZF 1 NF 0 if RaH RbH ZF 0 NF 0 if RaH RbH ZF 0 NF 1 Pipeline This is a single cycle instruction Example MOVIZF32 R0H 5 0 R0H 5 0 0x40A00000 MOVIZF32 R1H 2 0 R1H 2 0 0xC0000000 MOVIZF32 R2H 1 5 R2H 1 5 0xBFC00000 MAXF32 R2H R1H R2H 1 5 ZF NF ...

Page 73: ...0000 The assembler will accept either a hex or float as the immediate value That is 1 5 can be represented as 1 5 or 0xBFC0 Special cases for the output from the MAXF32 operation NaN output will be converted to infinity A denormalized output will be converted to positive zero Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No Yes Y...

Page 74: ...ary number the bigger the floating point value Special cases for the output from the MAXF32 operation NaN output will be converted to infinity A denormalized output will be converted to positive zero Restrictions The destination register for the MAXF32 and the MOV32 must be unique That is RaH cannot be the same register as RcH Flags This instruction modifies the following flags in the STF register...

Page 75: ...TF ZI NI ZF NF LUF LVF Modified No No No Yes Yes No No The ZF and NF flags are configured on the result of the operation not the result stored in the destination register if RaH RbH ZF 1 NF 0 if RaH RbH ZF 0 NF 0 if RaH RbH ZF 0 NF 1 Pipeline This is a single cycle instruction Example MOVIZF32 R0H 5 0 R0H 5 0 0x40A00000 MOVIZF32 R1H 4 0 R1H 4 0 0x40800000 MOVIZF32 R2H 1 5 R2H 1 5 0xBFC00000 MINF32...

Page 76: ...0000 The assembler will accept either a hex or float as the immediate value That is 1 5 can be represented as 1 5 or 0xBFC0 Special cases for the output from the MINF32 operation NaN output will be converted to infinity A denormalized output will be converted to positive zero Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No Yes Y...

Page 77: ...ro Restrictions The destination register for the MINF32 and the MOV32 must be unique That is RaH cannot be the same register as RcH Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No Yes Yes No No The ZF and NF flags are configured on the result of the operation not the result stored in the destination register if RaH RbH ZF 1 NF 0...

Page 78: ...r 16 bits of the floating point register RaH 15 0 to the location pointed to by mem16 mem16 RaH 15 0 Flags No flags STF flags are affected Flag TF ZI NI ZF NF LUF LVF Modified No No No No No No No Pipeline This is a single cycle instruction Example MOVW DP 0x02C0 DP 0x02C0 MOVXI R4H 0x0003 R4H 3 0 0x0003 MOV16 0 R4H 0x00B000 3 0 0x0003 See also MOVIZ RaH 16FHiHex MOVIZF32 RaH 16FHi MOVXI RaH 16FLo...

Page 79: ...itAddr loc32 Flags This instruction does not modify any STF register flags Flag TF ZI NI ZF NF LUF LVF Modified No No No No No No No Pipeline This is a two cycle instruction Example MOVIZ R5H 0x1234 R5H 31 16 0x1234 MOVXI R5H 0xABCD R5H 15 0 0xABCD NOP 1 Alignment Cycle MOV32 ACC R5H ACC 0x1234ABCD MOV32 0xA000 ACC 0x00A000 ACC NOP 1 Cycle delay for MOV32 to complete MOV32 0 16bitAddr loc32 comple...

Page 80: ... follows a single cycle floating point instruction a single alignment cycle must be added For example MINF32 R0H R1H Single cycle instruction NOP 1 alignment cycle MOV32 ACC R0H Copy R0H to ACC NOP Any instruction If the move follows a 2 pipeline cycle floating point instruction then two alignment cycles must be used For example ADDF32 R2H R1H R0H 2 pipeline instruction 2p NOP 1 cycle delay for AD...

Page 81: ...c32 is the ACC register then the Z and N flag in status register zero ST0 of the 28x CPU are affected Flag TF ZI NI ZF NF LUF LVF Modified No No No No No No No Pipeline This is a 2 cycle instruction Example MOVW DP 0x0300 DP 0x0300 MOV 0 0xFFFF 0x00C000 0xFFFF MOV 1 0x1111 0x00C001 0x1111 MOV32 ACC 0xC000 AL 0x00C000 AH 0x00C001 NOP 1 Cycle delay for MOV32 to complete MOV32 complete AL 0xFFFF AH 0...

Page 82: ...3 5th multiply E X3 Y3 Result A B C D E MOV32 R0H XAR4 R0H X0 MOV32 R1H XAR5 R1H Y0 R6H A X0 Y0 MPYF32 R6H R0H R1H In parallel R0H X1 MOV32 R0H XAR4 MOV32 R1H XAR5 R1H Y1 R7H B X1 Y1 MPYF32 R7H R0H R1H In parallel R0H X2 MOV32 R0H XAR4 MOV32 R1H XAR5 R1H Y2 R7H A B R6H C X2 Y2 MACF32 R7H R6H R6H R0H R1H In parallel R0H X3 MOV32 R0H XAR4 MOV32 R1H XAR5 R1H Y3 R3H A B C R6H D X3 Y3 MACF32 R7H R6H R6...

Page 83: ...No No No flags affected Pipeline This is a single cycle instruction Example 1 MOVW DP 0x0280 DP 0x0280 MOVIZF32 R0H 2 0 R0H 2 0 0x40000000 MOVIZF32 R1H 3 0 R1H 3 0 0x40400000 CMPF32 R0H R1H ZF 0 NF 1 STF 0x00000004 MOV32 0 STF 0x00A000 0x00000004 Example 2 MOV32 SP STF Store STF in stack MOVF32 R2H 3 0 R2H 3 0 0x40400000 MOVF32 R3H 5 0 R3H 5 0 0x40A00000 CMPF32 R2H R3H ZF 0 NF 1 STF 0x00000004 MOV...

Page 84: ...e alignment cycle must be added For example MINF32 R0H R1H Single cycle instruction NOP 1 alignment cycle MOV32 ACC R0H Copy R0H to ACC NOP Any instruction If the move follows a 2 pipeline cycle floating point instruction then two alignment cycles must be used For example ADDF32 R2H R1H R0H 2 pipeline instruction 2p NOP 1 cycle delay for ADDF32 to complete ADDF32 completes R2H is valid NOP 1 align...

Page 85: ...tional pipeline alignment is required Four alignment cycles are required after any copy from a standard 28x CPU register to a floating point register The four alignment cycles can be filled with any non conflicting instructions except for the following FRACF32 UI16TOF32 I16TOF32 F32TOUI32 and F32TOI32 MOV32 R0H ACC Copy ACC to R0H NOP Wait 4 cycles NOP Do not use FRACF32 UI16TOF32 NOP I16TOF32 F32...

Page 86: ...Q Less than or equal to zero ZF 1 AND NF 1 1010 TF Test flag set TF 1 1011 NTF Test flag not set TF 0 1100 LU Latched underflow LUF 1 1101 LV Latched overflow LVF 1 1110 UNC Unconditional None 1111 UNCF 2 Unconditional with flag None modification 1 Values not shown are reserved 2 This is the default operation if no CNDF field is specified This condition will allow the ZF NF ZI and NI flags to be m...

Page 87: ...MOV 1 0x5555 0x00C001 0x5555 MOVIZF32 R3H 7 0 R3H 7 0 0x40E00000 MOVIZF32 R4H 7 0 R4H 7 0 0x40E00000 MAXF32 R3H R4H ZF 1 NF 0 MOV32 R1H 0 EQ R1H 0x55555555 See also MOV32 RaH RbH CNDF MOVD32 RaH mem32 SPRUEO2A June 2007 Revised August 2008 Instruction Set 87 Submit Documentation Feedback ...

Page 88: ...ignment is required Four alignment cycles are required after any copy from a standard 28x CPU register to a floating point register The four alignment cycles can be filled with any non conflicting instructions except for the following FRACF32 UI16TOF32 I16TOF32 F32TOUI32 and F32TOI32 MOV32 R0H P Copy P to R0H NOP Wait 4 alignment cycles NOP Do not use FRACF32 UI16TOF32 NOP I16TOF32 F32TOUI32 or F3...

Page 89: ... not set TF 0 1100 LU Latched underflow LUF 1 1101 LV Latched overflow LVF 1 1110 UNC Unconditional None 1111 UNCF 2 Unconditional with flag None modification 1 Values not shown are reserved 2 This is the default operation if no CNDF field is specified This condition will allow the ZF NF ZI and NI flags to be modified when a conditional operation is executed All other conditions will not modify th...

Page 90: ...ine alignment is required Four alignment cycles are required after any copy from a standard 28x CPU register to a floating point register The four alignment cycles can be filled with any non conflicting instructions except for the following FRACF32 UI16TOF32 I16TOF32 F32TOUI32 and F32TOI32 MOV32 R0H XAR7 Copy XAR7 to R0H NOP Wait 4 alignment cycles NOP Do not use FRACF32 UI16TOF32 NOP I16TOF32 F32...

Page 91: ...equired Four alignment cycles are required after any copy from a standard 28x CPU register to a floating point register The four alignment cycles can be filled with any non conflicting instructions except for the following FRACF32 UI16TOF32 I16TOF32 F32TOUI32 and F32TOI32 MOV32 R0H XT Copy XT to R0H NOP Wait 4 alignment cycles NOP Do not use FRACF32 UI16TOF32 NOP I16TOF32 F32TOUI32 or F32TOI32 NOP...

Page 92: ...I ZF NF LUF LVF Modified Yes Yes Yes Yes Yes Yes Yes Restoring status register will overwrite all flags Pipeline This is a single cycle instruction Example 1 MOVW DP 0x0300 DP 0x0300 MOV 2 0x020C 0x00C002 0x020C MOV 3 0x0000 0x00C003 0x0000 MOV32 STF 2 STF 0x0000020C Example 2 MOV32 SP STF Store STF in stack MOVF32 R2H 3 0 R2H 3 0 0x40400000 MOVF32 R3H 5 0 R3H 5 0 0x40A00000 CMPF32 R2H R3H ZF 0 NF...

Page 93: ...point instruction a single alignment cycle must be added For example MINF32 R0H R1H Single cycle instruction NOP 1 alignment cycle MOV32 ACC R0H Copy R0H to ACC NOP Any instruction If the move follows a 2 pipeline cycle floating point instruction then two alignment cycles must be used For example ADDF32 R2H R1H R0H 2 pipeline instruction 2p NOP 1 cycle delay for ADDF32 to complete ADDF32 completes...

Page 94: ...e alignment cycle must be added For example MINF32 R0H R1H Single cycle instruction NOP 1 alignment cycle MOV32 XT R0H Copy R0H to ACC NOP Any instruction If the move follows a 2 pipeline cycle floating point instruction then two alignment cycles must be used For example ADDF32 R2H R1H R0H 2 pipeline instruction 2p NOP 1 cycle delay for ADDF32 to complete ADDF32 completes R2H is valid NOP 1 alignm...

Page 95: ...H mem32 mem32 2 mem32 Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No Yes Yes Yes Yes No No NF RaH 31 ZF 0 if RaH 30 23 0 ZF 1 NF 0 NI RaH 31 ZI 0 if RaH 31 0 0 ZI 1 Pipeline This is a single cycle instruction Example MOVW DP 0x02C0 DP 0x02C0 MOV 2 0x0000 0x00B002 0x0000 MOV 3 0x4110 0x00B003 0x4110 MOVD32 R7H 2 R7H 0x41100000 0x00B00...

Page 96: ...er will only accept a float value represented in floating point representation That is 3 0 can only be represented as 3 0 0x40400000 will result in an error RaH 32F Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No No No No No Pipeline Depending on 32FH this instruction takes one or two cycles If all of the lower 16 bits of the IE...

Page 97: ...ting point number The assembler will only accept a hex immediate value That is 3 0 can only be represented as 0x40400000 3 0 will result in an error RaH 32FHex Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No No No No No Pipeline Depending on 32FHex this instruction takes one or two cycles If all of the lower 16 bits of 32FHex ar...

Page 98: ...are assumed to be all 0 The assembler will only accept a hex immediate value That is 1 5 can only be represented as 0xBFC0 1 5 will result in an error By itself MOVIZ is useful for loading a floating point register with a constant in which the lowest 16 bits of the mantissa are 0 Some examples are 2 0 0x40000000 4 0 0x40800000 0 5 0x3F000000 and 1 5 0xBFC00000 If a constant requires all 32 bits of...

Page 99: ...x or float That is 1 5 can be represented as 1 5 or 0xBFC0 MOVIZF32 is an alias for the MOVIZ RaH 16FHiHex instruction In the case of MOVIZF32 the assembler will accept either a hex or float as the immediate value and encodes it into a MOVIZ instruction For example MOVIZF32 RaH 1 5 will be encoded as MOVIZ RaH 0xBFC0 RaH 31 16 16FHi RaH 15 0 0 Flags This instruction modifies the following flags in...

Page 100: ...he following is VALID MPYF32 R2H R1H R0H 2 pipeline cycle instruction 2p NOP 1 delay cycle R2H updated after this instruction MOVST0 TF VALID Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No No No Yes Yes When the flags are moved to the C28x ST0 register the LUF or LVF flags are automatically cleared if selected Pipeline This is ...

Page 101: ...6FLoHex 16FLoHex represents the lower 16 bits of an IEEE 32 bit floating point value The upper 16 bits of RaH will not be modified MOVXI can be combined with the MOVIZ or MOVIZF32 instruction to initialize all 32 bits of a RaH register RaH 15 0 16FLoHex RaH 31 16 Unchanged Flags Flag TF ZI NI ZF NF LUF LVF Modified No No No No No No No Pipeline This is a single cycle instruction Example Load R0H w...

Page 102: ... overflow condition Pipeline This is a 2 pipeline cycle 2p instruction That is MPYF32 RaH RbH RcH 2 pipeline cycles 2p NOP 1 cycle delay or non conflicting instruction MPYF32 completes RaH updated NOP Any instruction in the delay slot must not use RaH as a destination register or use RaH as a source operand Example Calculate Y A B MOVL XAR4 A MOV32 R0H XAR4 Load R0H with A MOVL XAR4 B MOV32 R1H XA...

Page 103: ...This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No No No Yes Yes The STF register flags are modified as follows LUF 1 if MPYF32 generates an underflow condition LVF 1 if MPYF32 generates an overflow condition Pipeline This is a 2 pipeline cycle 2p instruction That is MPYF32 RaH 16FHi RbH 2 pipeline cycles 2p NOP 1 cycle delay or non conf...

Page 104: ...H 16FHi RbH Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No No No Yes Yes The STF register flags are modified as follows LUF 1 if MPYF32 generates an underflow condition LVF 1 if MPYF32 generates an overflow condition Pipeline This is a 2 pipeline cycle 2p instruction That is MPYF32 RaH RbH 16FHi 2 pipeline cycles 2p NOP 1 cycle...

Page 105: ...fH This instruction can also be written as MACF32 RaH RbH RcH RdH ReH RfH Restrictions The destination register for the MPYF32 and the ADDF32 must be unique That is RaH cannot be the same register as RdH Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No No No Yes Yes The STF register flags are modified as follows LUF 1 if MPYF32 o...

Page 106: ...2H R2H R0H R1H In parallel R0H X3 MOV32 R0H XAR4 MOV32 R1H XAR5 R1H Y3 R3H A B C R2H D X3 Y3 MACF32 R3H R2H R2H R0H R1H In parallel R0H X4 MOV32 R0H XAR4 MOV32 R1H XAR5 R1H Y4 R2H E X4 Y4 MPYF32 R2H R0H R1H in parallel R3H A B C D ADDF32 R3H R3H R2H NOP Wait for MPYF32 ADDF32 to complete ADDF32 R3H R3H R2H R3H A B C D E NOP Wait for ADDF32 to complete MOV32 Result R3H Store the result See also MAC...

Page 107: ...d the MOV32 must be unique That is RaH cannot be the same register as RdH Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No Yes Yes Yes Yes Yes Yes The STF register flags are modified as follows LUF 1 if MPYF32 generates an underflow condition LVF 1 if MPYF32 generates an overflow condition The MOV32 Instruction will set the NF ZF NI an...

Page 108: ...complete ADDF32 complete MOV32 Y1 R1H Store the result Calculate Y A B C MOVL XAR4 A MOV32 R0H XAR4 Load ROH with A MOVL XAR4 B MOV32 R1H XAR4 Load R1H with B MOVL XAR4 C MPYF32 R1H R1H R0H Calculate R1H A B MOV32 R0H XAR4 and in parallel load R2H with C MOV32 complete MOVL XAR4 Y MPYF32 complete MPYF32 R2H R1H R0H Calculate Y A B C NOP Wait 1 cycle for MPYF32 to complete MPYF32 complete MOV32 XAR...

Page 109: ...low condition LVF 1 if MPYF32 generates an overflow condition Pipeline MPYF32 takes 2 pipeline cycles 2p and MOV32 takes a single cycle That is MPYF32 RdH ReH RfH 2 pipeline cycles 2p MOV32 mem32 RaH 1 cycle MOV32 completes mem32 updated NOP 1 cycle delay or non conflicting instruction MPYF32 completes RdH updated NOP Any instruction in the delay slot must not use RdH as a destination register or ...

Page 110: ...ags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No No No Yes Yes The STF register flags are modified as follows LUF 1 if MPYF32 or SUBF32 generates an underflow condition LVF 1 if MPYF32 or SUBF32 generates an overflow condition Pipeline MPYF32 and SUBF32 both take 2 pipeline cycles 2p That is MPYF32 RaH RbH RcH 2 pipeline cycles 2p ...

Page 111: ...1110 UNC Unconditional None 1111 UNCF 2 Unconditional with flag None modification 1 Values not shown are reserved 2 This is the default operation if no CNDF field is specified This condition will allow the ZF NF ZI and NI flags to be modified when a conditional operation is executed All other conditions will not modify these flags Flags This instruction modifies the following flags in the STF regi...

Page 112: ...lude a RPTB block then you do not have to save the RB register Repeat Block within a High Priority Interrupt Non Interruptible _Interrupt RAS RA RA 0 PUSH RB Save RB register only if a RPTB block is used in the ISR RPTB BlockEnd AL Execute the block AL 1 times BlockEnd End of block to be repeated POP RB Restore RB register IRET RA RAS RAS 0 A low priority interrupt is defined as an interrupt that ...

Page 113: ...rvice routine does not include a RPTB block then you do not have to save the RB register Repeat Block within a High Priority Interrupt Non Interruptible _Interrupt RAS RA RA 0 PUSH RB Save RB register only if a RPTB block is used in the ISR RPTB BlockEnd AL Execute the block AL 1 times BlockEnd End of block to be repeated POP RB Restore RB register IRET RA RAS RAS 0 A low priority interrupt is def...

Page 114: ...be used in any delay slots for pipelined operations Doing so will yield invalid results To avoid this the proper number of NOPs or non pipelined instructions must be inserted before the RESTORE operation The following is INVALID MPYF32 R2H R1H R0H 2 pipeline cycle instruction 2p RESTORE INVALID do not use RESTORE in a delay slot The following is VALID MPYF32 R2H R1H R0H 2 pipeline cycle instructio...

Page 115: ...erruptable ASP Align stack PUSH RB Save RB register if used in the ISR PUSH AR1H AR0H Save other registers if used PUSH XAR2 PUSH XAR3 PUSH XAR4 PUSH XAR5 PUSH XAR6 PUSH XAR7 PUSH XT SPM 0 Set default C28 modes CLRC AMODE CLRC PAGE0 OVM SAVE RNDF32 1 Save all FPU registers set default FPU modes Interrupt Restore RESTORE Restore all FPU registers POP XT restore other registers POP XAR7 POP XAR6 POP...

Page 116: ...ven aligned and 9 words if the block is odd aligned If you have a block of 8 words as in the following example you can make sure the block is odd aligned by proceeding it by a align 2 directive and a NOP instruction The align 2 directive will make sure the NOP is even aligned Since a NOP is a 16 bit instruction the RPTB will be odd aligned For blocks of 9 or more words this is not required Repeat ...

Page 117: ...gister must always be saved and restored in a low priority interrupt The RB register must stored before interrupts are enabled Likewise before restoring the RB register interrupts must first be disabled Repeat Block within a Low Priority Interrupt Interruptible Interrupt RAS RA RA 0 PUSH RB Always save RB register CLRC INTM Enable interrupts only after saving RB ISR may or may not include a RPTB b...

Page 118: ...if the block is even aligned and 9 words if the block is odd aligned If you have a block of 8 words as in the following example you can make sure the block is odd aligned by proceeding it by a align 2 directive and a NOP instruction The align 2 directive will make sure the NOP is even aligned Since a NOP is a 16 bit instruction the RPTB will be odd aligned For blocks of 9 or more words this is not...

Page 119: ...ter must always be saved and restored in a low priority interrupt The RB register must stored before interrupts are enabled Likewise before restoring the RB register interrupts must first be disabled Repeat Block within a Low Priority Interrupt Interruptible Interrupt RAS RA RA 0 PUSH RB Always save RB register CLRC INTM Enable interrupts only after saving RB ISR may or may not include a RPTB bloc...

Page 120: ... proper number of NOPs or non pipelined instructions must be inserted before the SAVE operation The following is INVALID MPYF32 R2H R1H R0H 2 pipeline cycle instruction 2p SAVE RNDF32 1 INVALID do not use SAVE in a delay slot The following is VALID MPYF32 R2H R1H R0H 2 pipeline cycle instruction 2p NOP 1 delay cycle R2H updated after this instruction SAVE RNDF32 1 VALID Flags This instruction modi...

Page 121: ...ault C28 modes CLRC AMODE CLRC PAGE0 OVM SAVE RNDF32 0 Save all FPU registers set default FPU modes RESTORE Restore all FPU registers POP XT restore other registers POP XAR7 POP XAR6 POP XAR5 POP XAR4 POP XAR3 POP XAR2 POP AR1H AR0H POP RB restore RB register NASP un align stack IRET return from interrupt See also RESTORE SETFLG FLAG VALUE SPRUEO2A June 2007 Revised August 2008 Instruction Set 121...

Page 122: ...ing so can yield invalid results To avoid this the proper number of NOPs or non pipelined instructions must be inserted before the SETFLG operation The following is INVALID MPYF32 R2H R1H R0H 2 pipeline cycle instruction 2p SETFLG RNDF32 1 INVALID do not use SETFLG in a delay slot The following is VALID MPYF32 R2H R1H R0H 2 pipeline cycle instruction 2p NOP 1 delay cycle R2H updated after this ins...

Page 123: ...eline This is a 2 pipeline cycle 2p instruction That is SUBF32 RaH RbH RcH 2 pipeline cycles 2p NOP 1 cycle delay or non conflicting instruction SUBF32 completes RaH updated NOP Any instruction in the delay slot must not use RaH as a destination register or as a source operand Example Calculate Y A B C MOVL XAR4 A MOV32 R0H XAR4 Load R0H with A MOVL XAR4 B MOV32 R1H XAR4 Load R1H with B MOVL XAR4 ...

Page 124: ... value That is the value 1 5 can be represented as 1 5 or 0xBFC0 RaH 16FHi 0 RbH Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No No No No No Yes Yes The STF register flags are modified as follows LUF 1 if MPYF32 generates an underflow condition LVF 1 if MPYF32 generates an overflow condition Pipeline This is a 2 pipeline cycle 2p inst...

Page 125: ...on register for the SUBF32 and the MOV32 must be unique That is RaH cannot be the same register as RdH Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF LUF LVF Modified No Yes Yes Yes Yes Yes Yes The STF register flags are modified as follows LUF 1 if SUBF32 generates an underflow condition LVF 1 if SUBF32 generates an overflow condition The MOV32 Instruc...

Page 126: ...2 A completes R0H valid R4H valid ADDF32 R5H R4H R3H B R5H R4H R3H MOV32 XAR1 4 R0H R0H stored MOVL XAR2 0xE000 B completes R5H valid MOV32 XAR2 R5H R5H stored See also SUBF32 RaH RbH RcH SUBF32 RaH 16FHi RbH MPYF32 RaH RbH RcH SUBF32 RdH ReH RfH Instruction Set 126 SPRUEO2A June 2007 Revised August 2008 Submit Documentation Feedback ...

Page 127: ...F 1 if SUBF32 generates an overflow condition Pipeline SUBF32 is a 2 pipeline cycle instruction 2p and MOV32 takes a single cycle That is SUBF32 RdH ReH RfH 2 pipeline cycles 2p MOV32 mem32 RaH 1 cycle MOV32 completes mem32 updated NOP 1 cycle delay or non conflicting instruction ADDF32 completes RdH updated NOP Any instruction in the delay slot must not use RdH as a destination register or as a s...

Page 128: ...e 1111 UNCF 2 Unconditional with flag None modification 1 Values not shown are reserved 2 This is the default operation if no CNDF field is specified This condition will allow the ZF NF ZI and NI flags to be modified when a conditional operation is executed All other conditions will not modify these flags Flags This instruction modifies the following flags in the STF register Flag TF ZI NI ZF NF L...

Page 129: ...verflow LVF 1 1110 UNC Unconditional None 1111 UNCF 2 Unconditional with flag None modification 1 Values not shown are reserved 2 This is the default operation if no CNDF field is specified This condition will allow the ZF NF ZI and NI flags to be modified when a conditional operation is executed All other conditions will not modify these flags Flags This instruction modifies the following flags i...

Page 130: ...UI16TOF32 RaH mem16 2 pipeline cycles 2p NOP 1 cycle delay or non conflicting instruction UI16TOF32 completes RaH updated NOP Any instruction in the delay slot must not use RaH as a destination register or as a source operand Example float32 y m b AdcRegs RESULT0 is an unsigned int Calculate y float AdcRegs ADCRESULT0 m b MOVW DP 0x01C4 UI16TOF32 R0H 8 R0H float AdcRegs RESULT0 MOV32 R1H SP 6 R1H ...

Page 131: ...ZI NI ZF NF LUF LVF Modified No No No No No No No Pipeline This is a 2 pipeline cycle 2p instruction That is UI16TOF32 RaH RbH 2 pipeline cycles 2p NOP 1 cycle delay or non conflicting instruction UI16TOF32 completes RaH updated NOP Any instruction in the delay slot must not use RaH as a destination register or as a source operand Example MOVXI R5H 0x800F R5H 15 0 32783 0x800F UI16TOF32 R6H R5H R6...

Page 132: ...ine cycles 2p NOP 1 cycle delay non conflicting instruction UI32TOF32 completes RaH updated NOP Any instruction in the delay slot must not use RaH as a destination register or as a source operand Example unsigned long X float Y M B Calculate Y float X M B UI32TOF32 R0H SP 2 R0H float X MOV32 R1H SP 6 R1H M Conversion complete R0H valid MPYF32 R0H R1H R0H R0H float X M MOV32 R1H SP 8 R1H B MPYF32 c...

Page 133: ...cle 2p instruction That is UI32TOF32 RaH RbH 2 pipeline cycles 2p NOP 1 cycle delay or non conflicting instruction UI32TOF32 completes RaH updated NOP Any instruction in the delay slot must not use RaH as a destination register or as a source operand Example MOVIZ R3H 0x8000 R3H 31 16 0x8000 MOVXI R3H 0x1111 R3H 15 0 0x1111 R3H 2147488017 UI32TOF32 R4H R3H R4H UI32TOF32 R3H NOP 1 cycle delay for U...

Page 134: ...2 i y 2 i 1 x 2 i 1 y 2 i Assume AR7 n 1 ZERO R4H R4H real 0 ZERO R5H R5H imag 0 LOOP MOV AL AR7 MOV ACC AL 2 MOV AR0 ACC MOV32 R0H XAR4 AR0 R0H x 2 i MOV32 R1H XAR5 AR0 R1H y 2 i ADD AR0 2 MPYF32 R6H R0H R1H R6H x 2 i y 2 i MOV32 R2H XAR4 AR0 R2H x 2 i 1 MPYF32 R1H R1H R2H R1H y 2 i x 2 i 2 MOV32 R3H XAR5 AR0 R3H y 2 i 1 MPYF32 R2H R2H R3H R2H x 2 i 1 y 2 i 1 ADDF32 R4H R4H R6H R4H x 2 i y 2 i MP...

Page 135: ...2 i y 2 i 1 x 2 i 1 y 2 i Assume AR7 n 1 ZER0A Clear all RaH registers LOOP MOV AL AR7 MOV ACC AL 2 MOV AR0 ACC MOV32 R0H XAR4 AR0 R0H x 2 i MOV32 R1H XAR5 AR0 R1H y 2 i ADD AR0 2 MPYF32 R6H R0H R1H R6H x 2 i y 2 i MOV32 R2H XAR4 AR0 R2H x 2 i 1 MPYF32 R1H R1H R2H R1H y 2 i x 2 i 2 MOV32 R3H XAR5 AR0 R3H y 2 i 1 MPYF32 R2H R2H R3H R2H x 2 i 1 y 2 i 1 ADDF32 R4H R4H R6H R4H x 2 i y 2 i MPYF32 R0H R...

Page 136: ...Instruction Set 136 SPRUEO2A June 2007 Revised August 2008 Submit Documentation Feedback ...

Page 137: ...tion MAXF32 RaH 16FHi Modifed the syntax of the immediate operand Modified the desciption MINF32 RaH 16FHi Modified the syntax of the immediate operand Modified the description MINF32 RaH RbH Modified the MINF32 RaH RbH instruction MOV16 mem16 RaH Modified the MOV16 mem16 RaH instruction MOV32 loc32 0 16bitAddr Modified the MOV32 loc32 0 16bitAddr instruction MOV32 mem32 RaH Modified the MOV32 mem...

Page 138: ...iate addressing modes modes were changed to 16FHi 16FHiHex and 16FLoHex to be more descriptive and consistent The descriptions for instructions using these modes were updated for clarity Example 2 2 Changed first instruction in example Table 4 1 Updated the operand nomenclature table Section 2 1 2 Modified the register figure introduction and register figure EINVF32 RaH RbH Modified the example EI...

Page 139: ...usiness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all neces...

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