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B6
B7
DR
CLKR
Data hold
Á
Á
Á
Á
Data setup
Internal
Figure 15-48. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a
Falling Edge
Set the SRG Frame-Synchronization Period and Pulse Width.
15.7.16.2 Frame-Synchronization Period and the Frame-Synchronization Pulse Width
The sample rate generator can produce a clock signal, CLKG, and a frame-synchronization signal, FSG. If the
sample rate generator is supplying receive or transmit frame synchronization, you must program the bit fields
FPER and FWID.
On FSG, the period from the start of a frame-synchronization pulse to the start of the next pulse is (FPER + 1)
CLKG cycles. The 12 bits of FPER allow a frame-synchronization period of 1 to 4096 CLKG cycles, which allows
up to 4096 data bits per frame. When GSYNC = 1, FPER is a don't care value.
Each pulse on FSG has a width of (FWID + 1) CLKG cycles. The eight bits of FWID allow a pulse width of 1
to 256 CLKG cycles. It is recommended that FWID be programmed to a value less than the programmed word
length.
The values in FPER and FWID are loaded into separate down-counters. The 12-bit FPER counter counts down
the generated clock cycles from the programmed value (4095 maximum) to 0. The 8-bit FWID counter counts
down from the programmed value (255 maximum) to 0.
shows settings for FPER and FWID.
shows a frame-synchronization period of 16 CLKG periods (FPER = 15 or 00001111b) and a
frame-synchronization pulse with an active width of 2 CLKG periods (FWID = 1).
Table 15-39. Register Bits Used to Set the SRG Frame-Synchronization Period and Pulse Width
Register
Bit
Name
Function
Type
Reset Value
SRGR2
11-0
FPER
Sample rate generator frame-synchronization period
R/W
0000 0000 0000
For the frame-synchronization signal FSG, (FPER +
1) determines the period from the start of a frame-
synchronization pulse to the start of the next frame-
synchronization pulse.
Range for (FPER + 1):
1 to 4096 CLKG cycles
SRGR1
15-8
FWID
Sample rate generator frame-synchronization pulse width
R/W
0000 0000
This field plus 1 determines the width of each frame-
synchronization pulse on FSG.
Range for (FWID + 1):
1 to 256 CLKG cycles
FSG
CLKG
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Frame-synchronization pulse width: (FWID + 1) x CLKG
Frame-synchronization period: (FPER+1) x CLKG
Figure 15-49. Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods
When the sample rate generator comes out of reset, FSG is in its inactive state. Then, when GRST = 1 and
FSGM = 1, a frame-synchronization pulse is generated. The frame width value (FWID + 1) is counted down on
Multichannel Buffered Serial Port (McBSP)
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
TMS320x2806x Microcontrollers
933
Copyright © 2022 Texas Instruments Incorporated
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