10.2.2 CLA Memory Bus
The CLA has dedicated bus architecture similar to that of the C28x CPU where there are separate program read,
data read, and data write buses. Thus, there can be simultaneous instruction fetch, data read, and data write in
a single cycle. Like the C28x CPU, the CLA expects memory logic to align any 32-bit read or write to an even
address. If the address-generation logic generates an odd address, the CLA will begin reading or writing at the
previous even address. This alignment does not affect the address values generated by the address-generation
logic.
•
CLA Program Bus
The CLA program bus has an access range of 2048 32-bit instructions. Since all CLA instructions are 32
bits, this bus always fetches 32 bits at a time and the opcodes must be even-word aligned. The amount of
program space available for the CLA is limited to the number of allocated memory blocks. This number is
device-dependent and will be described in the device-specific data manual.
•
CLA Data Read Bus
The CLA data read bus has a 64K x 16 address range. The bus can perform 16 or 32-bit reads and will
automatically stall if there are memory access conflicts. The data read bus has access to both the message
RAMs, CLA data memory, and the shared peripherals.
•
CLA Data Write Bus
The CLA data write bus has a 64K x 16 address range. This bus can perform 16 or 32-bit writes. The bus
will automatically stall if there are memory access conflicts. The data write bus has access to the CLA to CPU
message RAM, CLA data memory, and the shared peripherals.
10.2.3 Shared Peripherals and EALLOW Protection
The CPU and CLA share access to some peripherals. describes the arbitration between the CPU and CLA.
Refer to the device data sheet for the list of peripherals connected to the bus.
Several peripheral control registers are protected from spurious 28x CPU writes by the EALLOW protection
mechanism. These same registers are also protected from spurious CLA writes. The EALLOW bit in the CPU
status register 1 (ST1) indicates the state of protection for the CPU. Likewise the MEALLOW bit in the CLA
status register (MSTF) indicates the state of write protection for the CLA. The MEALLOW CLA instruction
enables write access by the CLA to EALLOW protected registers. Likewise the MEDIS CLA instruction will
disable write access. This way the CLA can enable/disable write access independent of the CPU.
The ADC offers the option to generate an early interrupt pulse at the start of a sample conversion. If this option
is used to start an ADC-triggered CLA task, the user may use the intervening cycles, until the completion of the
conversion, to perform preliminary calculations or loads and stores before finally reading the ADC value. The
CLA pipeline activity for this scenario is shown in
.
Control Law Accelerator (CLA)
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
TMS320x2806x Microcontrollers
573
Copyright © 2022 Texas Instruments Incorporated
Summary of Contents for TMS320 2806 Series
Page 2: ......
