DV_ENABLE
TAS_SCL
TAS_SDA
MCLK
BCLK1
WCLK1
DOUT1
DIN1
TAS_MISO
TAS_MOSI
TAS_SSz
TAS_SCLK
I2S_ENABLE
RESETz
BCLK2
WCLK2
DOUT2
DIN2
BCLK2
WCLK2
DOUT2
DIN2
TAS_BCLK
TAS_WCLK
TAS_DOUT
TAS_DIN
GPIO3
GPIO4
IN1L
IN1R
IN2L
IN2R
IN3R
IN3L
IN4L
IN4R
MICBIAS
MICBIAS_EXT
HS_MIC
SPKP
SPKM
SPKM
SPKP
RECP
RECM
LLOUT
RLOUT
HPL
HPR
AV_ENABLE
GPIO5
GPIO1
GPIO2
GND
GND
VARVD
VARVD
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
69
67
65
63
61
59
57
55
53
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
J11
mfg: JST
p/n: 100P-JMDSS-G-1-TF(LF)(SN)
100
98
96
94
92
90
88
86
84
76
74
72
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
99
97
95
93
91
89
87
85
83
73
71
69
67
65
63
61
59
57
55
53
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
75
77
79
81
78
80
82
J12
mfg: JST
p/n: 100P-JMDSS-G-1-TF(LF)(SN)
S03
0.5in
0.5in
S02
0.5in
0.5in
S05
0.5in
0.5in
S04
0.5in
0.5in
S07
0.5in
0.5in
S01
0.5in
0.5in
S06
0.5in
0.5in
S08
0.5in
0.5in
L;DN
11
C
C
JOHN FEDAK IV
JANUARY 31, 2014
AIP013C_Schematic.sbk
DESIGN LEAD
PAGE INFO:
FILENAME
DATE
OF
DRAWN BY
SHEET
PCB REV
SCH REV
TI
GND
GND
+1.8V_CP
+3.3VD
GND
GND
+5V
+5V
+1.8V
+1.8V
+3.3VD
+3.3VD
GND
J12
Anchor
J11
Anchor
TLV320AIC3268RGC EVALUATION BOARD
9
RESERVED
RESERVED
I2S_4
I2S_3
GPIO
DGND
I2S_ENABLE
DGND
I2S1
DGND
MCLK
I2C
RESERVED
RESERVED
DV_ENABLE
VARVD
VARVD
+1.8VD
+1.8IO
+3.3IO
+3.0IO
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
+5VD
+5VD
IN8-
IN7-
IN6-
IN5-
IN4-
IN3-
IN1-
IN2-
MICDET
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
IN8+
IN7+
IN6+
IN5+
IN4+
IN3+
IN1+
IN2+
MICBIAS
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
SPK1+
SPK1-
SPK2+
SPK2-
CLASS-D
SPEAKER
OUTPUT
CLASS-D
SPEAKER
OUTPUT
SPK2-
SPK2+
SPK1-
SPK1+
HEADSET
GROUND
HPGND
HPGND
HPGND
HPGND
LINE
OUTPUTS
OUT1GND
OUT1+
OUT2+
OUT2GND
OUT3+
OUT3GND
OUT4GND
OUT4+
AGND
HP2L
HP2R
HP1R
OUT4-
OUT4GND
HP1L
HEADSET
OUTPUTS
AGND
OUT3GND
OUT3-
OUT2GND
OUT2-
OUT1-
OUT1GND
LINE
OUTPUTS
AGND
VARVA
BREAK-OUT CONNECTIONS
BREAK-OUT CONNECTIONS
ANALOG INTERFACE CONNECTOR
STANDOFFS
+5VA
AGND
+3.3VA
AGND
+1.8V_CP
AGND
VARVA
AGND
AGND
+1.8VA
AGND
+3.3VA
AGND
+5VA
BREAK-OUT CONNECTIONS
BREAK-OUT CONNECTIONS
DIGITAL INTERFACE CONNECTOR
AV_ENABLE
HPVDD
HPGND
RESERVED
HPGND
HPVDD
SPKVDD
SPKVDD
SPKGND
SPKGND
RESERVED
MCLK
SPI
RESET
I2S_2
RESERVED
BREAKOUT BOARD CONNECTIONS
TLV320AIC3268EVM-U EVM Schematics
Figure 13. Breakout Board Connections
16
TLV320AIC3268EVM-U Evaluation Module
SLAU564A – February 2014 – Revised February 2014
Copyright © 2014, Texas Instruments Incorporated