Digital Output
2-4
2.1.6
User Supplied Input Circuit
A breadboarding area allows the use of custom input filters or other signal
conditioning circuits. To route the input signal to the breadboarding area
(terminal E24), solder a jumper between terminals E5 and E6.
To route the signal from the breadboard area (terminal E25) to the
TLC5540/TLC5510/TLC5510A input, solder a jumper between terminals E11
and E12.
Only one of the above configurations should be used at one time to prevent
excessive capacitance on the signal path. This excessive capacitance can
degrade the input signal quality at high frequencies.
2.2
Digital Output
An octal high-speed latch (U4) provides buffered digital data. The factory con-
figuration uses this latch as a buffer to drive the 22-ohm line damping resistors.
Pin 24 on the output connector (J5) can be used to drive the U4 output to a high
impedance (3-state) allowing a bus interface to external circuitry. To do so, the
jumper between terminals E17 and E18 must be removed to eliminate the
ground connection. Logic 1 applied to J5 pin 24 makes the latch output a
3-state output.
This latch can be transparent by using external circuitry to drive the strobe
input (pin 11). The jumper at E19 and E20 must be removed and the external
drive be connected to E19. A logic 0 on this input captures and holds the input
data on the output. A logic 1 allows the outputs to follow the inputs.
2.3
Clock Circuit
An external clock of up to 40 MHz is required for operation. The clock source
is required to drive the 50-
Ω
BNC input J1. If the clock signal comes from a DSP
or microcontroller, resistor R1 should be removed from the circuit. The clock
is buffered by inverters (U1) and provides a true (noninverted) output to the
TLC5540/TLC5510/TLC5510A and a true equivalent output at pin 22 of the
output connector J5. This provides the user a buffered reference clock output
for external circuitry.
2.4
Board Schematic
Figure 2–1 shows the EVM board schematic.
