Processor
MAC
Ethernet PHY
OS
IEEE1588 code
(Application layer)
4
3
2
1
Hardware assist
System Overview
9
JAJU324B – March 2015 – Revised July 2017
翻訳版
—
最新の英語版資料
http://www-s.ti.com/sc/techlit/TIDU832
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2.2.3
IEEE 1588v2
Precise time information is important, especially for distributed systems like in factory automation. The
IEEE 1588v2 is an IEEE standard for precision clock synchronization protocol for networked measurement
and control systems. The protocol is used to synchronize the time and clock frequency. It defines a way to
provide sub-microsecond precision synchronization.
To define this synchronization, the start of package detection is needed. Depending on which application
layer this detection happens, the timing error varies. The lower the layer, the smaller the error.
図
図
3. Options 1 to 4 for Time Stamp versus Layer
The closer to the PHY the time stamp is set the better the time reference. The time stamp consists of two
signals the Ingress (RX) and Egress (TX) time stamp. Depending on when the time stamp is done, the
delay can vary from nanoseconds to microseconds.
2.3
System Design Theory
2.3.1
Circuit Design and Component Selection
2.3.1.1
DP83867IR 10/100/1000-Mb/s Gigabit Ethernet PHY
The DP83867IR was selected due to following features:
•
IEEE 802.3ab 1000BASE-T compliant
•
Operating temperature range –40°C to 85°C
•
8-kV IEC 61000-4-2 ESD protection (direct contact)
•
RGMII with software (register) programmable and hardware configurable (strap resistors) clock skew
•
Integrated termination resistors
•
Low power: 565 mW
•
SOF detect for IEEE 1588 time stamp
In addition to the above features, the DP83867IR also offers the following features:
•
Low deterministic TX and RX latency
•
Wake on LAN (WoL)
