U15
GND via to ensure GND
matching when changing layers
on signals
Clearance between data and data lines
and clock and data lines
Length matching for RGMII TX
on layer 6
Termination for RGMII TX on top layer
U15
Rev E1
Rev E3
Design Files
77
JAJU324B – March 2015 – Revised July 2017
翻訳版
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6.4.2
Layout RGMII Signals
Looking at the layout, each RX or TX group of the RGMII signals are routed on the same layer with
matched trace length as outlined in
.
The goal for routing the signals is to minimize the trace length of both RGMII 1 and RGMII 2 interfaces,
which is done using the following considerations.
The RGMII interface is a 125-MHz signal, which gives a full clock cycle of 8 ns.
The typical propagation delay in a FR4 stripline is 7.087 ns/mm, which means that the length of the RGMII
interface introduces a delay that should be kept as small as possible. For the RGMII signal below 0.5 ns,
this should be a delay that can be ignored. So the signal can be around 63.5-mm long, maximum.
A second important point is that when changing layers, a GND via is added next to the signal via to
ensure a good matching as well offer a current return path close to the signal.
The PCB signals are impedance controlled to 50
Ω
, and have series line termination. For the series
termination at both the PHYs, 0-
Ω
resistors were chosen due to the DP83867IR internal 50-
Ω
impedance.
These resistors were only added for test and debug. For the AM3359, 22-
Ω
series termination resistors
were chosen.
図
図
71. Layout Guidelines for RGMII TX Signals Comparing E1 and E3
