System Overview
20
JAJU324B – March 2015 – Revised July 2017
翻訳版
—
最新の英語版資料
http://www-s.ti.com/sc/techlit/TIDU832
Copyright © 2015–2017, Texas Instruments Incorporated
EMI/EMC
規格準拠、産業用温度範囲のデュアルポート・ギガビット・イーサネットの
リファレンス・デザイン
Termination was done with parallel termination of 47
Ω
to improve performance. Arrays were chosen here
to minimize size.
Further general considerations are:
•
All nets in the address and command fly-by groups shall have the same number of vias in each length-
matched segment. Ground vias are placed to ensure a proper current return path. Minimize use of vias
on signal traces as they negatively impact signal integrity.
•
The single-ended Address/Command net class and the control net class needs external termination to
V
TT
.
•
For the data net class within a byte lane, the data bits can be swapped to simplify routing.
•
Organize the power, ground, and signal planes to eliminate or significantly reduce the number of split
or cut planes present in the design (no splits are allowed under any DDR3 routes).
•
Maintain an acceptable level of skew across the entire DDR3 interface (by net class).
•
It is strongly recommended that all nets be simulated to assure proper design, performance, and signal
integrity.
•
Take into account the differences in propagation delays between microstrip and stripline nets when
evaluating timing constraints. All long routes should be stripline to reduce EMI and timing skew, and
any microstrip routed for BGA breakouts should be as short as possible.
•
Routes along the same path and routing segment must have the same number of vias. Vias can be
blind, buried, or HDI microvia for improved signal integrity, but are not required for standard data rates.
Similarly, back drilling vias is not required for standard data rates but can be used to eliminate via
stubs.
•
For this design, the DDR3 layout was copied from the TI AM3359 Industrial Communications Engine
development platform with part number TMDSICE3359 to leverage a working and fully tested design
with the peripheral settings for the DDR3 interface.
2.3.1.2.6
AM3359 Clocking Options
For the clock, either a crystal or a digital clock source can be used. For both cases, the clock needs to be
19.2, 24, 25, or 26 MHz with a tolerance of ±50 ppm. For more details, see Section 6.2.2 of the AM3359
data sheet
. For this design, a 24-MHz crystal was chosen as used with the TMDSICE3359 AM3359
Industrial Communications Engine development platform.
The preferred option, as realized with revision E3 of this design, is to have all system clocks in the design
synced to a single reference clock. This consolidation helps to reduce jitter between the individual clocks
on the board. This option is a key feature for system performance between the PHY and the MAC layer
communication, especially in real-time Ethernet systems. See
for more details.
The CDCE913 programmable 1-PLL VCXO clock synthesizer is used to generate the 24-MHz clock for
the AM3359.
2.3.1.2.7
Power Supply Pins
For the decoupling capacitors on the different power rails of the AM3359, see Section 5.9 of the AM3359
data sheet
.
