Texas Instruments TIDA-00204 Manual Download

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JTAG/

UART

Micro

24-V to 5-V

DC-DC

Reset

button

Input: 24 V

(17 V to 60 V)

Micro

USB

DDR3

Status LEDs

10/100/1000

Mb/s

Ethernet

PHY1

DP83867IR

RJ45

10/100/1000

Mb/s

Ethernet

PHY2

DP83867IR

6LWDUDŒ 30,&

DDR3 P/S

Gigabit PHY P/S

Port 1

25-MHz clock

24-MHz

clock

Host processor
Sitara

AM3359

Status LEDs

RJ45

Port 2

25-MHz clock

Application firmware
- IPv4 TCP/IP
- UDP
- IP address:
192.168.1.10
- HTTP webserver
example

Clocking

Distribution

Network

CDCE913

25-MHz

clocks

24-MHz

clock

System Description

www.tij.co.jp

JAJU324B – March 2015 – Revised July 2017

TIDU832

翻訳版

—

Summary of Contents for TIDA-00204

Page 1: ...ォルダ TPS65910A3 プロダクトフォルダ TPS51200 プロダクトフォルダ LMZ10501 プロダクトフォルダ TPS720 プロダクトフォルダ TPS737 プロダクトフォルダ TPD4E05U06 プロダクトフォルダ TPS717 プロダクトフォルダ TPD4S012 プロダクトフォルダ CDCE913 プロダクトフォルダ E2Eエキスパートに質問 WEBENCH 設計支援ツール特特長長 EMIおよびEMC規格に準拠した設計で 2つの DP83867IRギガビットイーサネットPHYおよび AM3359 Sitara プロセッサを使用して広い入力電圧範囲 17 60V に対応し過酷な工業用環境で動作可能 CISPR 11 EN55011 Class Aの放射要件を4 3dB 超上回る IEC61800 3 EMCの耐性要件を上回る 6kV E...

Page 2: ... for ESD according to 61000 4 2 fast transient burst EFT according to IEC61000 4 4 and surge according to IEC61000 4 5 The design implements dual port Gigabit Ethernet using two DP83867IR Gigabit Ethernet PHYs which are connected through the Reduced Gigabit Media Independent Interface RGMII to AM3359 Sitara processor with integrated Ethernet MAC and Switch It offers a wide input voltage range from...

Page 3: ...lace protection diodes on either side of the magnetics used for test purpose SMI Y 2 5 MHz Configurable PHY address SMI Y Through strap resistors DP83867IR Low power 565 mW Integrated termination resistors Y RGMII Delay Mode on RX TX Programmable Clock 25 MHz 50 ppm Power Input voltage 24 V 17 to 60 V Output voltage 5 V Intermediate voltage Output current 850 mA nominal 1 2 A maximum Indicator LED...

Page 4: ...porated EMI EMC規格準拠産業用温度範囲のデュアルポートギガビットイーサネットのリファレンスデザイン表表 2 TIDA 00204 Firmware Specification AM3359 continued FUNCTION INFO SPECIFICATION COMMENT PHY Driver for DP83867IR Y RTOS TI SYS BIOS Y UDP and TCP IP IPv4 protocol support Y Based on TI s AM335x industrial SDK and NDK Fixed IP 192 168 1 10 HTTP Web server example Y Based on TI s AM335x industrial SDK and NDK ...

Page 5: ...3867IR Gigabit Ethernet PHY the AM3359 Sitara Host Processor and the power supplies 図図 1 System Block Diagram of TIDA 00204 2 2 Design Considerations 2 2 1 Gigabit Ethernet Overview Ethernet has heavily expanded usage over the years Ethernet became an attractive option for industrial networking applications The opportunity to use open protocols such as TCP IP over Ethernet networks help replace p...

Page 6: ...ransmission by allowing symbols to be transmitted and received on the same wire pairs at the same time Baseband signaling with a modulation rate of 125 MBd is used on each of the wire pairs The transmitted symbols are selected from a four dimensional five level symbol constellation 4D PAM5 In the absence of data idle symbols are transmitted The IEEE 802 3 specifies specify that a PHY with a MDI th...

Page 7: ...d the TX_CLK signal is used to synchronize the signals TX_D TX_EN and TX_ER The receiver signals are RX_CLK RX_D 7 0 RX_DV RX_ER COL and CS The GMII uses in total a maximum of 25 pins 2 2 2 2 2 RGMII The RGMII is designed to reduce the number of pins required to interconnect the MAC and PHY 12 pins for RGMII relative to 24 pins for GMII With this optimization the RGMII consists of 12 signals 6 sig...

Page 8: ...k MDC and a Management Data Input Output MDIO signal It provides access to the PHY s internal register space for status information and configuration The MDC and MDIO signals can be shared amongst several PHYs due to the serial communication protocol where an address is used to identify the corresponding PHY slave The MDIO has a standard set of registers from 0 to 31 each containing 16 bits In IEE...

Page 9: ...yer this detection happens the timing error varies The lower the layer the smaller the error 図図 3 Options 1 to 4 for Time Stamp versus Layer The closer to the PHY the time stamp is set the better the time reference The time stamp consists of two signals the Ingress RX and Egress TX time stamp Depending on when the time stamp is done the delay can vary from nanoseconds to microseconds 2 3 System D...

Page 10: ...ance are recommended 図図 4 Strap Circuit 表表 4 Four Level Strap Resistor Ratios MODE RESISTOR RHI kΩ RESISTOR RLO kΩ 1 OPEN OPEN 2 11 2 49 3 6 04 2 49 4 2 49 OPEN Because this design employs two DP83867IR the SMI will have two DP83867IR slaves addresses This means that the SMI address of the two DP83867IR have to differ to ensure a valid communication To set the DP83867IR SMI address a strap confi...

Page 11: ...ギガビットイーサネットのリファレンスデザイン図図 5 Schematic for DP83867IR Strap Configuration on ETH2 表表 5 DP83867IR Strap on Resistor Chosen DP83687IR PIN NAME CONFIGURATION MODE RX_D4 Strap resistors 2 PHY_ADD4 1 only ETH2 RX_D6 Strap resistors 2 RGMII enable RX_D7 Strap resistors 2 Clock out disable When using the strap configuration on a specific pin ensure that the additional function mapped to this pin is ap...

Page 12: ... done properly for all signals to avoid skew due to different propagation delay between the clock and the data signals For this design the following rules were followed on the RGMII signals 表表 7 DP83867 RGMII Design Rules on TIDA 00204 PCB RULES DISTANCE RGMII TX length matching 0 254 mm RGMII RX length matching 0 254 mm RGMII data to data distance separation 0 762 mm RGMII clock to data distance...

Page 13: ...Texas Instruments Incorporated www tij co jp System Overview 13 JAJU324B March 2015 Revised July 2017 TIDU832 翻訳版最新の英語版資料 http www s ti com sc techlit TIDU832 Copyright 2015 2017 Texas Instruments Incorporated EMI EMC規格準拠産業用温度範囲のデュアルポートギガビットイーサネットのリファレンスデザイン 2 3 1 1 3 Interface From PHY to RJ 45 The transformer used in the MDI connection provides DC isolation between local circuitry and the ...

Page 14: ...R PHY to the second DP83867IR PHY and eliminates the need for a crystal at the second PHY reducing costs The TIDA 00204 design has been prepared for this configuration by adding series 0 Ω resistors The preferred option as realized with revision E3 of this design is to have all system clocks in the design synced to a single reference clock This consolidation helps to reduce jitter between the indi...

Page 15: ... co jp System Overview 15 JAJU324B March 2015 Revised July 2017 TIDU832 翻訳版最新の英語版資料 http www s ti com sc techlit TIDU832 Copyright 2015 2017 Texas Instruments Incorporated EMI EMC規格準拠産業用温度範囲のデュアルポートギガビットイーサネットのリファレンスデザイン図図 8 PHY Reset Option During Power Up SYS_RESETn and Software Reset GPIO_PHY_RESETn ...

Page 16: ...ernal pull up JTAG TDO Output 2 3 1 2 Host Processor The Sitara AM3359 was chosen as it has a 2 Gb Ethernet MAC with switch layer supporting RGMII to both DP83867IRs The MAC switch layer inside the AM3359 is supporting several features of passing messages from one PHY to the other without the use of the core To achieve deterministic and very low transmit and receive latency the ICSS PRU subsystem ...

Page 17: ...device part and package This tool is a huge help for AM3359 pin assignment This design uses the following peripherals EMAC with RGMII1 and RGMII2 UART MMC0 and MMC1 MDIO SDRAM DDR3 I2 C and ECAP The pin mux tool was used to find the optimum pin assignment for the different peripherals used in the TIDA 00204 reference design 表表 11 AM3359 Pin Assignment SIGNAL PINS GPIO MODE AMOUNT OF PINS RGMII1 J...

Page 18: ...ace including ESD protection device on the TIDA 00204 The TPD6E001 is a low capacitance 15 kV ESD protection diode array designed to protect sensitive electronics attached to communication lines Each channel consists of a pair of diodes that steer ESD current pulses to VCC or GND The TPD6E001 protects against ESD pulses up to 15 kV human body model HBM 8 kV contact discharge CD and 15 kV air gap d...

Page 19: ...s of the DDR3 memory signals For DDR3 the signals can be divided into four different groups that have similar requirements 表表 12 DDR3 Net Class Definitions NET CLASS SIGNALS Data DDR_D 15 0 DDR_DQM 1 0 DDR_DQS0 _P and _N DDR_DQS1 _P and _N Address Command DDR_A 13 0 DDR_BA 2 0 DDR_CASN DDR_RASN DDR_WEN Control DDR_CKE DDR_CSN DDR_ODT DDR_RESETN Clock DDR_CLK_N DDR_CLK_P For the different groups i...

Page 20: ...ted for BGA breakouts should be as short as possible Routes along the same path and routing segment must have the same number of vias Vias can be blind buried or HDI microvia for improved signal integrity but are not required for standard data rates Similarly back drilling vias is not required for standard data rates but can be used to eliminate via stubs For this design the DDR3 layout was copied...

Page 21: ...http processors wiki ti com index php XDS100 How_to_make_an_XDS100 The EEPROM needs to be programmed in a specific way To find an example image also called a ept file to write in the EEPROM go to the following webpage http processors wiki ti com index php XDS100 A ept file for the Mprog tool is available for the specific XDS100 version needed Download a ept file which includes both JTAG and Virtua...

Page 22: ... 3 1 3 Power Supplies The power supplies are realized in three stages The first stage is a 24 V to 5 V DC DC to provide an intermediate 5 V rail to the other two stages The second stage is a PMIC supplying the host processor and the last stage is supplying the two Gigabit PHYs 図図 12 TIDA 00204 Power Supply Stages 2 3 1 3 1 24 V to 5 V DC DC Buck Converter For this stage the LM46002 SIMPLE SWITCHE...

Page 23: ... peak ripple current that flows in the inductor along with the DC load current A higher inductance gives lower ripple current which then gives a lower output voltage ripple with the same output capacitors An inductance that gives a ripple current of 20 to 40 at the maximum current is normally a good starting point The minimum inductor value is calculated based on input voltage range 17 to 60 V out...

Page 24: ...oo low inductance can generate too large inductor current ripple such that over current protection at the full load could be falsely triggered It also generates more conduction loss because the RMS current is slightly higher relative that with lower current ripple at the same DC current Larger inductor current ripple also implies larger output voltage ripple with the same output capacitors With pe...

Page 25: ...between 4 7 to 10 μF A good practice for ceramic capacitors is to choose a voltage rating of twice the maximum input voltage If the placement of the LM46002 additional bulk capacitance is needed this additional capacitor dampens voltage spikes caused by the lead inductance of the trace The value is not critical but it must be rated to fit the voltage requirements The output voltage is externally a...

Page 26: ...ザイン式 9 indicates that the crossover frequency is geometrically centered on the zero and pole frequencies caused by the C14 capacitor For designs with higher ESR C14 is not needed When COUT has medium ESR C14 calculated from 式 9 should be reduced With Low ESR used the calculated value Table 2 of the LM46002 data sheet can be used as a starting point The calculated value is 8 2 pF and an 8 2 pF COG...

Page 27: ...ll take the output voltage to reach its programmed value during start up This also allows limiting the inrush current in the LM46002 current require to charge the output capacitors to the programmed value If this pin is left unconnected the soft start time is 4 1 ms typically Longer soft start times can be set by an external soft start capacitor per 式 10 10 with C12 equal the soft start capacitor ...

Page 28: ... be 3 3 2 5 or 1 8 V See its data sheet for more details on the current consumption per rail and if a voltage other than 3 3 V is used in the VDDIO rail 1 表表 14 Power Consumption per Voltage Rail RAIL STANDARD POWER MODE 565 mW LOW POWER MODE 545 mW 1 1 V 106 mA 106 mA 1 8 V N A 64 mA 2 5 V 157 mA 103 mA VDDIO 3 3 2 5 or 1 8 V 31 mA 1 8 V 31 mA 1 8 V For this design the power supply was designed ...

Page 29: ...ENT TEMPERATURE RɵJA MAX CURRENT AT 85 C TPS72011DRV 2 5 V 1 1 V 1 4 V 615 mW 65 K W 439 29 mA TPS73733DCQ 5 V 3 3 V 1 7 V 790 mW 1 53 1 K W 464 71 mA 1 The 2 5 V rail at LMZ10501 was chosen due to the fact that an LDO with the current needed would be a very expensive device and would dissipate a significant amount of power When two PHYs are powered approximately 526 mA is required with margin the...

Page 30: ...per 10 EEPROM Sequence RAIL NAME TYPE VOLTAGE OPTIONS DEFAULT VOLTAGE POWER VIO SMPS 1 5 1 8 2 5 or 3 3 V 1 5 V 1000 mA VDD1 SMPS 0 6 to 1 5 V in 12 5 mV steps Programmable multiplication factor 2 3 1 1 V 1 1 V 1500 mA VDD2 SMPS 0 6 to 1 5 V in 12 5 mV steps Programmable multiplication factor 2 3 1 1 V 1 1 V 1500 mA VDD3 LDO 5 V or OFF N A 100 mA VDIG1 LDO 1 2 1 5 1 8 or 2 7 V 1 8 V 300 mA VDIG2 L...

Page 31: ...ce CS and the external load capacitors CX and CY respectively as per 式 14 Assuming that the external load capacitors are the same value they can be calculated with 式 14 14 CS is the stray capacitance device and PCB this value can be assumed to a few pF as a rule of thumb The load capacitors need to be NPO COG type 表 17 shows the selected load capacitors per crystal and per device on the TIDA 00204...

Page 32: ...tentially run at 25 MHz 1250 Hz When running several crystals the phase shift between the two crystals can potentially be maximum negative and maximum positive which 図 17 shows 図図 17 Crystal Phase Shift Diagram This distribution means that depending on how many clocks are seen on a signal package the phase shift of the two clocks accumulates Avoid this accumulation by adding a clocking distributi...

Page 33: ...MC規格準拠産業用温度範囲のデュアルポートギガビットイーサネットのリファレンスデザイン This new clocking source could be used to change the component floor plan as shown in 図 19 with an Altium 3 D PCB simulation 図図 19 PCB Component Area Saving With CDCE913 Clock Generator When using the CDCE913 part programming the EEPROM of the part before soldering it may be an easier solution TI provides the CDCEL9XXPROGEVM tool for this reason Th...

Page 34: ...i com sc techlit TIDU832 Copyright 2015 2017 Texas Instruments Incorporated EMI EMC規格準拠産業用温度範囲のデュアルポートギガビットイーサネットのリファレンスデザイン図図 20 Settings Used to Program CDCE913 Device on TIDA 00204 Reference Design The diagrams also shows that the load crystals can be removed and replaced by an internal crystal ...

Page 35: ...h boots from micro SD Card automatically after the TIDA 00204 is powered The application firmware implements a driver for the DP83867IR UDP and TCP IP stack and HTTP web server examples A USB virtual COM port offers optional user access to read or write to DP83867IR registers for custom configurations like RGMII Delay Mode if required 3 1 1 Functional Overview The host processor Sitara AM3359 is c...

Page 36: ...read as well as an Ethernet task thread After that the app starts SYS BIOS Then both the UART thread and the Ethernet thread are scheduled and run accordingly 図図 22 AM3359 Initialization The Ethernet thread initializes the configuration registers of both DP83867IR Gigabit PHYs through SMI For example set RGMII mode autonegotiation indicator LEDs and more Then the thread enables the network layer ...

Page 37: ...PHY1 and PHY2 with MDIO interface Gigabit Ethernet thread Port 2 cable connected Yes Autonegotiate Ethernet Ethernet link Port 2 cable Disconnected No No Yes Init HTTP Init IPv4 with static IP 192 168 1 10 Init TCP and UDP Cable connected Yes No Thread Thread www tij co jp Software Design 37 JAJU324B March 2015 Revised July 2017 TIDU832 翻訳版最新の英語版資料 http www s ti com sc techlit TIDU832 Copyright 2...

Page 38: ...ation to MLO to fit the AM3359 ROM boot loader and is part of the TIDA 00204_Firmware_AM3359_SD Card_Image 3 1 2 2 app Binary File The TIDA 00204 example application binary file app was developed with the following Texas Instruments software packages AM335x_SYSBIOS_Industrial_SDK 01_01_00_06 http downloads ti com sitara_indus esd AM335x_SYSBIOS_Industrial_SDK latest index_FDS html SYS BIOS 6_40_03...

Page 39: ... and then included into the TIDA 00204 software package 3 2 PC Test Software for UDP Packet Transfer Based on TI s NDK The tests for the Gigabit Ethernet communication path developed with the Texas Instruments NDK 2_24_00_11 software package From this software package the following source file was used c ti ndk_2_24_00_11 packages ti ndk winapps testudp c For more information on the testudp files ...

Page 40: ... co jp 40 JAJU324B March 2015 Revised July 2017 TIDU832 翻訳版最新の英語版資料 http www s ti com sc techlit TIDU832 Copyright 2015 2017 Texas Instruments Incorporated EMI EMC規格準拠産業用温度範囲のデュアルポートギガビットイーサネットのリファレンスデザイン 3 2 1 UDP Throughput Test The example UDP test file is called TIDA 00204_UDP_throughput_test exe The software flow of the throughput example code can be seen in 図 26 図図 26 Flowchart of UDP...

Page 41: ...新の英語版資料 http www s ti com sc techlit TIDU832 Copyright 2015 2017 Texas Instruments Incorporated EMI EMC規格準拠産業用温度範囲のデュアルポートギガビットイーサネットのリファレンスデザイン 3 2 2 UDP Packet Error Test The example UDP test file is called TIDA 00204_UDP_throughput_test exe 図 28 shows the software flow of the throughput example code can be seen 図図 28 Flowchart of UDP Packet Error Test Software The above example verifies i...

Page 42: ... March 2015 Revised July 2017 TIDU832 翻訳版最新の英語版資料 http www s ti com sc techlit TIDU832 Copyright 2015 2017 Texas Instruments Incorporated EMI EMC規格準拠産業用温度範囲のデュアルポートギガビットイーサネットのリファレンスデザイン図図 29 Command Prompt UDP Packet Error Test Print ...

Page 43: ...s supply rails D2 5 V D3 2 5 V D14 3 3 V Micro USB virtual COM port www tij co jp Getting Started 43 JAJU324B March 2015 Revised July 2017 TIDU832 翻訳版最新の英語版資料 http www s ti com sc techlit TIDU832 Copyright 2015 2017 Texas Instruments Incorporated EMI EMC規格準拠産業用温度範囲のデュアルポートギガビットイーサネットのリファレンスデザイン 4 Getting Started 4 1 PCB Overview A picture of the PCB with key functional blocks is shown in 図 3...

Page 44: ...llowing hardware equipment and software is required 表表 18 Prerequisites HARDWARE EQUIPMENT OR SOFTWARE REQUIREMENTS 24 V power supply 24 V output power brick with at least a 250 mA output current Output connector 2 1 mm I D 5 5 mm O D 9 5 mm Female PC PC or Laptop with USB port and Gigabit Ethernet port Ethernet cable Recommended CAT7 twisted pair cable Micro USB cable N A Micro SD card Big enoug...

Page 45: ...er MLO from the micro SD Card and enables the Sitara AM3359 in a mode The Sitara AM3359 enables the needed peripherals to communicate with the two PHYs over the MDI and sets those PHYs in autonegotiate 10 100 1000 mode It also enables a UART functionality where one can read out the PHY registers from the two DP83867 devices over virtual COM port Write the image TIDA 00204_SD Card_Image_rev1_0 img ...

Page 46: ...s Incorporated EMI EMC規格準拠産業用温度範囲のデュアルポートギガビットイーサネットのリファレンスデザイン CAUTION If the micro SD Card is not prepared like above but the individual binary files MLO and app are copied to a preformatted micro SD Card it might be that the AM3359 does not boot properly For further details on this topic see the Section 26 1 7 5 2 of the AM335x technical reference manual 6 ...

Page 47: ... connected Connect the micro USB cable from the TIDA 00204 reference design to the PC Now the XDS100 v2 PC USB driver is installed on the PC If PC does not find this driver install CCS 6 to get the driver Invoke a terminal program like TeraTerm that can connect to the virtual COM port Setup the terminal program in Serial Console Mode and set the parameters as seen in 表 19 表表 19 Terminal Program S...

Page 48: ... 2 Status LED Configuration LED D7 D12 D4 D9 D5 D10 D6 D11 Function Not assigned to a specific function on TIDA 00204 Receive or transmit activity 1000 Mb link established Link established The status LEDs are explained from left to right when looking at the board picture The reference design is setup to use the IP address 192 168 1 10 that is a static IP It does not have DHCP function enabled Setu...

Page 49: ...e two PC test programs as part of the TIDA 00204 software package can be used Insure that the libwinpthread 1 dll is located in the same folder as the TIDA 00204_throughput_test exe and TIDA 00204_packet_test exe This library can be downloaded from the internet To invoke these programs use a Windows PC with the command prompt see 図 35 and 図 36 for example print outs 図図 35 Command Prompt UDP Throu...

Page 50: ...com sc techlit TIDU832 Copyright 2015 2017 Texas Instruments Incorporated EMI EMC規格準拠産業用温度範囲のデュアルポートギガビットイーサネットのリファレンスデザイン 4 3 3 HTTP Web Server Example Open a browser and enter this address http 192 168 1 10 See 図 37 for a screenshot of the TIDA 00204 webpage 図図 37 TIDA 00204 HTTP Web Server Example ...

Page 51: ...ection can be used to read and write to both DP83867IR registers through SMI With this it is possible to configure the DP83867IR registers in a different configuration than default for additional test options CAUTION All inputs are in decimal and all outputs are in hexadecimal 図 38 shows an example screenshot for a register read from DP83867IR on Ethernet port 2 図図 38 Virtual COM Port Connection ...

Page 52: ... DRAKA UC900 super screen 27 CAT7 with a CAT6A connector Oscilloscope Tektronix TDS794D P6339A probes Tektronix TDS2024B P2220 probes Electronic load Chroma 63103 with Chroma 6314 Multimeter FLUKE 179 5 1 Gigabit Ethernet Signal Integrity Tests 5 1 1 RGMII Signals The RGMII signals between the MAC and the PHY are tested with a 1000 Mb connection on both PHY1 and PHY 2 RX and TX 図 39 through 図 42 s...

Page 53: ...図 42 ETH2 RGMII TX Clock and Data Signal During Gigabit Ethernet Connection 5 1 2 Serial Management Interface SMI The maximum clock frequency of the SMI of the Sitara AM3359 is 2 5 MHz This test does not need to have an Ethernet connection running 図 43 and 図 44 show the two signals MDC Clock and MDIO I O between the Sitara AM3359 and the two DP83867IR for Gigabit Ethernet ETH1 and ETH2 図図 43 SMI ...

Page 54: ...nge between 17 and 60 V The nominal load current was defined for the following configuration The Sitara AM3359 running at 600 MHz executing the application code from DDR3 with both DP83867IR connected in Gigabit Ethernet mode with continuous UDP packet transfer at 20 network utilization on both ports The minimum load current is set to 500 mA the nominal load to 850 mA and the maximum load to 1 2 A...

Page 55: ...トイーサネットのリファレンスデザイン 5 2 2 Power Supply for the DP83867IR Gigabit Ethernet PHYs Tests The voltages have been verified as shown in 表 22 The startup of the 3v3 2v5 and 1v1 rails are shown in 図 48 表表 22 Measured Voltage Rails of the Gigabit Ethernet PHY SUPPLY NAME PER SCHEMATICS SPECIFIED VOLTAGE MEASURED 3v3 3 3 V 3 31 V 2v5 2 5 V 2 47 V 1v1 1 1 V 1 10 V 図図 48 PHY Power Supply Voltage Rails Duri...

Page 56: ... the expected voltages based on the TPS65910A3 EEPROM pin configuration 表表 23 Measured Voltages on the PMIC TPS65910A3 SIGNAL EXPECTED VOLTAGE MEASURED VOLTAGE VIO 1 5 V 1 52 V VDD1 1 1 V 1 11 V VDD2 1 1 V 1 11 V VDD3 OFF N A VDIG1 1 8 V NC VDIG1 pin was not connected in this design VDIG2 1 8 V 1 81 V VPLL 1 8 V 1 82 V VDAC 1 8 V 1 80 V VAUX1 1 8 V 1 82 V VAUX2 3 3 V 3 31 V VAUX33 3 3 V 3 33 V VM...

Page 57: ...ink negotiated is not going into a default setting defined in the IEEE 802 3ab standard This can happen if one partner of the link is forced and the other is set to autonegotiate The default autonegotiate setting of the DP83867IR is set 10 100 1000 Mb half or full duplex mode The DP83867IR recognizes the data rate supported by partner and sets the highest data rate supported by both 表 25 shows the...

Page 58: ... Log of TIDA 00204 Ping Test Using a Linux PC as the test machine when running ping tests gives a better indication of the Ethernet utilization The Linux ping command gives the user more options to define the ping condition as well as the ping speed The ping command to use here is sudo ping 192 168 1 10 s 1400 p 5a f The following result is achieved with this command PATTERN 0x5a PING 192 168 1 10...

Page 59: ... Task Manager networking was used to log the packet transfer utilization during the UDP throughput test 図 52 shows the Windows Task Manager printout 図図 52 Utilization of One Port Connection With UDP Throughput Test Running With the throughput test file it is possible to achieve around 25 utilization of the Gigabit bandwidth The slight change in the utilization on the curve is due to other network...

Page 60: ...C規格準拠産業用温度範囲のデュアルポートギガビットイーサネットのリファレンスデザイン 5 3 4 HTTP Web Server To test the HTTP web page example the TIDA 00204 s static IP address http 192 168 1 10 is entered into a browser see 図 53 図図 53 HTTP Web Server Example For this test Wireshark was used to log the traffic generated by initializing the web server and the loading of the page 図 54 shows the traffic log from Wireshark ...

Page 61: ... 2015 Revised July 2017 TIDU832 翻訳版最新の英語版資料 http www s ti com sc techlit TIDU832 Copyright 2015 2017 Texas Instruments Incorporated EMI EMC規格準拠産業用温度範囲のデュアルポートギガビットイーサネットのリファレンスデザイン図図 54 Wireshark Log of TIDA 00204 HTTP Web Server Example ...

Page 62: ...jor drop in network utilization One UDP packet loss will be tolerated by the system if the following UDP packet is echoed back successfully The test has been conducted with a UDP error packet test program at around 5 network bandwidth 表表 27 IEC61800 3 and IEC61000 6 2 EMC Immunity Requirements for Second Environment and Measured Voltage Levels and Class REQUIREMENTS TIDA 00204 MEASUREMENTS Port P...

Page 63: ... receives continuous UDP packages with a payload size of 1472 bytes yielding the maximum 1514 bytes per IPv4 packet The firmware of the Sitara AM3359 receives the UDP packets and echoes them back Each of the two Ethernet ports used around 20 of the network The second test program tida 00204_udp_packet_error_test exe implements a UDP packet tester It compares the transmitted packet with the receive...

Page 64: ... of margin far field measurements at 125 MHz vertical polarization The minimum margin in horizontal polarization was 10 6 dB at 125 MHz as well An automatic pre test with near field measurement 3 m antenna distance to device under test DuT was used to identify the frequencies of maximum EMI in each horizontal and vertical polarization as preparation for the final test with a 10 m antenna distance ...

Page 65: ...ed during the pre test As mentioned earlier the minimum margin was 4 3 dB in vertical and 10 6 dB in horizontal polarization each at 125 MHz 表表 29 Measured EMI Spectrum Quasi Peak According to EN55011 10 m Far Field Horizontal Polarization FREQUENCY MHz READING dBµV QP CORRECTION dB VALUES dBµV m QP LIMIT dBµV m QP MARGIN dB QP 125 18 6 10 8 29 4 40 10 6 250 21 1 15 2 36 3 47 10 7 375 16 6 18 8 3...

Page 66: ...ンスデザイン表表 30 Measured EMI Spectrum Quasi Peak According to EN55011 10 m Far Field Vertical Polarization FREQUENCY MHz READING dBuV QP CORRECTION dB VALUES dBuV m QP LIMIT dBuV m QP MARGIN dB QP 125 24 9 10 8 35 7 40 4 3 250 20 4 15 2 35 6 47 11 4 375 12 6 18 8 31 4 47 15 6 500 8 5 21 8 30 3 47 16 7 875 1 2 27 3 28 5 47 18 5 図図 58 Measured EMI Spectrum Quasi Peak According to EN55011 10 m Far Fi...

Page 67: ...for radiated EMI is higher by 10 dB as well The setup is shown in 図 59 図図 59 Automatic Pre Test Setup for EMI With 3 m Antenna Distance to DuT Left Antenna Right TIDA 00204 DuT and Box With Shielded Laptops A pre test was done to identify the critical frequencies on each polarization This test has been done in a chamber with a 3 m distance to the antenna 表表 31 Pre Test Equipment Setup TYPE NAME ...

Page 68: ...ncorporated EMI EMC規格準拠産業用温度範囲のデュアルポートギガビットイーサネットのリファレンスデザイン The measured spectrum of the pre test is shown in 図 60 for horizontal and in 図 61 for vertical polarization 図図 60 Measured EMI Spectrum According to EN55011 3 m Near Field Horizontal Polarization Pre Test 図図 61 Measured EMI Spectrum According to EN55011 3 m Near Field Vertical Polarization Pre Test ...

Page 69: ... connected with a conductive copper foil During the ESD test both Gigabit Ethernet ports were connected with a 20 m cable to the far end laptops A UDP packet transfer was launched on each Gigabit Ethernet link The test program tida 00204_udp_throughput_test exe transmits and receives continuous UDP packages with a payload size of 1472 bytes yielding the maximum 1514 bytes per IPv4 packet The firmw...

Page 70: ...C61000 4 2 4 kV CD RJ45 port 1 and 2 B ESD IEC61000 4 2 6 kV CD RJ45 port 1 and 2 B Not required per IEC61800 3 ESD IEC61000 4 2 8 kV CD RJ45 port 1 and 2 C Not required per IEC61800 3 ESD IEC61000 4 2 8 kV AD RJ45 port 1 and 2 B ESD IEC61000 4 2 15 kV AD RJ45 port 1 and 2 B Not required per IEC61800 3 Class B was claimed when there was a network utilization reduction but no link loss Only for 8 k...

Page 71: ... on a laptop for analysis as described earlier The test results are shown in 表 33 1 See 5 4 1 for test setup description 2 See 表 28 for performance descriptions 表表 33 IEC 61000 4 4 EFT Test Results for TIDA 00204 PHENOMENON BASIC STANDARD LEVEL TIDA 00204 CONNECTOR UNDER TEST PERFORMANCE CRITERION 1 2 COMMENT EFT IEC61000 4 4 2 kV 5 kHz cap clamp RJ45 port 1 B EFT IEC61000 4 4 2 kV 5 kHz cap clam...

Page 72: ...to 1 due to a laptop issue when a packet lost was detected 図図 65 IEC61000 4 4 4 kV EFT Network Utilization With UDP Throughput Test on Gigabit Ethernet Port 1 図図 66 IEC61000 4 4 4 kV EFT Network Utilization With UDP Packet Error Test on Gigabit Ethernet Port 1 During the test the UDP packet error test program printed the packet number for every packet lost as well as the total submitted packets ...

Page 73: ...ests a UDP packet transfer was launched on each Gigabit Ethernet port Each test level and Gigabit Ethernet port was tested with two different PC software programs running on a laptop for analysis as described earlier The test results are shown in 表 34 1 See 5 4 1 for test setup description 2 See 表 28 for performance descriptions 表表 34 IEC 61000 4 5 Surge Test Results for TIDA 00204 PHENOMENON BAS...

Page 74: ...h a UDP error packet test program at around 5 network bandwidth see 図 68 To verify the number of packets lost the program during the surge tests a UDP packet transfer was launched on each Gigabit Ethernet port Each surge voltage test level and Gigabit Ethernet port was tested with two different software programs running on the laptop for analysis of throughput and packet errors during a surge even...

Page 75: ... TVS diode between the PHY and transformer During 1 kV surge as per IEC61800 3 no significant changes were observed with or without TVS diode However at 2 kV exceeding the level required by IEC61800 3 the packet error losses significantly increase by a factor of 10 Therefore if higher surge immunity is desired the TVS diode is recommend to be populated between the PHY and the transformer as per th...

Page 76: ...00 Ω impedance For the single ended traces the board is matched to 50 Ω A layer size of 0 018 mm was chosen for the top and mid layers This size can be defined as the base thickness When actually building the board the mid layers will decrease in size and the outer layers will increase in size This means that the expected top layer thickness would be 0 040 mm and a mid layer would have an expected...

Page 77: ...llowing considerations The RGMII interface is a 125 MHz signal which gives a full clock cycle of 8 ns The typical propagation delay in a FR4 stripline is 7 087 ns mm which means that the length of the RGMII interface introduces a delay that should be kept as small as possible For the RGMII signal below 0 5 ns this should be a delay that can be ignored So the signal can be around 63 5 mm long maxim...

Page 78: ...n layer 6 Termination for RGMII TX on top layer U15 Rev E1 Rev E3 Design Files www tij co jp 78 JAJU324B March 2015 Revised July 2017 TIDU832 翻訳版最新の英語版資料 http www s ti com sc techlit TIDU832 Copyright 2015 2017 Texas Instruments Incorporated EMI EMC規格準拠産業用温度範囲のデュアルポートギガビットイーサネットのリファレンスデザイン図図 72 Layout Guidelines for RGMII RX Signals Comparing E1 and E3 ...

Page 79: ...tics the differential pairs are routed on the top layer with differential impedance control matching of 100 Ω The reference GND is on mid layer 1 This is achieved by ensuring that isolation between top layer and mid layer 1 is smaller than the surrounding planes From the magnetics to the RJ45 the differential pairs A C and D are routed on the top layer while pair B is routed on mid layer 2 This is...

Page 80: ...evised July 2017 TIDU832 翻訳版最新の英語版資料 http www s ti com sc techlit TIDU832 Copyright 2015 2017 Texas Instruments Incorporated EMI EMC規格準拠産業用温度範囲のデュアルポートギガビットイーサネットのリファレンスデザイン 6 4 4 Layout PHY Power Supply For the 2 5 V LMZ rail add a keep out GND cut in mid layer 1 to decrease noise coupling To additional thermal management add as many vias as possible on the powerPAD of the 1 1 V and 1 8 V L...

Page 81: ...er LM46002 to avoid coupling into other layers Ensure that current loop of the device is maintained as small as possible The example layout of the LM46002 on TIDA 00204 is shown in 図 75 図図 75 Layout Guidelines for 24 V to 5 V DC DC Buck With LM46002 6 4 6 Layout Sitara Power Supply For the Sitara power supply the following guidelines were considered Routing the power tracks to the Sitara each pow...

Page 82: ...www s ti com sc techlit TIDU832 Copyright 2015 2017 Texas Instruments Incorporated EMI EMC規格準拠産業用温度範囲のデュアルポートギガビットイーサネットのリファレンスデザイン 6 4 7 Layout DDR3 Layer 6 is GND reference for DDR3 90 µm dielectric distance layer to layer The other layers are 400 µm away All DDR3 signals are on one layer ...

Page 83: ...4 NDK User s Guide SPRU523 10 Texas Instruments Sitara Wiki Page http processors wiki ti com index php Sitara 11 Texas Instruments AM3359 Industrial Communications Engine Evaluation Module Part TMDSICE3359 http www ti com tool tmdsice3359 12 Texas Instruments LM46002 SIMPLE SWITCHER 3 5 V to 60 V 2 A Synchronous Step Down Voltage Converter LM46002 Data Sheet SNVSA13 13 IEEE 802 3 2012 IEEE Standar...

Page 84: ...商標標 All trademarks are the property of their respective owners 9 About the Authors KRISTEN MOGENSEN is a system engineer in the Industrial Systems Motor Drive team at Texas Instruments Mogensen is responsible for developing reference designs for industrial drives MARTIN STAEBLER is a system engineer in the Industrial Systems Motor Drive team at Texas Instruments Staebler is responsible for develo...

Page 85: ... on TIDA 00204 PCB and updated the listed rules and distances 変更 12 図 7 to updated schematic 変更 13 detail on clock option to sync all clocks using a clock distribution network for DP83867IR Input Clock Selection 追加 14 detail on clock option to sync all clocks using a clock distribution network for AM3359 Clocking Options 追加 20 図 17 to updated figure from CDCE913 Clock Distribution Circuit Example ...

Page 86: ...リケーションの開発に関連する目的でのみ使用コピー変更することが許可されています明示的または黙示的を問わず禁反言の法理その他どのような理由でも他のTIの知的所有権に対するその他のライセンスは付与されませんまた TIまたは他のいかなる第三者のテクノロジまたは知的所有権についてもいかなるライセンスも付与されるものではありません付与されないものには TI製品またはサービスが使用される組み合わせ機械プロセスに関連する特許権著作権回路配置利用権その他の知的所有権が含まれますがこれらに限られません第三者の製品やサービスに関するまたはそれらを参照する情報はそのような製品またはサービスを利用するライセンスを構成するものではなくそれらに対する保証または推奨を意味するものでもありません TIリソースを使用するため第三者の特許または他の知的所有権に基づく第三者か...

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