System Overview
19
JAJU324B – March 2015 – Revised July 2017
翻訳版
—
最新の英語版資料
http://www-s.ti.com/sc/techlit/TIDU832
Copyright © 2015–2017, Texas Instruments Incorporated
EMI/EMC
規格準拠、産業用温度範囲のデュアルポート・ギガビット・イーサネットの
リファレンス・デザイン
2.3.1.2.5
DDR3 RAM
For this design, the MT41J128M16JT-125K TR DDR3 RAM was chosen to leverage experience from the
TI AM3359 Industrial Communications Engine development platform with part number TMDSICE3359.
This memory requires a 1.5-V supply with a rise time better than 200 ms. During this time a V
TT
supply
needs to be provided as this rail is a system supply for signal termination resistors. Once powered, the
device needs to be reset before going into the initialization state. Then the memory is ready for operation.
Due to the speed of the signals to the DDR3 RAM, length matching and termination are important to
ensure performance. For the data lines, length matching was done by defining different net classes with
specific considerations. The concept of defining different net classes is important when routing high speed
signals, as they can insure timing constraints or timing relationships. When defining these groups, it is
important to understand the basics of the DDR3 memory signals. For DDR3, the signals can be divided
into four different groups that have similar requirements.
表
表
12. DDR3 Net Class Definitions
NET CLASS
SIGNALS
Data
DDR_D[15:0],DDR_DQM[1:0], DDR_DQS0[_P and _N], DDR_DQS1[_P and _N]
Address/Command
DDR_A[13:0],DDR_BA[2:0], DDR_CASN, DDR_RASN, DDR_WEN
Control
DDR_CKE, DDR_CSN, DDR_ODT, DDR_RESETN
Clock
DDR_CLK_N,DDR_CLK_P
For the different groups, it is possible with either software or hardware to shift the sampling point. Even
with this feature of DDR3 RAM, it is still needed to do a timing budget calculation. With this calculation, it
is possible to have an estimation of how the length matching needs to be. Length matching is needed due
to the fact that the typical propagation delay for the FR4 PCB is approximately 6.5 ps/mm and so a length
mismatch would lead to a delay of the signal compared to the other signal lines. As an example the net
class data has been matched as seen in
表
表
13. DDR3 Trace Length on PCB for Net Class Data
SIGNAL
TRACE LENGTH (mm)
SIGNAL
TRACE LENGTH (mm)
DDR_D0
27.4776
DDR_D8
25.3669
DDR_D1
27.6777
DDR_D9
25.2680
DDR_D2
27.4567
DDR_D10
25.4147
DDR_D3
27.2947
DDR_D11
25.6113
DDR_D4
27.4070
DDR_D12
25.6584
DDR_D5
27.5413
DDR_D13
25.3574
DDR_D6
27.4398
DDR_D14
25.5648
DDR_D7
27.3044
DDR_D15
25.4486
DDR_DQM0
27.3479
DDR_DQM1
25.4907
DDR_DQS0_N
27.4755
DDR_DQS1_N
25.4209
DDR_DQS0_P
27.4726
DDR_DQS1_P
25.4285
