System Overview
14
JAJU324B – March 2015 – Revised July 2017
翻訳版
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最新の英語版資料
http://www-s.ti.com/sc/techlit/TIDU832
Copyright © 2015–2017, Texas Instruments Incorporated
EMI/EMC
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リファレンス・デザイン
To ensure no unnecessary stubs, all traces are routed on the top layer. The only exception is the pins
D2_P and D2_N. Due to the RJ45 jack pin assignment without integrated transformer, this differential pair
changed the layer to minimize the overall differential trace length of the four pairs.
表
表
9. RJ45 Connector Pinout
PIN
SIGNAL
PIN
SIGNAL
1
D1_P
5
D3_N
2
D1_N
6
D2_N
3
D2_P
7
D4_P
4
D3_P
8
D4_N
2.3.1.1.4
DP83867IR Input Clock Selection
For the input clock, either a crystal or an external clock source can be used. For both cases, the clock
needs to be 25 MHz with a tolerance of less than ±50 ppm. For more details, refer to the DP83867IR data
sheet, Sections 8.2.1.2 and 8.2.1.3
. For this design, a 25-MHz crystal was chosen (see
for
more details).
The DP83867IR has a clock out pin CLK_OUT too. This allows to route the 25-MHz clock from one
DP83867IR PHY to the second DP83867IR PHY and eliminates the need for a crystal at the second PHY,
reducing costs. The TIDA-00204 design has been prepared for this configuration by adding series 0-
Ω
resistors.
The preferred option, as realized with revision E3 of this design, is to have all system clocks in the design
synced to a single reference clock. This consolidation helps to reduce jitter between the individual clocks
on the board. This option is a key feature for system performance between the PHY and the MAC layer
communication, especially in real-time Ethernet systems. See
for more details.
The CDCE913 programmable 1-PLL VCXO clock synthesizer is used to generate the two 25-MHz clocks
for the DP83867IR.
2.3.1.1.5
Power and Ground Pins
For each of the three power rails on the DP83867IR, decoupling capacitors are recommended as follows.
A 1-nF capacitor is recommended be placed close to each supply pin of the DP83867IR. A 10-nF and a
10-µF capacitor are recommended per supply rail.
2.3.1.1.6
PHY RESET
The DP83867IR PHYs are automatically reset after power-up, through signal SYS_RESETn. Additionally,
the DP83867IR hardware reset signal PHY_RESETn can be issued by the Sitara AM3359 GPIO pin with
the signal GPIO_PHY_RESETn, which offers a software option to reset the PHYs if needed.
