Strap (GPIO)
V
DDIO
R
HI
R
LO
System Overview
10
JAJU324B – March 2015 – Revised July 2017
翻訳版
—
最新の英語版資料
http://www-s.ti.com/sc/techlit/TIDU832
Copyright © 2015–2017, Texas Instruments Incorporated
EMI/EMC
規格準拠、産業用温度範囲のデュアルポート・ギガビット・イーサネットの
リファレンス・デザイン
•
Synchronized clock output to synchronize multiple PHYs using one crystal (or clock)
2.3.1.1.1
DP83867IR Gigabit Ethernet PHY Configuration
When configuring the DP83867IR, this can be done using either a SMI or a strap configuration through the
four-level strap pins. A pull-up resistor and a pull-down resistor of suggested values may be used to set
the voltage ratio of the four-level strap pin input and the supply to select one of the possible selected
modes. The device should feature four-level strap pins, each supporting at least four selectable options,
as shown in
and
. Strap resistors with 1% tolerance are recommended.
図
図
4. Strap Circuit
表
表
4. Four-Level Strap Resistor Ratios
MODE
RESISTOR R
HI
(k
Ω
)
RESISTOR R
LO
(k
Ω
)
1
OPEN
OPEN
2
11
2.49
3
6.04
2.49
4
2.49
OPEN
Because this design employs two DP83867IR, the SMI will have two DP83867IR slaves addresses. This
means that the SMI address of the two DP83867IR have to differ to ensure a valid communication. To set
the DP83867IR SMI address a strap configuration option can be used on one DP83867IR to change the
default address from 0x00. In this design, it was chosen to use the pin RX_D4 to set the SMI address, as
this pin is not used for the RGMII.
A strap configuration option was chosen so the RGMII is always enabled to ensure the RGMII is enabled
when as the RX_D6 pin is used as input pin on the AM3359 Sitara processor.
As the clock out option of the device is not used by default, RX_D7 strap configuration option was done to
disable the clock out of the device. This feature is default on if this strap on is not done and if it needs to
be disabled without strap configuration. It would have to be done using the SMI.
