START_EXT1
STOP_EXT1
GND
GND
TRIG1
OSC_ENABLE
VCC
GND
GND
VCC
SH-JP1
GND
GND
INT1
DOUT1
DIN
CS1
SCLK
GND
TRIG1
CS1
ENABLE1
1
TP1
1
TP2
1
2
3
4
5
J6
142-0701-801
1
2
3
4
5
J4
142-0701-801
1
2
3
4
5
J5
142-0701-801
OSC_ENABLE
10µF
C1
1µF
C4
GND
0.01µF
C5
8MHz
VDD
4
OE/STANDBY
1
GND
2
OUT
3
Y1
VCC
GND
GND
GND
GND
1
TP7
1
TP8
1
2
3
4
5
J7
142-0701-801
1
2
3
4
5
J8
142-0701-801
0.1µF
C6
0.01µF
C7
1µF
C8
1
TP6
VCC
VCC
CS2
INT2
START_EXT2
STOP_EXT2
INT2
CS2
TRIG2
1
TP9
DTG_TRIG
MSP_START
1
2
3
4
5
J3
0
R11
0
R12
GND
SH-JP3
DTG_TRIG
MSP_START
GND
1
2
3
4
5
TP10
GND
1
3
5
6
4
2
7
9
10
8
12
11
14
13
16
15
18
17
20
19
J2
PPPC102LFBN-RC
1
2
JP1
ICC
1
2
JP3
ICC
TP4
TP5
1
3
5
6
4
2
7
9
10
8
12
11
14
13
16
15
18
17
20
19
J1
PPPC102LFBN-RC
GND
INT1
VCC
10.0k
R5
0
R10
10.0k
R6
49.9
R1
49.9
R2
49.9
R8
49.9
R9
49.9
R13
1
TP3
0
R3
TRIG2
VREG1
VREG2
VDD2
VDD1
VDD1
VDD2
ENABLE1
CLOCK_TDC_CAL
SCLK
DIN
START_EXT1
STOP_EXT1
START_EXT2
STOP_EXT2
0.1µF
C2
0.01µF
C3
GND
0
R7
SCLK
OSC_OUT
CLOCK_TDC_CAL
0
R18
EXT_CLOCK
0
R17
0
R16
0
R4
0
R15
0
R14
DIN
DOUT2
DOUT1
DOUT2
NOTE: 1. Add via on each SPI pins and label
2. Take all SPI bus and digital pins to Bottom Layer
3. START1, START2, STOP1, STOP2 must be symmetic and equal
from device's pin
4. Add J3 vertical narrow SMA between START1 and START2
5. Distance J3 must be the same for START1 and START2
GND
TP13
GND
TP14
CLOCK
C1
CSB1
B5
CSB2
E5
DIN
D5
DOUT1
C5
DOUT2
E3
ENABLE
A3
GND1
B2
GND2
E2
INTB1
B3
INTB2
D3
SCLK
A5
START1
A1
START2
D1
STOP1
B1
STOP2
E1
TRIGG1
A2
TRIGG2
D2
VDD1
B4
VDD2
C4
VREG1
A4
VREG2
E4
NC
C2
NC
C3
NC
D4
U1
TDC7201ZAXR
GND
GND
SV601269
A
PCB Number:
PCB Rev:
Assembly Note
ZZ1
Short SH-JP1 and SH-JP3 on JP1 pin 1-2 and JP3 pin 1-2
FID2
FID1
FID3
LOGO
PCB
FCC disclaimer
FID5
FID4
FID6
LOGO
PCB
Logo1
LOGO
PCB
Logo2
Copyright © 2016, Texas Instruments Incorporated
TDC7201EVM Schematic
18
SNAU198A – May 2016 – Revised May 2016
Copyright © 2016, Texas Instruments Incorporated
TDC7201-ZAX-EVM
Figure 16. TDC7201EVM Schematic