Texas Instruments TDC1000-GASEVM, User Manual

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C/R42& 42 must be close to TDC1000
RX pins. Place minimal parasitic
capacitances onto RX1&RX2
Interstage Passive Filters:
Configured for 1MHz
GND
TP9
DNP
TX1
TX2
RX1
RX2
TX2/RX1or TX2
TX2/RX1or RX1
GND
TX1/RX2 or TX1
TX1/RX2 or RX2
GPIO5
GPIO6
GPIO7
TDC1000_CHSEL
GPIO2
GPIO3
GPIO4
GPIO1
GPIO2
GPIO3
GPIO1
GPIO4
GPIO5
TDC1000_CHSEL
GPIO6
GPIO7
USB_5V
GND
RTD1
RTD2
1.00k
R34
GND
RTD2
RTD1
GND
1.00k
R38
GND
VCOM
ST
AR
T
ST
OP
VCOM
GND
GND
0.1µF
C30
GND
TDC1000_MCU_STOP
TDC1000_MCU_START
V5p0
GND
GND
V3p3
GND
1µF
C31
0.1µF
C29
V3p3
0.1µF
C26
GND
0.01µF
C25
V3p3
0.1µF
C34
GND
0.01µF
C33
V3p3
STOP_OUT
GND
START_OUT
33
R29
33
R33
STOP
START
TDC1000_ENABLE
10.0k
R53
TDC1000_ERRB
TDC1000_CHSEL
V3p3
TP13
DNP
TP12
DNP
TDC1000_RESET
SH-JP5
MSP430_TRIGGER TDC7200_TRIGGER
TP14
DNP
0.01µF
C37
GND
0.1µF
C38
GND
0
R49
V3p3
GND
GND
OSC_OUT
ExtClock
51.1
R50
SH-JP3
SH-JP4
SH-JP6
AVDD
CLK
CPU_CLK_OUT
33
R48
60 ohm
FB2
GND
0.01µF
C44
GND
VIO
VDD
OSC_SOURCE_SEL
OSC_ENABLE
EXT_OSC
Place the ground TP
close to VDD jumper
JP
GND
0.01µF
C40
GND
0.1µF
C41
GND
V3p3
SPI_MISO
TRIGGER_IN
33 R45
SPI_MOSI
SPI_SCLK
TDC1000_SPI_CSB
1.00k
R37
V5p0
4
3
2
1
6
5
V+
V-
U9
LMH6601MG
VCOM
10pF
C35
10.0k
R40
VCOM_OUT
GND
COMPIN
1.00k
R44
V5p0
BUFF_PGA
4
3
2
1
6
5
V+
V-
U12
LMH6601MG
V5p0
10pF
C39
10.0k
R47
GND
COMPIN_OUT
GND
CPU_CMP_OUT
C
OM
P
IN
Place filter caps
to VDD pins
GND
V5p0
Directly connected STOP and START traces from
TDC71000 to TDC7200 must be completely
symmetrical and as short as possible to avoid
introducing timing delay
Buffered STOP and START traces
from the buffers to the connectors
must be completely symmetrical to
avoid introducing timing delay
Pin 1 and pin 14 of the connector
must be marked on the PC board
Pin 1 and pin 10 of the connector
must be marked on the PC board
All the labels appearing on pin 2, 4, 6, 8, 10,
12 and 14 must be marked on the PC board
VDD_TDC1000
VIO
10.0Meg
R35
GND
10.0Meg
R36
Component value = DNP means do not populate
60 ohm
FB3
STOP
START
Buffered STOP and START traces
from the buffers to the MCU must
be completely symmetrical to avoid
introducing timing delay
0.01µF
C28
GND
TP17
DNP
AVDD
0.1µF
C45
60 ohm
FB4
CLK
10µF
C46
GND
10pF
C47
R
X
1
1
R
X
2
2
V
C
OM
3
L
NAOU
T
4
P
GAIN
5
P
G
AOU
T
6
C
OM
P
IN
7
R
TD1
8
R
TD2
9
R
R
E
F
1
0
C
HS
EL
1
1
E
R
RB
1
2
S
T
A
R
T
1
3
S
T
OP
1
4
E
N
1
5
TR
IGGE
R
1
6
R
E
S
ET
1
7
S
C
L
K
1
8
C
S
B
1
9
S
D
I
2
0
S
D
O
2
1
V
IO
2
2
V
D
D
2
3
V
D
D
2
4
C
LKIN
2
5
GN
D
2
6
TX
2
2
7
TX
1
2
8
U10
TDC1000PW
IO1
1
IO2
2
IO3
3
IO4
4
IO5
5
IO6
6
IO7
7
IO8
8
EP
9
U11
TPD8E003DQDR
CLKIN
1
1G
2
Y0
3
GND
4
NC
5
VDD
6
NC
7
Y1
8
U8
CDCLVC1102PW
CLKIN
1
1G
2
Y0
3
GND
4
NC
5
VDD
6
NC
7
Y1
8
U7
CDCLVC1102PW
V3p3
V3p3
GND
200
R30
200
R32
0
R43
0
R42
5600pF
C36
510pF
C27
510pF
C32
5.36k
R31
0
R41
DNP
0
R52
DNP
VDD
4
STANDBY
1
GND
2
OUT
3
13 MHz
Y2
SG-210STF13.000000MHZS
1
2 3 4 5
J7
142-0701-201
DNP
1
2 3 4 5
J3
142-0701-201
DNP
1
2 3 4 5
J4
142-0701-201
DNP
1
2 3 4 5
J8
142-0701-201
1
3
5 6
4
2
7
9 10
8
12 11
14 13
J5
SSW-107-02-G-D-RA
1
3
5
6
4
2
7
9
10
8
J6
PPPC052LJBN-RC
1
2
JP3
1
2
JP4
1 2 3
JP5
TRIGGER_SOURCE_SEL
1 2
3 4
5 6
JP6
TP5
TP7
TP6
TP8
TP18 TP10
TP16 TP15
TP11
50
R39
50
R46
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TDC1000-GASEVM Schematic
13 TDC1000-GASEVM Schematic
Figure 23. TDC1000-GASEVM Schematic 1
29 SNIU026A – March 2015 – Revised December 2015 TDC1000-GASEVM and TDC1000-BSTEVM Kit User’s Guide
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