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TAS5707, TAS5707A

SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009

www.ti.com

ERROR STATUS REGISTER (0x02)

The error bits are sticky and are not cleared by the hardware. This means that the software must clear the
register (write zeroes) and then read them to determine if they are persistent errors.

Error Definitions:

MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing.

SCLK Error: The number of SCLKs per LRCLK is changing.

LRCLK Error: LRCLK frequency is changing.

Frame Slip: LRCLK phase is drifting with respect to internal frame sync.

Table 7. Error Status Register (0x02)

D7

D6

D5

D4

D3

D2

D1

D0

FUNCTION

1

-

MCLK error

1

PLL autolock error

1

SCLK error

1

LRCLK error

1

Frame slip

1

Overcurrent, overtemperature, overvoltage or undervoltage error

1

Overtemperature warning (sets around 125°)

0

0

0

0

0

0

0

0

No errors

(1)

(1)

Default values are in bold.

SYSTEM CONTROL REGISTER 1 (0x03)

The system control register 1 has several functions:

Bit D7:

If 0, the dc-blocking filter for each channel is disabled.
If 1, the dc-blocking filter (–3 dB cutoff <1 Hz) for each channel is enabled (default).

Bit D5:

If 0, use soft unmute on recovery from clock error. This is a slow recovery. Unmute takes same
time as volume ramp defined in reg 0X0E.
If 1, use hard unmute on recovery from clock error (default). This is a fast recovery, a single step
volume ramp

Bits D1–D0: Select de-emphasis

Table 8. System Control Register 1 (0x03)

D7

D6

D5

D4

D3

D2

D1

D0

FUNCTION

0

PWM high-pass (dc blocking) disabled

1

PWM high-pass (dc blocking) enabled

(1)

0

Reserved

(1)

0

Soft unmute on recovery from clock error

1

Hard unmute on recovery from clock error

(1)

0

Reserved

(1)

0

Reserved

(1)

0

Reserved

(1)

0

0

No de-emphasis

(1)

0

1

De-emphasis for f

S

= 32 kHz

1

0

Reserved

1

1

De-emphasis for f

S

= 48 kHz

(1)

Default values are in bold.

38

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Copyright © 2008–2009, Texas Instruments Incorporated

Product Folder Link(s):

TAS5707 TAS5707A

Summary of Contents for TAS5707

Page 1: ...ble data path routes General Features these channels to the internal speaker drivers Serial Control Interface Operational Without MCLK The TAS5707 is a slave only device receiving all clocks from exte...

Page 2: ...tegrated circuits be handled with appropriate precautions Failure to observe proper handling and installation procedures can cause damage ESD damage can range from subtle performance degradation to co...

Page 3: ...e Rate Autodetect and PLL Serial Control Microcontroller Based System Control Terminal Control OUT_A OUT_B 2 HB FET Out OUT_C OUT_D 2 HB FET Out B0262 02 TAS5707 TAS5707A www ti com SLOS556B NOVEMBER...

Page 4: ...ate Drive Ctrl PWM Rcv PWM_A OUT_A PGND_AB PVDD_A BST_A Timing Gate Drive Ctrl PWM Rcv GVDD_AB Ctrl Pulldown Resistor Pulldown Resistor Pulldown Resistor Pulldown Resistor 4 GVDD_CD Regulator GVDD_AB...

Page 5: ...SDA SCL DVSS GND VREG BST_B PVDD_B PVDD_C OUT_C PVDD_D BST_D PGND_AB OUT_B PGND_CD OUT_D AGND PGND_AB PVDD_B PGND_CD PVDD_D BST_C PVDD_C GVDD_OUT P0075 01 PHP Package Top View TAS5707 1 2 3 4 5 6 7 8...

Page 6: ...device for loss of power supplies by shutting down the noise shaper and initiating PWM stop sequence PGND_AB 47 48 P Power ground for half bridges A and B PGND_CD 37 38 P Power ground for half bridge...

Page 7: ...nge Tstg 40 to 125 C 1 Stresses beyond those listed under absolute ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any...

Page 8: ...ut filter inductance H short circuit condition 1 Continuous operation above the recommended junction temperature may result in reduced reliability and or lifetime of the device PWM OPERATION AT RECOMM...

Page 9: ...e 30 55 IPVDD Half bridge supply current No load PVDD_X mA Reset RESET low 5 13 PDN high Drain to source resistance LS TJ 25 C includes metallization resistance 180 rDS on 1 m Drain to source resistan...

Page 10: ...PVDD 12 V 10 THD 1 kHz input 9 4 signal PO Power output per channel W PVDD 12 V 7 THD 1 kHz input signal 8 9 PVDD 8 V 10 THD 1 kHz input signal 4 1 PVDD 8 V 7 THD 1 kHz input signal 3 8 PVDD 18 V PO 1...

Page 11: ...h1 Hold time LRCLK from SCLK rising edge 10 ns tsu2 Setup time SDIN to SCLK rising edge 10 ns th2 Hold time SDIN from SCLK rising edge 10 ns LRCLK frequency 8 48 48 kHz SCLK duty cycle 40 50 60 LRCLK...

Page 12: ...se duration SCL high 0 6 s tw L Pulse duration SCL low 1 3 s tr Rise time SCL and SDA 300 ns tf Fall time SCL and SDA 300 ns tsu1 Setup time SDA to SCL 100 ns th1 Hold time SCL to SDA 0 ns t buf Bus f...

Page 13: ...se refer to Recommended Use Model section on usage of all terminals PARAMETER MIN TYP MAX UNIT tw RESET Pulse duration RESET active 100 us td I2C_ready Time to enable I2 C 13 5 ms NOTE On power up it...

Page 14: ...Output Power W 0 01 PVDD 8 V RL 8 0 1 1 10 THD N Total Harmonic Distortion Noise 0 001 0 01 10 40 0 1 G006 1 f 20 Hz f 1 kHz f 10 kHz TAS5707 TAS5707A SLOS556B NOVEMBER 2008 REVISED NOVEMBER 2009 www...

Page 15: ...ight to Left PO 0 25 W PVDD 18 V RL 8 100 90 80 70 60 50 40 30 20 10 0 f Frequency Hz Crosstalk dB G014 20 100 1k 10k 20k Left to Right Right to Left PO 0 25 W PVDD 12 V RL 8 TAS5707 TAS5707A www ti c...

Page 16: ...eft PO 0 25 W PVDD 8 V RL 8 TAS5707 TAS5707A SLOS556B NOVEMBER 2008 REVISED NOVEMBER 2009 www ti com TYPICAL CHARACTERISTICS BTL CONFIGURATION continued CROSSTALK vs FREQUENCY Figure 16 16 Submit Docu...

Page 17: ...during the remaining part of the PWM cycle Special attention should be paid to the power stage power supply this includes component selection PCB placement and routing As indicated each half bridge ha...

Page 18: ...ller than 2 2 nF will decrease the start up time The SSTIMER pin should be left floating for BD modulation CLOCK AUTO DETECTION AND PLL The TAS5707 is a slave device It accepts MCLK SCLK and LRCLK The...

Page 19: ...e interface to receive commands from a system controller The serial control interface supports both normal speed 100 kHz and high speed 400 kHz operations without wait states As an added feature this...

Page 20: ...l 16 Bit Mode 1 1 15 15 14 14 MSB LSB 16 Clks Right Channel 2 Channel I S Philips Format Stereo Input 2 T0266 01 3 3 2 2 5 5 4 4 9 9 8 8 0 13 13 10 10 11 11 12 12 SCLK MSB LSB TAS5707 TAS5707A SLOS556...

Page 21: ...the left channel and when it is for the right channel LRCLK is high for the left channel and low for the right channel A bit clock running at 32 48 or 64 fS is used to clock in the data The first bit...

Page 22: ...Mode 1 1 15 15 14 14 MSB LSB 16 Clks Right Channel 2 Channel Left Justified Stereo Input T0266 02 3 3 2 2 5 5 4 4 9 9 8 8 0 0 13 13 10 10 11 11 12 12 SCLK MSB LSB TAS5707 TAS5707A SLOS556B NOVEMBER 20...

Page 23: ...channel and when it is for the right channel LRCLK is high for the left channel and low for the right channel A bit clock running at 32 48 or 64 fS is used to clock in the data The first bit of data a...

Page 24: ...5 19 18 1 5 19 18 1 5 0 0 0 2 2 2 6 6 6 15 14 15 14 23 22 1 15 14 5 19 18 1 5 19 18 1 5 0 0 0 2 2 2 6 6 6 15 14 15 14 LSB TAS5707 TAS5707A SLOS556B NOVEMBER 2008 REVISED NOVEMBER 2009 www ti com Figur...

Page 25: ...ime of the clock period These conditions are shown in Figure 26 The master generates the 7 bit slave address and the read write R W bit to open communication with another device and then waits for an...

Page 26: ...smitted determines how many subaddresses are written As was true for random addressing sequential addressing requires that a complete set of data be transmitted If only a partial set of data is writte...

Page 27: ...memory address to be read As a result the read write bit becomes a 0 After receiving the TAS5707 address and the read write bit TAS5707 responds with an acknowledge bit In addition after sending the i...

Page 28: ...e is one ganged DRC for the left right channels The DRC input output diagram is shown in Figure 31 Professional quality dynamic range compression automatically adjusts volume to flatten volume level O...

Page 29: ...ith bits 2 0 being 001 010 or 011 brings the system into the coefficient bank update state update bank1 update bank2 or update bank3 respectively Any subsequent write to bankable locations updates the...

Page 30: ...most significant bit is a logic 1 then the number is a negative number In this case every bit must be inverted a 1 added to the result and then the weighting shown in Figure 34 applied to obtain the m...

Page 31: ...PLL 1 1 ms 1 3 t stop 2 0 ns Normal Operation Shutdown Powerdown 1 t has to be greater than 240 ms 1 3 t This constraint only applies to the first trim command following AVDD DVDD power up It does no...

Page 32: ...amp up AVDD DVDD to at least 3V 2 Initialize digital inputs and PVDD supply as follows Drive RESETZ 0 PDNZ 1 and other digital inputs to their desired state while ensuring that all are never more than...

Page 33: ...tion sequence Exit 1 Ensure I2S clocks have been stable and valid for at least 50ms 2 Write 0x00 to register 0x05 exit shutdown command may not be serviced for as much as 240ms after trim following AV...

Page 34: ...sequent section 0x02 0x11 IC delay channel 1 1 Description shown in subsequent section 0xAC 0x12 IC delay channel 2 1 Description shown in subsequent section 0x54 0x13 IC delay channel 3 1 Description...

Page 35: ...000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2 25 0 0x0000 0000 0x30 ch2_bq 0 20 u 31 26 b0 25 0 0x0080 0000 u 31 26 b1 25 0 0x0000 0000 u 31 26 b2 25 0 0x0000 0000 u 31 26 a1 25 0 0x0000 0000 u 31 26 a2...

Page 36: ...0 0000 0x3C 8 DRC 1 ad u 31 26 1 ad 25 0 0x0000 0000 0x3D 0x3F Reserved 2 0x40 DRC T 4 T 31 0 9 23 format 0xFDA2 1490 0x41 DRC K 4 u 31 26 K 25 0 0x0384 2109 0x42 DRC O 4 u 31 26 O 25 0 0x0008 4210 0x...

Page 37: ...05 24 kHz sample rate 1 1 0 fs 8 kHz sample rate 1 1 1 fs 11 025 12 kHz sample rate 0 0 0 MCLK frequency 64 fS 3 0 0 1 MCLK frequency 128 fS 3 0 1 0 MCLK frequency 192 fS 4 0 1 1 MCLK frequency 256 f...

Page 38: ...e in bold SYSTEM CONTROL REGISTER 1 0x03 The system control register 1 has several functions Bit D7 If 0 the dc blocking filter for each channel is disabled If 1 the dc blocking filter 3 dB cutoff 1 H...

Page 39: ...16 0000 0 0 0 0 Right justified 20 0000 0 0 0 1 Right justified 24 0000 0 0 1 0 I2 S 16 000 0 0 1 1 I2 S 20 0000 0 1 0 0 I2 S 1 24 0000 0 1 0 1 Left justified 16 0000 0 1 1 0 Left justified 20 0000 0...

Page 40: ...own hard mute 1 0 Exit all channel shutdown normal operation 0 0 0 0 0 0 Reserved 1 1 Default values are in bold SOFT MUTE REGISTER 0x06 Writing a 1 to any of the following bits sets the output of the...

Page 41: ...egisters 0x07 0x08 0x09 D D D D D D D D FUNCTION 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 24 dB 0 0 1 1 0 0 0 0 0 dB default for individual channel volume 1 1 1 0 0 1 1 0 1 78 5 dB 1 1 0 0 1 1 1 0 79 0 dB 1 1...

Page 42: ...steps in a volume ramp Volume steps occur at a rate that depends on the sample rate of the I2S data as follows Sample Rate KHz Approximate Ramp Rate 8 16 32 125 us step 11 025 22 05 44 1 90 7 us step...

Page 43: ...1 Maximum positive delay 31 4 DCLK cycles 1 0 0 0 0 0 Maximum negative delay 32 4 DCLK cycles 0 0 RESERVED SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 Delay value 4 DCLKs 0x11 1 0 1 0 1 1 Default value for ch...

Page 44: ...duty cycle start stop period 0 1 1 1 1 125 7 ms 50 duty cycle start stop period 1 1 0 0 0 0 164 6 ms 50 duty cycle start stop period 1 0 0 0 1 239 4 ms 50 duty cycle start stop period 1 0 0 1 0 314 2...

Page 45: ...x1C When a back end error signal is received from the internal power stage the power stage is reset stopping all PWM activity Subsequently the modulator waits approximately for the time listed in Tabl...

Page 46: ...erved 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Ground 0 to channel 2 1 1 1 Reserved D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION 0 1 1 1 0 1 1 1 Reserved 1 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 1 1 1...

Page 47: ...C 1 1 Multiplex channel 2 to OUT_C 0 0 Reserved 1 0 0 Multiplex channel 1 to OUT_D 0 1 Multiplex channel 2 to OUT_D 1 0 Multiplex channel 1 to OUT_D 1 1 Multiplex channel 2 to OUT_D 1 D7 D6 D5 D4 D3 D...

Page 48: ...ed 1 0 44 1 48 kHz does not use bank 2 1 44 1 48 kHz uses bank 2 1 0 16 kHz does not use bank 2 1 1 16 kHz uses bank 2 0 22 025 24 kHz does not use bank 2 1 1 22 025 24 kHz uses bank 2 0 8 kHz does no...

Page 49: ...2 L and R are ganged for EQ biquads a write to Left channel BQ is 1 also written to Right channel BQ 0X29 2F is ganged to 0X30 0X36 0 Reserved 2 0 0 0 No bank switching All updates to DAP 2 0 0 1 Con...

Page 50: ...age test conditions 9 Added rows to Electrical Characteristics fro OTW and OTW 9 Changed OLPC typical value to 0 63 ms 9 Replaced text of Overtemperature Protection section 18 Added address informatio...

Page 51: ...en defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not...

Page 52: ...better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or...

Page 53: ...mm Pin1 Quadrant TAS5707APHPR HTQFP PHP 48 1000 330 0 16 4 9 6 9 6 1 5 12 0 16 0 Q2 TAS5707APHPR HTQFP PHP 48 1000 330 0 16 4 9 6 9 6 1 5 12 0 16 0 Q2 TAS5707PHPR HTQFP PHP 48 1000 330 0 16 4 9 6 9 6...

Page 54: ...Width mm Height mm TAS5707APHPR HTQFP PHP 48 1000 367 0 367 0 38 0 TAS5707APHPR HTQFP PHP 48 1000 336 6 336 6 31 8 TAS5707PHPR HTQFP PHP 48 1000 367 0 367 0 38 0 TAS5707PHPR HTQFP PHP 48 1000 336 6 33...

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Page 59: ...TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD...

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