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Appendix D 4 x SE AD
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Appendix D
01
1B
00
Oscillator Trim
01
03
A0
System Control Register 1
01
04
05
Serial Data Interface Register
01
05
00
System Control Register 2
01
06
00
Soft Mute Register
01
07
FF
Master Volume Register (0xFF = Mute)
01
08
30
Channel 1 Volume
01
09
30
Channel 2 Volume
01
0A
30
Channel 3 Volume
01
0B
30
Channel 4 Volume
01
0C
30
Channel 5 Volume
01
0D
1C
Channel 6 Volume
01
0E
91
Micro Register
01
10
02
Modulation Limit
01
18
0F
PWM Start Register
01
19
30
Shutdown Group Resister
01
1A
95
Split Capacitor Charge Period
01
1C
02
Back-end Error Register
00
01
(Below)
Input Mux Register
02
20
0A
01
23
66
00
01
(Below)
Downmix Register
02
21
00
00
40
03
00
01
(Below) AM Mode Register
02
22
00
00
00
00
00
01
(Below) Biquad1 Coeff
02
23
00
80
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
01
(Below) Biquad2 Coeff
02
24
00
80
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
01
(Below)
PWM Output MUX Register (Note: Writes to this register affect Inter-Channel Delay)
02
25
01
01
23
45
00
01
(Below) 1/G
02
26
00
80
00
00
00
01
(Below) Scale = 1/(1-1/G)
02
28
00
80
00
00
01
11
20
Inter-Channel Delay Channel 1
01
12
A0
Inter-Channel Delay Channel 2
01
13
E0
Inter-Channel Delay Channel 3
01
14
60
Inter-Channel Delay Channel 4
01
15
04
Inter-Channel Delay Channel 5
01
16
FC
Inter-Channel Delay Channel 6
01
17
00
Offset Register (Absolute Delay)
SLOU220 – September 2008
4 x SE AD
31