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1.2
PCB Key Map
SPEAKER OUTPUTS
4-CHANNEL
POWER STAGE
TAS5132
INPUT SIGNAL
INTERFACE (J60)
CONTROL
INTERFACE (J40)
TAS5086
3.3 V
Regulator
2-CHANNEL
POWER STAGE
TAS5132
J101
J102
J103
J104
J105
J106
5V
Regulator
GateDrive
Regulator
PSU
INTERF
ACE
(J901)
BTL
SE
2
Quick Setup Guide
2.1
Electrostatic Discharge Warning
Quick Setup Guide
Physical structure for the TAS5132DDV6EVM is illustrated in
Figure 2. Physical Structure for TAS5132DDV6EVM (Approximate Layout)
This section describes the TAS5132DDV6EVM board in regards to power supplies and system interfaces.
It provides information regarding handling and unpacking, absolute operating conditions, and a description
of the factory default switch and jumper configuration.
This section also provides a step-by-step guide to configuring the TAS5132DDV6EVM for device
evaluation.
Many of the components on the TAS5132DDV6EVM are susceptible to damage by electrostatic discharge
(ESD). Customers are advised to observe proper ESD handling precautions when unpacking and handling
the EVM, including the use of a grounded wrist strap at an approved ESD workstation.
CAUTION
Failure to observe ESD handling procedures can result in damage to EVM
components.
TAS5132DDV6EVM
4
SLLU096A – February 2007 – Revised March 2007