background image

GND

GPIO2

GND

GND

SW2

SW

E1

SBCK

A2

FSYNC

A3

SDIN

B2

SDOUT

B1

SCL

A4

SDA

A5

AD1

B3

SD

A1

GPIO

C6

VBST

F2

VBAT

C1

VDD

B6

PVDD

F4

DREG

A6

OUT_P

E5

OUT_N

E6

VSNS_P

C5

VSNS_N

C3

GNDB

D1

VBAT

C2

AD0

B4

IRQ

B5

GREG

C4

GNDB

D2

GNDB

D3

GND

D4

PGND

D5

SW

E2

SW

E3

GNDD

E4

VBST

F1

VBST

F3

PVDD

F5

PVDD

F6

PGND

D6

TAS2562YFPR

U2

SW

E1

SBCK

A2

FSYNC

A3

SDIN

B2

SDOUT

B1

SCL

A4

SDA

A5

AD1

B3

SD

A1

GPIO

C6

VBST

F2

VBAT

C1

VDD

B6

PVDD

F4

DREG

A6

OUT_P

E5

OUT_N

E6

VSNS_P

C5

VSNS_N

C3

GNDB

D1

VBAT

C2

AD0

B4

IRQ

B5

GREG

C4

GNDB

D2

GNDB

D3

GND

D4

PGND

D5

SW

E2

SW

E3

GNDD

E4

VBST

F1

VBST

F3

PVDD

F5

PVDD

F6

PGND

D6

TAS2562YFPR

U1

GND

1.8V

IRQZ

CONTROL

SDZ

I2C

SCL
SDA

VBAT

VBAT

GND

1.8V

GND

DF2SE

<

>

>

>

SDZ

IRQZ

SDOUT

SCL
SDA

FSYNC

SBCLK

SDIN

>

<

>

> <

GND

SDIN

SBCLK
FSYNC

SDOUT

ASI

VSENSE2-


VSENSE1-

DF2SE

0

R4

0

R5

VSENSE2-

J5

OUT2

OUT-2P

OUT-2N

OUT2+

OUT2-

1

2

3

J10

AD0

1

2

3

J11

AD1

1

2

3

J12

AD0

1

2

3

J13

AD1

0

R1

0

R2

0

R11

0

R12

J8

OUT1

OUT-1P

OUT-1N

OUT1+

OUT1-

0

R8

0

R9

DF2SE

VSENSE1-

IRQ2Z

SDZ

1.8V

10.0k

R6

SCL
SDA

SDIN

SBCLK
FSYNC

SDOUT

TP3

SBCLK

SCL

SDA

SDIN

SBCLK

FSYNC

IRQZ

SDZ

TP6

FSYNC

TP9

SDIN

TP4

SCL

TP7

SDA

TP5

IRQZ

TP8

SDZ

VDD2

GND

VBAT

1.8V

J4
VDD2

GND

GND

GND

GND

J3
VBAT2

VBAT2

GND

GND

0.1µF

C12

GND

GND

AD0-2
AD1-2

AD0-2

AD1-2

GREG2

PVDD2

SW1

SDZ

SCL
SDA

SDIN

SBCLK
FSYNC

VDD1

GND

VBAT

1.8V

J7
VDD1

GND

GND

GND

GND

VBAT1

GND

GND

GND

GND

PVDD1

0.1µF

C24

GND

GREG1

IRQZ

GND

GND

DREG1

DREG2

GPIO1

SDOUT

AD0-1

AD1-1

AD0-1
AD1-1

SDOUT

TP10

SDOUT

GPIO

>

IRQ2Z

IRQZ

0

R7

1

2

3

4

J9

GPIO SEL

GPIO2
GPIO1

CHANNEL 2

CHANNEL 1

0.1µF

C3

DNP

0.01uF

C5

DNP

4.7uF

C4

0.01uF

C11

DNP

0.01uF

C7

DNP

0.1µF

C15

DNP

0.01uF

C17

DNP

4.7uF

C16

0.01uF

C23

DNP

0.01uF

C19

DNP

PVDD1

PVDD2

TP11

PVDD1

TP1

PVDD2

GND

TP13

GND

TP14

GND

TP2

GND

1uH

L1

1uH

L2

GND

GND

GND

GND

0.01uF

C8

DNP

0.01uF

C20

DNP

GND

TP12

GND

ASI

10uF

C13

10uF

C14

10uF

C18

10uF

C22

10uF

C1

10uF

C10

10uF

C2

10uF

C6

0

R10

DNP

VBAT

0

R13

DNP

VBAT

A0

1

A1

2

A2

3

VSS

4

SDA

5

SCL

6

WP

7

VCC

8

24FC512-I/ST

U3

3.3V

GND

SCL

SDA

GND

3

VCC

5

U4B

LVC1G125

GND

4

1

2

U4A

LVC1G125

GPIO

GND

1.8V

GND

0.1µF

C29

3.3V

GND

0.1µF

C30

1.8V

1
3
5

6

4

2

7
9

10

8

12

11

14

13

16

15

18

17

20

19

22

21

24

23

26

25

28

27

30

29

32

31

34

33

36

35

38

37

40

39

J1

Power/Analog

1
3
5

6

4

2

7
9

10

8

12

11

14

13

16

15

18

17

20

19

22

21

24

23

26

25

28

27

30

29

32

31

34

33

36

35

38

37

40

39

J2

ASI/I2C/CONTROL

1uH

L3

DNP

1uH

L4

DNP

1µF

C21

1µF

C9

C27

DNP

C28

DNP

C25

DNP

C26

DNP

J14
OUT2

J15
OUT1

J6
VBAT1

GND

J16

WP

10.0k

R3

GPIO

VSENSE2-

VSENSE1-

New Part Number Requested

IOVDD

IOVDD

IOVDD

EVM Schematics

www.ti.com

10

SLAU788 – October 2018

Submit Documentation Feedback

Copyright © 2018, Texas Instruments Incorporated

TAS2562YFPEVM-DC User's Guide

8

EVM Schematics

Figure 12. EVM Schematic

Summary of Contents for TAS2562YFPEVM-DC

Page 1: ...ruments USB Audio Device Control Panel 6 7 Windows Playback device Sample Rate 7 8 Stereo Setup 7 9 Windows Playback Devices 8 10 Texas Instruments USB Audio Device Control Panel 8 11 Windows Playback device Sample Rate 9 12 EVM Schematic 10 13 TAS2562YFPEVM DC Top Assembly 11 14 TAS2562YFPEVM DC Top Silk Screen 11 15 TAS2562YFPEVM DC Top Solder Mask 11 16 TAS2562YFPEVM DC Top Copper 11 17 TAS2562...

Page 2: ... demonstrate the performance of TAS2562 in a stereo configuration The design utilizes the PPC3 EVM MB hardware to provide an interface and supply voltages to the EVM TAS2562 is a mono digital input Class D audio amplifier optimized for efficiently driving high peak power into small loudspeaker applications The Class D amplifier is capable of delivering 6W of peak power into a 4 Ω load at a battery...

Page 3: ...ed with PPC3 running the TAS2562 plug in To request access to the software first request a myTI com account here After creating an account navigate to the TAS2562 product page and follow the link in the information box to request access to the software Figure 1 Requesting PPC3 Access 6 Device Configuration The default configuration for the TAS2562 is described below in Table 2 and Figure 2 6 1 Def...

Page 4: ...User s Guide Figure 2 Default Jumper Settings 6 2 Address Select Jumpers Table 3 Address Select Jumpers Address Pin A0 Pin A1 0x98 L L 0x9A H L 0x9C L H 0x9E H H Figure 3 Address Select TAS2562 supports 4 user configurable I2 C addresses shown in Section 6 2 Use J12 J13 to configure Channel 1 and J10 J11 to configure Channel 2 as shown in Figure 3 ...

Page 5: ...DC 3 Remove the jumpers at J3 and J4 as shown in Figure 4 Figure 4 Mono Setup 4 Set the jumpers at J12 and J13 to the desired I2 C address as shown in Section 6 2 5 Configure PPC3 EVM MB as described in SLEU120 USB control for I2 C USB control for I2S 3 3 V I2 C 3 3 V I2S 1 8 V IOVDD 6 Connect a 5V supply to connector J12 or J11 on PPC3 EVM MB 7 Connect a Micro USB Cable from PC to PPC3 EVM MB 8 V...

Page 6: ...2562YFPEVM DC User s Guide Figure 5 Windows Playback Devices 9 Set the maximum bit depth using the Texas Instruments USB Audio Device Control Panel found in the system tray Figure 6 Texas Instruments USB Audio Device Control Panel 10 Set the sampling rate Right click TI USB AUdio UAC2 0 Select Properties Click advanced tab Select Rate ...

Page 7: ...ws Playback device Sample Rate 11 Configure the device using the TAS2562 PPC3 Plug in 6 4 Stereo Setup Use the following instructions to complete a stereo setup 1 Install PPC3 with the TAS2562 plug in 2 Connect a speaker to both J8 and J5 on the TAS2562YFPEVM DC 3 Set the jumpers at J12 J13 and J11 J10 to the unique I2 C address as shown in Section 6 2 Figure 8 Stereo Setup ...

Page 8: ... J12 or J11 on PPC3 EVM MB 6 Connect a Micro USB Cable from PC to PPC3 EVM MB 7 Verify that TI USB Audio UAC2 0 is the default playback device by opening the sound dialog from the Windows Control Panel Figure 9 Windows Playback Devices 8 Set the maximum bit depth using the Texas Instruments USB Audio Device Control Panel found in the system tray Figure 10 Texas Instruments USB Audio Device Control...

Page 9: ... interfaces on the TAS2770EVM Reference Board through hardware settings and software settings Several headers on PPC3 EVM MB allow access to the following digital audio signals I2S Data out SDOUT from the TAS2562 for example current and voltage sense data I2S Data in SDIN to the TAS2562 I2S Word clock or frame sync FSYNC I2S Bit clock SBCLK I2 C Clock SCLK I2 C Data SDA The selection between USB i...

Page 10: ...Z SCL SDA SDIN SBCLK FSYNC VDD1 GND VBAT 1 8V J7 VDD1 GND GND GND GND VBAT1 GND GND GND GND PVDD1 0 1µF C24 GND GREG1 IRQZ GND GND DREG1 DREG2 GPIO1 SDOUT AD0 1 AD1 1 AD0 1 AD1 1 SDOUT TP10 SDOUT GPIO IRQ2Z IRQZ 0 R7 1 2 3 4 J9 GPIO SEL GPIO2 GPIO1 CHANNEL 2 CHANNEL 1 0 1µF C3 DNP 0 01uF C5 DNP 4 7uF C4 0 01uF C11 DNP 0 01uF C7 DNP 0 1µF C15 DNP 0 01uF C17 DNP 4 7uF C16 0 01uF C23 DNP 0 01uF C19 D...

Page 11: ...1 SLAU788 October 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated TAS2562YFPEVM DC User s Guide 9 EVM Layer Plots Figure 13 TAS2562YFPEVM DC Top Assembly Figure 14 TAS2562YFPEVM DC Top Silk Screen ...

Page 12: ...w ti com 12 SLAU788 October 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated TAS2562YFPEVM DC User s Guide Figure 15 TAS2562YFPEVM DC Top Solder Mask Figure 16 TAS2562YFPEVM DC Top Copper ...

Page 13: ...r Plots 13 SLAU788 October 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated TAS2562YFPEVM DC User s Guide Figure 17 TAS2562YFPEVM DC Copper Layer 2 Figure 18 TAS2562YFPEVM DC Copper Layer 3 ...

Page 14: ... ti com 14 SLAU788 October 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated TAS2562YFPEVM DC User s Guide Figure 19 TAS2562YFPEVM DC Copper Layer 4 Figure 20 TAS2562YFPEVM DC Copper Layer 5 ...

Page 15: ...er Plots 15 SLAU788 October 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated TAS2562YFPEVM DC User s Guide Figure 21 TAS2562YFPEVM DC Bottom Copper Figure 22 TAS2562YFPEVM DC Bottom Solder ...

Page 16: ...Materials Table 4 Bill of Materials Designator Value Description PackageRefer ence PartNumber Manufacturer Alternate PartNumber Alternate Manufacturer PCB1 Printed Circuit Board AMPS043 Any C1 C2 C6 C10 C13 C14 C18 C22 10uF CAP CERM 10 uF 35 V 10 X7R AEC Q200 Grade 1 1206_190 1206_190 CGA5L1X7R1 V106K160AC TDK C4 C16 4 7uF CAP CERM 4 7 uF 10 V 10 X5R 0603 0603 CGB3B1X5R1 A475K055AC TDK C9 C21 1uF ...

Page 17: ...utions L1 L2 1uH Inductor Shielded Metal Composite 1 uH 3 3 A 0 04 ohm SMD 2 5x1 2x2mm DFE252012F 1R0M P2 MuRata Toko R1 R2 R8 R9 0 RES 0 5 0 125 W 0805 0805 RC0805JR 070RL Yageo America R3 R6 10 0k RES 10 0 k 1 0 063 W AEC Q200 Grade 0 0402 0402 RMCF0402FT 10K0 Stackpole Electronics Inc R4 R5 R11 R12 0 RES 0 5 0 063 W 0402 0402 ERJ 2GE0R00X Panasonic R7 0 RES 0 5 0 1 W 0603 0603 ERJ 3GEY0R00V Pan...

Page 18: ...SN74LVC1G1 25DCKR Texas Instruments C3 C15 0 1uF CAP CERM 0 1 µF 25 V 10 X7R AEC Q200 Grade 1 0402 0402 CGA2B3X7R1 E104K050BB TDK C5 C7 C8 C11 C17 C19 C20 C23 0 01uF CAP CERM 0 01 uF 25 V 10 X7R 0402 0402 GCM155R71E 103KA37D MuRata C25 C26 C27 C28 1uF CAP CERM 1 µF 16 V 20 X7R 0603 0603 CL10B105MO 8NNWC Samsung FID1 FID2 FID3 FID4 FID5 FID6 Fiducial mark There is nothing to buy or mount N A N A N ...

Page 19: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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