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Board Layout
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SLVUB34 – April 2017
Copyright © 2017, Texas Instruments Incorporated
TPS561201EVM-896 1-A, SWIFT™ Regulator Evaluation Module
5
Board Layout
This section provides a description of the TPS561201EVM-896, board layout, and layer illustrations.
5.1
Layout
The board layouts for the TPS561201EVM-896 are shown in
, and
. The top
layer contains the main power traces for VIN, VOUT, and ground. Also on the top layer are connections
for the pins of the TPS561201 and a large area filled with ground. Most of the signal traces are also
located on the top side. The input decoupling capacitors, C1, C2, and C3 are located as close to the IC as
possible. The input and output connectors, test points, and all of the components are located on the top
side. The bottom layer is a ground plane along with the switching node copper fill, signal ground copper
fill, and the feedback trace from the point of regulation to the top of the resistor divider network.
Figure 14. Top Assembly
Figure 15. Top Layer
Figure 16. Bottom Layer