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Board Layout
12
SBOU212 – September 2018
Copyright © 2018, Texas Instruments Incorporated
INA1651EVM SoundPlus™ High Common-Mode Rejection Line Receiver
Evaluation Module
5
Board Layout
This section provides a description of the INA1651EVM board layout and layer illustrations.
5.1
Layout
The board layout for the INA1651EVM is shown in
and
. The top layer consists of all
signal traces and is poured with a solid ground plane. The traces of the positive input (IN+ A) and negative
input (IN- A) were kept as balanced as possible to reduce the possibility of a differential voltage from
developing due to trace impedance mismatch. The decoupling capacitors, C5, C6, C11, and C12, were
positioned as close as possible to the power supply pins of the device. Minimal traces were routed on the
bottom layer so that a large solid ground plane could be poured. Vias were placed at the ground
connection of every component to provide a low-impedance path on the bottom layer back to the supply
ground. The trace from J8 to VREF A was kept as short as possible to maintain the exceptional common-
mode rejection of the INA1651.
Figure 11. Top Layer PCB Layout