Texas Instruments SN65LVCP114 User Manual Download Page 18 | Manualshive

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Board Layout

10

Board Layout

Figure 11. SN65LVCP114 EVM PCB Layer Construction

NOTE: Always consult your board manufacturer for their process/design requirements to ensure
the desired impedance is achieved.

18

SN65LVCP114 Evaluation Module (EVM)

SLLU160

–

December 2011

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Copyright

©

2011, Texas Instruments Incorporated

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Summary of Contents for SN65LVCP114

Page 1: ... provides guidance on the device s proper use by showing some operating configurations and test modes The EVM board schematic and layout information are also provided for the customer Information in this guide assists the customer in choosing the optimal design methods and materials in designing a complete system 1 SLLU160 December 2011 SN65LVCP114 Evaluation Module EVM Submit Documentation Feedba...

Page 2: ...5 List of Figures 1 SN65LVCP114 EVM 4 2 SN65LVCP114 EVM Jumper Description 5 3 SN65LVCP114 EVM Schematic Port A 8 4 SN65LVCP114 EVM Schematic Port B 9 5 SN65LVCP114 EVM Schematic Port C 10 6 SN65LVCP114 EVM Schematic Controls_1 11 7 SN65LVCP114 EVM Schematic Controls_2 12 8 SN65LVCP114 EVM Schematic Controls_3 13 9 SN65LVCP114 EVM Schematic Power Distribution 14 10 SN65LVCP114 EVM Schematic USB In...

Page 3: ...eve this the board s impedance is controlled to 50 Ω single ended or 100 Ω differential impedance for both the low and high speed differential serial and clock connections The use of vias is minimized and when necessary are designed to minimize impedance discontinuities along the transmission line Care was taken to control trace length mismatch board skew to less than 0 1 MIL The board layout is d...

Page 4: ...lane switching Each of the ports are independently programmed for receive equalization The device also supports loopback on all three ports The EVM provides SMA connections for one lane per port for device evaluation with full configuration control of the device through I2C using the SN65LVCP114 GUI provided Limited configuration control is available through GPIO Refer to Section 7 for more detail...

Page 5: ...BOUTN2 Differential output lane 2 Fabric switch B side J9 J11 CINP2 CINN2 Differential input lane 2 Fabric switch C side J10 J12 COUTP2 COUTN2 Differential output lane 2 Fabric switch C side P1 VCC Banana jack positive power supply connection P2 GND Banana jack ground power supply connection J13 USB USB cable connection High acts as Chip Select JMP2 CS Don t Care Low disables the I2C interface Hig...

Page 6: ...C Mode Settings Ref Des Symbol I2C Mode Pin Settings JMP8 I2C_A0_EQA1 Low JMP6 I2C_A1_EQB1 Low JMP3 I2C_A2_EQC1 Low JMP5 PDZ High normal operation Low powers down the device inputs off and outputs disabled resets the I2C JMP1 I2C_SEL Configures the device in I2C or GPIO mode of operation High enables I2C mode 7 GPIO Mode Although it is recommended to use the EVM in I2C mode so that the user has fu...

Page 7: ...he same data on line side Port C to be output on both fabric side ports JMP7 DIAG Port A B Low normal operation LN_EN_0 Default setting lane 0 of ports A B C are disabled LN_EN_1 Default setting lane 1 of ports A B C are disabled High enables lane 2 of ports A B C JMP26 LN_EN_2 Low disables lane 0 of ports A B C LN_EN_3 Default setting lane 3 of ports A B C are disabled DIS_AGC_A Default setting A...

Page 8: ...matics www ti com 8 Schematics Figure 3 SN65LVCP114 EVM Schematic Port A 8 SN65LVCP114 Evaluation Module EVM SLLU160 December 2011 Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 9: ...www ti com Schematics Figure 4 SN65LVCP114 EVM Schematic Port B 9 SLLU160 December 2011 SN65LVCP114 Evaluation Module EVM Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 10: ...Schematics www ti com Figure 5 SN65LVCP114 EVM Schematic Port C 10 SN65LVCP114 Evaluation Module EVM SLLU160 December 2011 Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 11: ...www ti com Schematics Figure 6 SN65LVCP114 EVM Schematic Controls_1 11 SLLU160 December 2011 SN65LVCP114 Evaluation Module EVM Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 12: ...Schematics www ti com Figure 7 SN65LVCP114 EVM Schematic Controls_2 12 SN65LVCP114 Evaluation Module EVM SLLU160 December 2011 Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 13: ...www ti com Schematics Figure 8 SN65LVCP114 EVM Schematic Controls_3 13 SLLU160 December 2011 SN65LVCP114 Evaluation Module EVM Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 14: ...matics www ti com Figure 9 SN65LVCP114 EVM Schematic Power Distribution 14 SN65LVCP114 Evaluation Module EVM SLLU160 December 2011 Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 15: ...w ti com Schematics Figure 10 SN65LVCP114 EVM Schematic USB Interface 15 SLLU160 December 2011 SN65LVCP114 Evaluation Module EVM Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 16: ...ount SMA CON_02K243 40M 32K243 40ML5 Rosenberger J13 USB B Type B Type USB B S F B TH Samtec P1 P2 Banana Plug Metal 4 mm 108 0740 001 Emerson Network Power Q1 Q2 NPN SOT23 MMBT4401 Fairchild Semiconductor R1 R4 R6 R8 R10 R15 R18 R19 R23 R27 R28 R32 R36 4 99 KΩ 0402 RES RG1005P 4991 B T5 Susumu Co Ltd R37 R41 R51 R58 R65 R66 R71 R88 R90 R99 R104 R9 1 2 KΩ 0402 RES ERJ XGNJ122Y Panasonic ECG R57 R5...

Page 17: ... SN65LVCP114ZJA Texas Instruments U2 DUAL NPN SOT 23 6 ZXTD09N50DE6TA Zetex Inc U4 Voltage Supervisor with Manual Reset SOT 23 5 TPS3125J18DBVR Texas Instruments U5 USB Microcontroller 64 LQFP TUSB3210PM Texas Instruments U6 Bidirectional Level Shifter 20 TSSOP TXB0108PWR Texas Instruments U7 512Kb EEPROM 8 SOIC 24LC512 I SM Microchip Technology U8 Single Output LDO 8 SON TPS73701DRB Texas Instrum...

Page 18: ...r Construction NOTE Always consult your board manufacturer for their process design requirements to ensure the desired impedance is achieved 18 SN65LVCP114 Evaluation Module EVM SLLU160 December 2011 Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 19: ...om Board Layout Figure 12 SN65LVCP114 Board Layout Top Signal Layer 1 of 6 19 SLLU160 December 2011 SN65LVCP114 Evaluation Module EVM Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 20: ...ut www ti com Figure 13 SN65LVCP114 Board Layout Internal Ground Layer 2 of 6 20 SN65LVCP114 Evaluation Module EVM SLLU160 December 2011 Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 21: ... Board Layout Figure 14 SN65LVCP114 Board Layout Internal Power Layer 3 of 6 21 SLLU160 December 2011 SN65LVCP114 Evaluation Module EVM Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 22: ...ut www ti com Figure 15 SN65LVCP114 Board Layout Internal Signal Layer 4 of 6 22 SN65LVCP114 Evaluation Module EVM SLLU160 December 2011 Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 23: ... Board Layout Figure 16 SN65LVCP114 Board Layout Internal Ground Layer 5 of 6 23 SLLU160 December 2011 SN65LVCP114 Evaluation Module EVM Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 24: ...out www ti com Figure 17 SN65LVCP114 Board Layout Bottom Signal Layer 6 of 6 24 SN65LVCP114 Evaluation Module EVM SLLU160 December 2011 Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 25: ...hows the different shunt settings of the 3 and 4 pin jumpers on the EVM Appendix B Typical Evaluation Setups Figure 18 Receive Side Use Case 25 SLLU160 December 2011 Jumper Shunt Settings Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 26: ...www ti com Figure 19 Transmit Side Use Case Figure 20 Combined Bus Extension Use Case 26 Typical Evaluation Setups SLLU160 December 2011 Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 27: ...ency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC or ICES 003 rules which are designed to provide reasonable protection against radio frequency interference Operation of the equipment may cause interference with radio communications in which case the user at his own expense will be required to take whatever measures may be required t...

Page 28: ... its gain should be so chosen that the equivalent isotropically radiated power e i r p is not more than that necessary for successful communication This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated Antenna types not included in this l...

Page 29: ...er you obtained the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect to this product Also please do not transfer this product unless you give the same notice above to the transferee Please note that if you could not follow the instructions above you will be subject to penalties of Radio Law of Japan Texas Instruments Japan Limited address 24 1 Nishi Shi...

Page 30: ... property damage personal injury or death If there are questions concerning these ratings please contact a TI field representative prior to connecting interface electronics including input power and intended loads Any loads applied outside of the specified output range may result in unintended and or inaccurate operation and or possible permanent damage to the EVM and or interface electronics Plea...

Page 31: ...regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures monitor failures and their consequence...

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