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SN65HVD257 EVM Setup and Operation for Redundant (Parallel Networks)

3.4

Using Customer Installable IO Options for Current Limiting, Pull up or down, Noise
Filtering

The EVM has footprints on the PCB for the installation of various filtering and protection options to adapt
the EVM to match CAN network topology requirements if the EVM is being used as a CAN node.

Each digital input or output pin has footprints to allow for series current limiting resistors (default populated
with 0

Ω

), pull up or down resistors depending on pin use and a capacitor to GND which, configured with

the serial resistor, implements RC filters (for noisy environments). The table below lists these features for
each of the digital input and output pins of the EVM. Replace or populate the RC components as
necessary for the application. The RC output filter pads for may be reused as a resistor divider network to
level shift the outputs down to 3.3V levels. The SN65HVD257 already has 3.3V compatible inputs on TXD
and S pins.

Table 5. EVM Digital IO Configuration

Signal

Jumper

Pull Up or

Series R

C to GND

Description

Pull

Down

Description

Type

Pull Up

Down

TXD U1

Input

NA

NA

R8 (R4/R10)

NA

NA

TXD input from JMP1 to TXD U1

R32

TXD U2

Input

NA

NA

NA

NA

TXD input from JMP1 to TXD U2

(R28/R34)

R44 PD

RXD U1 output to AND Gate for

RXD U1

Output

NA

NA

R17

C10

(10k)

combined RXD redundant output

R43 PD

RXD U1 output to AND Gate for

RXD U2

Output

NA

NA

R17

C16

(10k)

combined RXD redundant output

RXDprime is the combined RXD output
from the parallel CAN buses via AND

RXDprime

Output

NA

NA

R20

NA

C15

gate U2 which is routed to JMP1 as
RXD

R3

S (Mode) pin input from JMP1 or PU or

S U1

Input

R1 (JMP2)

R2

NA

C1

(JMP2)

PD to S U1

R27

S (Mode) pin input from JMP1 or PU or

S U2

Input

R25 (JMP2)

R26

NA

C21

(JMP2)

PD to S U2

FAULT3 is the combined RXD output
from the parallel CAN buses via XOR

FLT3

Output

NA

NA

R47 (3.3k)

NA

C28 (1nF)

gate U6 with the RC filter populated
which is routed to JMP1 as FLT3.

3.5

Using customer installable IO options for 3.3V IO

The EVM may be configured to have a 3.3V level output through the repurposing of the RC output filter
pads. These RC pads may be reused as a resistor divider network to level shift the outputs down to 3.3V
levels. The SN65HVD257 already has 3.3V compatible inputs on the TXD and S pins.

Table 6

shows

some examples. For use in applications, calculations must be made to ensure the resistor divider network
chosen adheres to the application requirement. Considerations should include: current biasing in the
resistor network (loading, power), ensuring that the V

OH

and V

OL

of the divider will meet the V

IH

and V

IL

input threshold levels of the host processor, and that the output of the resistor divider will be below the
absolute maximum rating of the host processor at the absolute maximum rating of the transceiver (or the
worst case corner the application will provide).

Table 6. EVM Digital IO Configuration

Output

R1 Pad and Value

R2 Pad and Value

Description

RXDprime

R20 = 3.9 k

Ω

C15 = 6.8 k

Ω

C15 pad is repurposed as R2.

FLT1

R15 = 0

Ω

C6 = 8.2 k

Ω

R1 is the pull up R16. C6 pad is repurposed as R2.

R16 = 4.7k

Ω

FLT2

"R39 = 0

Ω

C26 = 8.2 k

Ω

R1 is the pull up R 40. C26 pad is repurposed as R2.

R40 = 4.7k

Ω

FLT3

R47 = 3.9 k

Ω

C28 = 1nF and 6.8 k

Ω

C28 pad is repurposed as R2 and filter C (stacked
components).

11

SLLU172 – August 2012

SN65HVD257 CAN EVM: Functional Safety and Redundant CAN Network

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Copyright © 2012, Texas Instruments Incorporated

Summary of Contents for SN65HVD257

Page 1: ...d Filtering Configuration 10 3 4 Using Customer Installable IO Options for Current Limiting Pull up or down Noise Filtering 11 3 5 Using customer installable IO options for 3 3V IO 11 4 SN65HVD257 EVM...

Page 2: ...odes normal mode and silent mode selected on pin 8 The FAULT pin indicates TXD dominant time out RXD dominant time out thermal shut down and under voltage faults Figure 1 SN65HVD257 Basic Block Diagra...

Page 3: ...combine the RXD outputs of both branches During dominant bits low were the branches do not match the XOR the circuit outputs a logic high A small RC filter on the output eliminates false outputs due t...

Page 4: ...such as GND VCC TXD RXD CANH CANL S FAULT The EVM supports many options for CAN bus configuration It is pre configured with two 120 resistors that may be connected on the bus via jumpers a single resi...

Page 5: ...5 GND 1 TP8 RXD 1 TP1 GND 1 C17 DNI U1 SN65HVD257 TXD 1 GND 2 Vcc 3 RXD 4 FLT 5 CANL 6 CANH 7 S 8 C13 1uF R10 DNI R17 0 U5 SN65HVD257 TXD 1 GND 2 Vcc 3 RXD 4 FLT 5 CANL 6 CANH 7 S 8 R19 330 C1 DNI TP7...

Page 6: ...60 load for CAN transceiver parametric measurement JMP10 4 pin header Connection for access to transceiver 2 CAN bus output CANH2 CANL2 GND GND Connect 120 CAN termination to the bus Used in combinat...

Page 7: ...XDprime RXD Receive Data 7 GND GND 8 VCC Pin 3 of Transceiver VCC 9 S2 Pin 5 of Transceiver 2 Used for Mode control 10 FLT2 Pin 8 of Transceiver 2 Indicates fault with transceiver 2 11 GND GND 12 FLT3...

Page 8: ...MP1 and TP10 This output indicates a RXD DTO TXD DTO Thermal Shut Down or undervoltage fault with transceiver 1 3 1 7 FLT 2 FAULT pin 5 transceiver 2 JMP1 TP23 Pin 5 of transceiver 2 is the fault outp...

Page 9: ...y the split capacitance is in the range of 4 7nF to 100nF Keep in mind that this is the common mode filter frequency not a differential filter that will impact the differential CAN signal directly Tab...

Page 10: ...us filter environment Filter caps may be used in combination with L1 CM choke To add extra protection for system level transients and ESD protection use the D1 and D2 Transient Protection Transient ES...

Page 11: ...ode pin input from JMP1 or PU or S U1 Input R1 JMP2 R2 NA C1 JMP2 PD to S U1 R27 S Mode pin input from JMP1 or PU or S U2 Input R25 JMP2 R26 NA C21 JMP2 PD to S U2 FAULT3 is the combined RXD output fr...

Page 12: ...r 1 JMP3 may be used to route these signals to an external host processor or test system Make sure that the MODE JMP2 jumper settings are not conflicting with signals to JMP3 JMP2 transceiver 1 config...

Page 13: ...nsceiver 2 Ensure JMP7 and JMP8 are not configured to conflict if TP19 is used as the input connection 4 2 4 FLT2 Output JMP7 TP23 Pin 5 of transceiver 2 is the fault output of the transceiver This ou...

Page 14: ...2 JMP5 JMP10 Header 1x4 HDR_THVT_1X4_100 ANY ACT45B or B82789 series 17 2 L1 L2 DNI TDK EPCOS CM choke 18 4 R1 R16 R25 R40 4 7k 805 ANY R2 R3 R8 R15 R17 R20 R21 R26 19 11 0 805 ANY R27 R32 R39 20 4 R3...

Page 15: ...o handling the product This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI a...

Page 16: ...egulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided...

Page 17: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments SN65HVD257EVM...

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