Texas Instruments SN65DSI8 Series, User'S Manual And Implementation Manual, Page: 8 / 17

LEAVE
UNCONNECTED
FOR NORMAL
OPERATION
ADDR = 1, Slave Addr = 0x2D
ADDR = 0, Slave Addr = 0x2C
Reset(EN) can be implemented with passive
components as shown or active circuitry. In
case of using passive components, the
values of the RC circuitry need to be
adjusted to make sure the low to high
transition occurs after the Vcc supply has
reached the minimum recommended
operating voltage. For this reason, it is
recommended to USE ACTIVE CIRCUITRY for
better control of the RESET/EN timing.
DSI INPUT LVDS OUTPUT
Optional ref CLK
for LVDS Pixel
CLK
25MHz-154MHz
1uF is min value.
The number of capacitors and their values may vary depending on the system implementation
R5: Terminate to GND
with a pull-down
resistor if unused
0.2uF
SN65DSI85
Reset Implementation
Note: Bypass caps and FB
should be placed near U1
SN65DSI85.
*IMPORTANT*
If REFCLK is to be
used, the CLK trace
length between the
REFCLK terminal and
the source of the REF
CLK(OSC or Xtal)
should be kept as short
as possble.
IRQ SilkScreen:
SilkScreen:
IRQ
SilkScreen: REF_CLK
DSI_A0P
DSI_A0N
DSI_A1N
DSI_A2P
DSI_A2N
DSI_A3P
DSI_A3N
DSI_ACLKP
DSI_ACLKN
DSI_A1P
FlatChA_Y0N
FlatChA_Y0P
FlatChA_Y1P
FlatChA_Y2N
FlatChA_Y2P
FlatChA_Y3N
FlatChA_Y3P
FlatChA_YCLKN
FlatChA_YCLKP
FlatChA_Y1N
ADDR
Test1
Test2
BOARD_RESETN
IRQ
DSI_B0P
DSI_B0N
DSI_B1N
DSI_B2P
DSI_B2N
DSI_B3P
DSI_B3N
DSI_BCLKP
DSI_BCLKN
DSI_B1P
FlatChB_Y0P
FlatChB_Y0N
FlatChB_Y1P
FlatChB_Y2N
FlatChB_Y2P
FlatChB_Y3N
FlatChB_Y3P
FlatChB_YCLKN
FlatChB_YCLKP
FlatChB_Y1N
I2C_SCL
I2C_SDA
BOARD_RESETN
Vcore_1P1_Out
IRQ_LED
IRQ
IRQ_OUT
REFCLK
EXT_REFCLK
Vcc_1P8V
BOARD_1P8V
BOARD_1P8V BOARD_1P8V
Vcc_1P8V
BOARD_1P8V BOARD_3P3V
DSI_A0P pg3
DSI_A0N pg3
DSI_A1P pg3
DSI_A1N pg3
DSI_A2P pg3
DSI_A2N pg3
DSI_A3P pg3
DSI_A3N pg3
DSI_ACLKP pg3
DSI_ACLKN pg3
DSI_B0P pg3
DSI_B0N pg3
DSI_B1P pg3
DSI_B1N pg3
DSI_B2P pg3
DSI_B2N pg3
DSI_B3P pg3
DSI_B3N pg3
DSI_BCLKP pg3
DSI_BCLKN pg3
I2C_SCL pg3,4
I2C_SDA pg3,4
LVDS_RefCLK pg4
FlatChA_Y0N pg3
FlatChA_Y0P pg3
FlatChA_Y1N pg3
FlatChA_Y1P pg3
FlatChA_Y2N pg3
FlatChA_Y2P pg3
FlatChA_Y3N pg3
FlatChA_Y3P pg3
FlatChA_CLKN pg3
FlatChA_CLKP pg3
FlatChB_Y0N pg3
FlatChB_Y0P pg3
FlatChB_Y1N pg3
FlatChB_Y1P pg3
FlatChB_Y2N pg3
FlatChB_Y2P pg3
FlatChB_Y3N pg3
FlatChB_Y3P pg3
FlatChB_CLKN pg3
FlatChB_CLKP pg3
BOARD_RESETN pg2,3,4
BOARD_RESETN pg2,3,4
ADDR pg4
IRQ pg3
Test1 pg4
Test2 pg4
R4
4.7K R32
DNI
J17
HDR2X1 M .1
1
2
C11
1uF
C1
10uF
R1
0
C5
10000pF
TP1
T POINT S
C2
1.0uF
R5
10K
C3
10000pF
D1
LED Orange 0805
C7
10000pF
U1
SN65DSI85
DA0P
H3
DA1P
H4
DA2P
H6
DA3P
H7
DACP
H5
DB0P
C2
DB1P
D2
DB2P
F2
DB3P
G2
DBCP
E2
DA0N
J3
DA1N
J4
DA2N
J6
DA3N
J7
DACN
J5
DB0N
C1
DB1N
D1
DB2N
F1
DB3N
G1
DBCN
E1
A_Y0N
C9
A_Y1N
D9
A_Y2N
E9
A_Y3N
G9
A_CLKN
F9
A_Y0P
C8
A_Y1P
D8
A_Y2P
E8
A_Y3P
G8
A_CLKP
F8
B_Y0N
A3
B_Y0P
B3
B_Y1N
A4
B_Y1P
B4
B_Y2N
A5
B_Y2P
B5
B_Y3N
A7
B_Y3P
B7
B_CLKN
A6
B_CLKP
B6
ADDR
A1
SDA
J1
SCL
H1
EN
B1
TEST2
B2
TEST1
H8
REFCLK
H2
IRQ
J9
V
c
c
A
9
V
c
c
B
8
V
c
c
D6
V
c
c
E
6
V
c
c
F6
V
c
c
J
2
V
c
c
E
5
GN
D
B
9
GN
D
A
8
GN
D
A
2
GN
D
D5
GN
D
E
4
GN
D
F4
GN
D
F5
GN
D
H9
V
cor
e
J
8
C6
0.1uF
R2
348
LP3
LP2 LP1
FB1
220 @ 100MHZ
C4
0.1uF
C9
0.1uF
C8
0.1uF
R33 0
R3
4.7K
C10
DNI
U2
SN74LVC1G07DCK
2
3
5
4
1
Copyright © 2016, Texas Instruments Incorporated
EVM Schematics
www.ti.com
8 SLLU221 – October 2016
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Copyright © 2016, Texas Instruments Incorporated
SN65DSI83, SN65DSI84, and SN65DSI85 EVM User’s Manual and
Implementation Guide
5 EVM Schematics
Figure 4 through Figure 7 illustrate the EVM schematics.
Figure 4. SN65DSI8X Schematic 1