Applying an Input
2-3
Setup and Equipment Required
Figure 2-2. EVM Power Connections for SN65LVDS100 Evaluation
Pattern
Generator
Oscilloscope
EVM
Power Supply 1
+
-
Power Supply 2
+
-
VCC
EVM
GND
DUT
GND
1.22V
3.3V
Matched
Cables
SMA to SMA
Matched
Cables
SMA to SMA
J2
J7
J6
J5
J4
J3
J1
100
Ω
50
Ω
50
Ω
Warning
Power jacks J1, J2, and J3 are not insulated on the backside of the
EVM. Place on a nonconductive surface.
2.2
Applying an Input
LVDS inputs should be applied to SMA connectors J4 and J5, while keeping
R1 installed. The EVM comes with a 100-
Ω
termination resistor (R1) installed
across the differential inputs. This 100-
Ω
resistor represents an LVDS
termination.
When using a general-purpose signal generator with 50-
Ω
output impedance,
make sure that the signal levels are between 0 V to 4 V with respect to J3. A
signal generator such as the Advantest D3186 can simulate LVDS, LVPECL,
or CML inputs.
When using LVPECL or CML drivers for the input signal, termination external
to the EVM must be provided (see Figure 2-3). LVPECL drivers should be
terminated with 50-
Ω
pulldowns to V
T
, while CML drivers should be terminated
Summary of Contents for SLLU040A
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Page 26: ...Board Layer Patterns 3 6 Layer 3 VCC Split Plane INT2 Layer 4 GND Plane Bottom Side ...