23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PIXEL_n
0
0
0
0
0
0
0
0
R[7:3]
G[7:2]
B[7:3]
16-bit panel
24-bit panel
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PIXEL_n
B[0]
G[0]
R[0]
B[1]
G[1]
R[1]
B[2]
R[2]
B[7:3]
G[7:2]
R[7:3]
16-bit panel
24-bit panel
Usage Notes and Known Design Exceptions to Functional Specifications
3
Usage Notes and Known Design Exceptions to Functional Specifications
3.1
Usage Notes
This document contains Usage Notes. Usage Notes highlight and describe particular situations where the
device's behavior may not match presumed or documented behavior. This may include behaviors that
affect device performance or functional correctness. These notes may be incorporated into future
documentation updates for the device (such as the device-specific data manual), and the behaviors they
describe may or may not be altered in future device revisions.
3.1.1
LCD: Color Assignments of LCD_DATA Terminals
The blue and red color assignments to the LCD data pins are reversed when operating in RGB888
(24bpp) mode compared to RGB565 (16bpp) mode. In order to correctly display RGB888 data from the
SGX, or any source formatted as RGB in memory, it is necessary to connect the LCD panel as shown in
. Using the LCD Controller with this connection scheme limits the use of RGB565 mode. Any data
generated for the RGB565 mode requires the red and blue color data values be swapped in order to
display the correct color.
Figure 2. RGB888 Mode LCD Controller Output Pin Mapping (LCD_DATA[23:0])
When operating the LCD Controller in RGB565 mode the LCD panel should be connected as shown in
. Using the LCD Controller with this connection scheme limits the use of RGB888 mode. Any data
generated for the RGB888 mode requires the red and blue color data values be swapped in order to
display the correct color.
Figure 3. RGB565 Mode LCD Controller Output Pin Mapping (LCD_DATA[23:0])
3.1.2
DDR3: JEDEC Compliance for Maximum Self-Refresh Command Limit
When using DDR3 EMIF Self-Refresh, it is possible to violate the maximum refresh command requirement
specified in the JEDEC standard DDR3 SDRAM Specification (JESD79-3E, July 2010). This requirement
states that the DDR3 EMIF controller should issue no more than 16 refresh commands within any 15.6-
μ
s
interval.
To avoid this requirement violation, when using the DDR3 EMIF and Self-Refresh (setting LP_MODE =
0x2 field in the PMCR), the SR_TIM value in the PMCR must to be programmed to a value greater than or
equal to 0x9.
8
SPRZ360F – October 2011 – Revised November 2013
Sitara™ AM335x ARM
®
Cortex™-A8 Microprocessors (MPUs) (Silicon
Revision 2.1, 2.0, 1.0)
Copyright © 2011–2013, Texas Instruments Incorporated
