Texas Instruments SimpleLink MSP432P4 Series, Technical Reference Manual

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Functional Peripherals Registers
173 SLAU356I – March 2015 – Revised June 2019
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Cortex-M4F Peripherals
2.4.7 COREDEBUG Registers
Table 2-92 lists the memory-mapped registers for the COREDEBUG. All register offset addresses not
listed in Table 2-92 should be considered as reserved locations and the register contents should not be
modified.
Table 2-92. COREDEBUG Registers
Offset Acronym Register Name Type Reset Section
DF0h DHCSR Debug Halting Control and Status Register read-write 00000000h Section 2.4.7.1
DF4h DCRSR Deubg Core Register Selector Register write-only Undefined Section 2.4.7.2
DF8h DCRDR Debug Core Register Data Register read-write Undefined Section 2.4.7.3
DFCh DEMCR Debug Exception and Monitor Control Register read-write 00000000h Section 2.4.7.4