UART Registers
1649
SLAU723A – October 2017 – Revised October 2018
Copyright © 2017–2018, Texas Instruments Incorporated
Universal Asynchronous Receiver/Transmitter (UART)
26.5.11 UARTRIS Register (Offset = 0x3C) [reset = 0x0]
UART Raw Interrupt Status (UARTRIS)
The UARTRIS register is the raw interrupt status register. On a read, this register gives the current raw
status value of the corresponding interrupt. A write has no effect.
UARTRIS is shown in
and described in
Return to
Figure 26-14. UARTRIS Register
31
30
29
28
27
26
25
24
RESERVED
R-0x0
23
22
21
20
19
18
17
16
RESERVED
DMATXRIS
DMARXRIS
R-0x0
R-0x0
R-0x0
15
14
13
12
11
10
9
8
RESERVED
9BITRIS
EOTRIS
OERIS
BERIS
PERIS
R-0x0
R-0x0
R-0x0
R-0x0
R-0x0
R-0x0
7
6
5
4
3
2
1
0
FERIS
RTRIS
TXRIS
RXRIS
DSRRIS
DCDRIS
CTSRIS
RIRIS
R-0x0
R-0x0
R-0x0
R-0x0
R-0x0
R-0x0
R-0x0
R-0x0
Table 26-14. UARTRIS Register Field Descriptions
Bit
Field
Type
Reset
Description
31-18
RESERVED
R
0x0
17
DMATXRIS
R
0x0
Transmit DMA Raw Interrupt Status.
This bit is cleared by writing a 1 to the DMATXIC bit in the UARTICR
register.
0x0 = No interrupt
0x1 = The transmit DMA has completed.
16
DMARXRIS
R
0x0
Receive DMA Raw Interrupt Status.
This bit is cleared by writing a 1 to the DMARXIC bit in the UARTICR
register.
0x0 = No interrupt
0x1 = The receive DMA has completed.
15-13
RESERVED
R
0x0
12
9BITRIS
R
0x0
9-Bit Mode Raw Interrupt Status.
This bit is cleared by writing a 1 to the 9BITIC bit in the UARTICR
register.
0x0 = No interrupt
0x1 = A receive address match has occurred.
11
EOTRIS
R
0x0
End of Transmission Raw Interrupt Status.
This bit is cleared by writing a 1 to the EOTIC bit in the UARTICR
register.
0x0 = No interrupt
0x1 = The last bit of all transmitted data and flags has left the
serializer.
10
OERIS
R
0x0
UART Overrun Error Raw Interrupt Status.
This bit is cleared by writing a 1 to the OEIC bit in the UARTICR
register.
0x0 = No interrupt
0x1 = An overrun error has occurred.