
SCB Registers
156
SLAU723A – October 2017 – Revised October 2018
Copyright © 2017–2018, Texas Instruments Incorporated
Cortex-M4 Peripherals
2.5.7 CFGCTRL Register (Offset = 0xD14) [reset = 0x200]
Configuration and Control (CFGCTRL)
NOTE:
This register can only be accessed from privileged mode.
The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault and
faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero and unaligned
accesses; and access to the SWTRIG register by unprivileged software (see ).
CFGCTRL is shown in
and described in
.
Return to
Figure 2-19. CFGCTRL Register
31
30
29
28
27
26
25
24
RESERVED
R-0x0
23
22
21
20
19
18
17
16
RESERVED
R-0x0
15
14
13
12
11
10
9
8
RESERVED
STKALIGN
BFHFNMIGN
R-0x0
R/W-0x1
R/W-0x0
7
6
5
4
3
2
1
0
RESERVED
DIV0
UNALIGNED
RESERVED
MAINPEND
BASETHR
R-0x0
R/W-0x0
R/W-0x0
R-0x0
R/W-0x0
R/W-0x0
Table 2-32. CFGCTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
31-10
RESERVED
R
0x0
9
STKALIGN
R/W
0x1
Stack Alignment on Exception Entry
On exception entry, the processor uses bit 9 of the stacked PSR to
indicate the stack alignment. On return from the exception, it uses
this stacked bit to restore the correct stack alignment.
8
BFHFNMIGN
R/W
0x0
Ignore Bus Fault in NMI and Fault
This bit enables handlers with priority -1 or -2 to ignore data bus
faults caused by load and store instructions. The setting of this bit
applies to the hard fault, NMI, and FAULTMASK escalated handlers.
Set this bit only when the handler and its data are in absolutely safe
memory. The normal use of this bit is to probe system devices and
bridges to detect control path problems and fix them.
7-5
RESERVED
R
0x0
4
DIV0
R/W
0x0
Trap on Divide by 0
This bit enables faulting or halting when the processor executes an
SDIV or UDIV instruction with a divisor of 0.
3
UNALIGNED
R/W
0x0
Trap on Unaligned Access
Unaligned LDM, STM, LDRD, and STRD instructions always fault
regardless of whether UNALIGNED is set.
2
RESERVED
R
0x0
1
MAINPEND
R/W
0x0
Allow Main Interrupt Trigger
0
BASETHR
R/W
0x0
Thread State Control