
Memory Model
102
SLAU723A – October 2017 – Revised October 2018
Copyright © 2017–2018, Texas Instruments Incorporated
Cortex
®
-M4F Processor
required.
•
Vector table
If the program changes an entry in the vector table and then enables the corresponding exception, use
a DMB instruction between the operations. The DMB instruction ensures that if the exception is taken
immediately after being enabled, the processor uses the new exception vector.
•
Self-modifying code
If a program contains self-modifying code, use an ISB instruction immediately after the code
modification in the program. The ISB instruction ensures subsequent instruction execution uses the
updated program.
•
Memory map switching
If the system contains a memory map switching mechanism, use a DSB instruction after switching the
memory map in the program. The DSB instruction ensures subsequent instruction execution uses the
updated memory map.
•
Dynamic exception priority change
When an exception priority has to change when the exception is pending or active, use DSB
instructions after the change. The change then takes effect on completion of the DSB instruction.
Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require the use
of DMB instructions.
For more information on the memory barrier instructions, see the Cortex-M4 instruction set chapter in the
Arm Cortex-M4 Devices Generic User Guide
.
1.5.5 Bit-Banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-
band regions occupy the lowest 1MB of the SRAM and peripheral memory regions. Accesses to the 32-
MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in
. Accesses to the
32-MB peripheral alias region map to the 1-MB peripheral bit-band region, as shown in
. For the
specific address range of the bit-band regions, see
NOTE:
A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in the
SRAM or peripheral bit-band region.
A word access to a bit-band address results in a word access to the underlying memory, and
similarly for halfword and byte accesses. This allows bit-band accesses to match the access
requirements of the underlying peripheral.
Table 1-17. SRAM Memory Bit-Banding Regions
Address Range
Memory Region
Instruction and Data Accesses
Start
End
0x2000.0000
0x2006.FFFF
SRAM bit-band region
Direct accesses to this memory range behave as SRAM
accesses, but this region is also bit addressable through bit-
band alias.
0x2200.0000
0x2234.FFFF
SRAM bit-band alias
Data accesses to this region are remapped to bit-band region. A
write operation is performed as read-modify-write. Instruction
accesses are not remapped.
Table 1-18. Peripheral Memory Bit-Banding Regions
Address Range
Memory Region
Instruction and Data Accesses
Start
End
0x4000.0000
0x400F.FFFF
Peripheral bit-band region
Direct accesses to this memory range behave as peripheral
memory accesses, but this region is also bit addressable
through bit-band alias.