Timer data in
HET[x]
Loop
Resolution
Clock
Timer data out
HETDIR
HETDIN
HETDOUT
HETDSET
HETDCLR
High Resolution
Structure
N2HET Functional Description
804
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
High-End Timer (N2HET) Module
As an example of where the automatic read clear feature is useful, consider the PCNT instruction. If this
instruction is configured for automatic read clear, then when the host CPU reads the PCNT data field it will
be cleared automatically. The host CPU can then poll the PCNT data field again, and as long as the field
returns a value of zero the host CPU program knows a new capture event has not occurred. If the data
field were not cleared, it would be impossible for the host CPU to determine whether the data field holds
data from the previous capture event, or if it happens to be data from a new capture event with the same
value.
20.2.4.4 Emulation Mode
Emulation mode, used by the software debugger, is specified in the global configuration register. When
the host CPU debugger hits a breakpoint, the CPU sends a suspend signal to the modules. Two modes of
operation are provided: suspend and ignore suspend.
•
Suspend
When a suspend is issued, the timer operation stops at the end of the current timer instruction. However,
the CPU accesses to the timer RAM or control registers are freely executed.
•
Ignore suspend
The timer RAM ignores the suspend signal and operates real time as normal.
20.2.4.5 Power-Down
After setting the turn-off bit in the Global Configuration Register (HETGCR), it is required to delay until the
end of the timer program loop before putting the N2HET in power-down mode. This can be done by
waiting until the N2HET Current Address (HETADDR) becomes zero, before disabling the N2HET clock
source in the device’s Global Clock Module (GCM).
20.2.5 I/O Control
The N2HET has up to 32 pins. Refer to device specific data sheets for information concerning the number
of N2HETIO available. All of the N2HET pins available are programmable as either inputs or outputs.
These 32 I/Os have an identical structure connected to pins HET[31] to HET[0]. See
for an
illustration of the I/O control. In addition all 32 I/Os have a special HR structure based on the HR clock.
This structure allows any N2HET instruction to use any of these I/Os with an accuracy of either loop
resolution or high resolution accuracy.
Figure 20-8. I/O Control
Pins N2HET [31] to N2HET [0] can be used by the CPU as general-purpose inputs or outputs using the
N2HET Data Input Register (HETDIN) for reading and N2HET Data Output Register (HETDOUT), N2HET
Data Set Register (HETDSET) or N2HET Data Clear Register (HETDCLR) for writing, depending on the
type of action to perform. The N2HET pins used as general-purpose inputs are sampled on each VCLK2
period.
