Texas Instruments RM48 series, Technical Reference Manual

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EMIF Registers
657 SPNU503C – March 2018
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External Memory Interface (EMIF)
17.3.8 EMIF Interrupt Raw Register (INTRAW)
The EMIF interrupt raw register (INTRAW) is used to monitor and clear the EMIF’s hardware-generated
Asynchronous Timeout Interrupt. The AT bit in this register will be set when an Asynchronous Timeout
occurs regardless of the status of the EMIF interrupt mask set register (INTMSKSET) and EMIF interrupt
mask clear register (INTMSKCLR). Writing a 1 to this bit will clear it. The EMIF on some devices does not
have the EMIF_nWAIT pin; therefore, these registers and fields are reserved on those devices. The
INTRAW is shown in
Figure 17-22 and described in Table 17-32 .
Figure 17-22. EMIF Interrupt Raw Register (INTRAW) [offset = 40h]
31 8
Reserved
R-0
7 3 2 1 0
Reserved WR LT AT
R-0 R/W1C-0 R/W1C-0 R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); - n = value after reset
Table 17-32. EMIF Interrupt Raw Register (INTRAW) Field Descriptions
Bit Field Value Description
31-3 Reserved 0 Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
2 WR Wait Rise. This bit is set to 1 by hardware to indicate that a rising edge on the EMIF_nWAIT pin has
occurred.
0 Indicates that a rising edge has not occurred on the EMIF_nWAIT pin. Writing a 0 has no effect.
1 Indicates that a rising edge has occurred on the EMIF_nWAIT pin. Writing a 1 will clear this bit and the
WR_MASKED bit in the EMIF interrupt masked register (INTMSK).
1 LT Line Trap. Set to 1 by hardware to indicate illegal memory access type or invalid cache line size.
0 Writing a 0 has no effect.
1 Indicates that a line trap has occurred. Writing a 1 will clear this bit as well as the LT_MASKED bit in
the EMIF interrupt masked register (INTMSK).
0 AT Asynchronous Timeout. This bit is set to 1 by hardware to indicate that during an extended
asynchronous memory access cycle, the EMIF_nWAIT pin did not go inactive within the number of
cycles defined by the MAX_EXT_WAIT field in the asynchronous wait cycle configuration register
(AWCC).
0 Indicates that an Asynchronous Timeout has not occurred. Writing a 0 has no effect.
1 Indicates that an Asynchronous Timeout has occurred. Writing a 1 will clear this bit as well as the
AT_MASKED bit in the EMIF interrupt masked register (INTMSK).