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VIM Control Registers
529
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Vectored Interrupt Manager (VIM) Module
15.8.5 VIM Offset Vector Registers
The VIM offset register provides the user with the numerical index value that represents the pending
interrupt with the highest precedence. The register IRQINDEX holds the index to the highest priority IRQ
interrupt; the register FIQINDEX holds the index to the highest priority FIQ interrupt. The index can be
used to locate the interrupt routine in a dispatch table, as shown in
Table 15-6. Interrupt Dispatch
IRQINDEX / FIQINDEX Register Bit Field
Highest Priority Pending Interrupt Enabled
0x00
No interrupt
0x01
Channel 0
:
:
0x5F
Channel 94
0x60
Channel 95
NOTE:
Channel 95 has no dedicated interrupt vector table entry. Therefore, Channel 95 shall NOT
be used in application.
The VIM offset registers are read only. They are updated continuously by the VIM. When an interrupt is
serviced, the offset vectors show the index for the next highest pending interrupt or 0x0 if no interrupt is
pending.