Texas Instruments RM48 series, Technical Reference Manual

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System and Peripheral Control Registers
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158 SPNU503C – March 2018
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Architecture
2.5.1.34 General Purpose Register (GPREG1)
This register is shown in Figure 2-39 and described in Table 2-53 . For information on filtering the RFSLIP,
see Section 2.5.2.5 .
Figure 2-39. General Purpose Register (GPREG1) [offset = A0h]
31 30 26 25 20 19 16
EMIF_FUNC Reserved PLL1_FBSLIP_FILTER_COUNT PLL1_FBSLIP_FILTER_KEY
R/WP-0 R-0 R/WP-0 R/WP-5h
15 0
OUTPUT_BUFFER_LOW_EMI_MODE
R/WP-FFFFh
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; - n = value after reset
Table 2-53. General Purpose Register (GPREG1) Field Descriptions
Bit Field Value Description
31 EMIF_FUNC 0 Enable EMIF functions to be output. EMIF_ADDR[0], EMIF_ADDR[1],
EMIF_ADDR[6], EMIF_ADDR[7], EMIF_ADDR[8], EMIF_BA[1],
EMIF_nCS[0], and EMIF_nCS[3] are multiplexed with N2HET2
signals. By default, these terminals are tri-stated and pulled down.
Any application that requires the EMIF functionality must set the
EMIF_FUNC bit. This allows these 8 EMIF module outputs to be
driven on to the assigned balls.
30-26 Reserved 0 Reads return 0. Writes have no effect.
25-20 PLL1_FBSLIP_FILTER_ COUNT FBSLIP down counter programmed value.
Configures the system response when a FBSLIP is indicated by the
PLL macro. When PLL1_FBSLIP_FILTER_KEY is not Ah, the down
counter counts from the programmed value on every LPO high-
frequency clock once PLL macro indicates FBSLIP. When the count
reaches 0, if the synchronized FBSLIP signal is still high, an FBSLIP
condition is indicated to the system module and is captured in the
global status register. When the FBSLIP signal from the PLL macro is
de-asserted before the count reaches 0, the counter is reloaded with
the programmed value.
On reset, counter value is 0. Counter must be programmed to a non-
zero value and enabled for the filtering to be enabled.
0 Filtering is disabled.
1h Filtering is enabled. Every slip is recognized.
2h Filtering is enabled. The slip must be at least 2 HF LPO cycles wide
in order to be recognized as a slip.
:
3Fh Filtering is enabled. The slip must be at least 63 HF LPO cycles wide
in order to be recognized as a slip.
19-16 PLL1_FBSLIP_FILTER_ KEY Enable the FBSLIP filtering.
5h On reset, the FBSLIP filter is disabled and the FBSLIP passes
through.
Fh This is an unsupported value. You should avoid writing this value to
this bit field.
All other
values
FBSLIP filtering is enabled. Recommended to program Ah in this bit
field. Enabling of the FBSLIP occurs when the KEY is programmed
and a non-zero value is present in the COUNT field.