DCAN Control Registers
1083
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Controller Area Network (DCAN) Module
NOTE:
The Bus-Off recovery sequence (see CAN specification) cannot be shortened by setting or
resetting Init bit. If the module goes Bus-Off, it will automatically set the Init bit and stop all
bus activities.
When the Init bit is cleared by the application again, the module will then wait for 129
occurrences of Bus Idle (129 × 11 consecutive recessive bits) before resuming normal
operation. At the end of the Bus-Off recovery sequence, the error counters will be reset.
After the Init bit is reset, each time when a sequence of 11 recessive bits is monitored, a Bit0
error code is written to the Error and Status Register, enabling the CPU to check whether the
CAN bus is stuck at dominant or continuously disturbed, and to monitor the proceeding of the
Bus-Off recovery sequence.
23.17.2 Error and Status Register (DCAN ES)
Figure 23-20. Error and Status Register (DCAN ES) [offset = 04h]
31
16
Reserved
R-0
15
11
10
9
8
Reserved
PDA
WakeUpPnd
PER
R-0
R-0
R/C-0
R/C-0
7
6
5
4
3
2
0
BOff
EWarn
EPass
RxOK
TxOK
LEC
R-0
R-0
R-0
R/C-0
R/C-0
R/S-7h
LEGEND: R = Read only; C = Clear; S = Set; -
n
= value after reset
Table 23-8. Error and Status Register Field Descriptions
Bit
Field
Value
Description
31-11
Reserved
0
These bits are always read as 0. Writes have no effect.
10
PDA
Local power-down mode acknowledge
0
DCAN is not in local power-down mode.
1
Application request for setting DCAN to local power-down mode was successful. DCAN is in local
power-down mode.
9
WakeUpPnd
Wake Up Pending
This bit can be used by the CPU to identify the DCAN as the source to wake up the system.
0
No Wake Up is requested by DCAN.
1
DCAN has initiated a wake up of the system due to dominant CAN bus while module power down.
This bit will be reset if Error and Status Register is read.
8
PER
Parity Error Detected
0
No parity error has been detected since last read access.
1
The parity check mechanism has detected a parity error in the Message RAM. This bit will be reset
if Error and Status Register is read.
7
BOff
Bus-Off State
0
The CAN module is not Bus-Off state.
1
The CAN module is in Bus-Off state.
6
EWarn
Warning State
0
Both error counters are below the error warning limit of 96.
1
At least one of the error counters has reached the error warning limit of 96.
