Texas Instruments RM46L852, Manual

Page: 47 / 173

PRODUCTPREVIEW
Address Waitstates
Data Waitstates
RAM
Address Waitstates
Data Waitstates
Flash
0MHz
0MHz
0MHz
0MHz
110MHz
0 1 3
0
0
0
165MHz
2
120MHz
1
220MHz
220MHz
220MHz
220MHz 55MHz
RM46L852
www.ti.com SPNS185 – SEPTEMBER 2012
3.3 Switching Characteristics over Recommended Operating Conditions for Clock Domains
Table 3-1. Clock Domain Timing Specifications
Parameter Description Conditions Max Unit
f
GCLK
GCLK - CPU clock frequency f
HCLK
MHz
f
HCLK
HCLK - System clock frequency Pipeline mode 220 MHz
enabled
Pipeline mode 55 MHz
disabled
f
VCLK
VCLK - Primary peripheral clock frequency 110 MHz
f
VCLK2
VCLK2 - Secondary peripheral clock 110 MHz
frequency
f
VCLK3
VCLK3 - Secondary peripheral clock 110 MHz
frequency
f
VCLKA1
VCLKA1 - Primary asynchronous 110 MHz
peripheral clock frequency
f
VCLKA2
VCLKA2 - Secondary asynchronous 110 MHz
peripheral clock frequency
f
VCLKA3
VCLKA3 - Primary asynchronous 110 MHz
peripheral clock frequency
f
VCLKA4
VCLKA4 - Secondary asynchronous 110 MHz
peripheral clock frequency
f
RTICLK
RTICLK - clock frequency f
VCLK
MHz
3.4 Wait States Required
Figure 3-1. Wait States Scheme
As shown in the figure above, the TCM RAM can support program and data fetches at full CPU speed without
any address or data wait states required.
The TCM flash can support zero address and data wait states up to a CPU speed of 55MHz in non-pipelined
mode.
The flash wrapper defaults to non-pipelined mode with zero address wait state and one random-read data wait
state.
Copyright © 2012, Texas Instruments Incorporated
Device Operating Conditions 47
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