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Texas Instruments PGA5807A User Manual Download Page 24

Testing the PGA5807A EVM

www.ti.com

4.2

Capturing a RAMP Test Pattern

As described in

Section 3.1

, the LVDS interface between the PGA5807A EVM and the TSW1400 EVM

can be tested using the default EVM configuration and minimal bench equipment.

1. Within the

ADS5296

tab, press on the sub-tab labeled

Test Pattern

and select

RAMP PATTERN

within

the

TEST_PATT

menu as shown in

Figure 32

.

Figure 32. ADS5296A Setup for RAMP Test

24

PGA5807A, 8-Channel, High-Bandwidth, Analog Front-End Evaluation

SLAU538 – October 2013

Module

Submit Documentation Feedback

Copyright © 2013, Texas Instruments Incorporated

Summary of Contents for PGA5807A

Page 1: ... 3 PGA5807A EVM 0 Ω Jumper Configuration 18 4 Testing the PGA5807A EVM 19 4 1 TSW1400 and PGA5807 GUI Setup 19 4 2 Capturing a RAMP Test Pattern 24 4 3 Capturing Sinusoidal Input for ADS5296A Only 28 4 4 SNR THD and Gain Test for PGA5807A ADS5296A 32 5 PGA5807 GUI in Detail 37 5 1 Read Me First tab 38 5 2 PGA5807 tab 39 5 3 ADS5296 Tab 43 6 PGA5807A EVM Schematics 44 7 PGA5807A EVM Bill of Materia...

Page 2: ...ADS5296A Only Sinusoidal Capture 1 31 43 PGA5807A ADS5296A Gain Test Setup 32 44 PGA5807 GUI Setup for PGA5807A ADS5296A 1 33 45 PGA5807A ADS5296A SNR THD Gain Test Capture 1 33 46 PGA5807 GUI Setup for PGA5807A ADS5296A SNR THD Gain Test 2 34 47 PGA5807A ADS5296A Gain Test Capture 2 35 48 PGA5807 GUI Setup for PGA5807A ADS5296A Gain Test 3 35 49 PGA5807A ADS5296A Gain Test Capture 3 36 50 PGA5807...

Page 3: ...ic Sh 13 of 16 PGA_CH8 ADC_CH4 56 76 PGA5807A Schematic Sh 14 of 16 FTDI Serial Interface 57 77 PGA5807A Schematic Sh 15 of 16 ADS5296A External Reference 58 78 PGA5807A Schematic Sh 16 of 16 Power Supply 59 79 PGA5807A EVM Top Layer Assembly Drawing Top View 63 80 PGA5807A EVM Bottom Layer Assembly Drawing Bottom View 64 81 PGA5807A EVM Top Side 65 82 PGA5807A EVM Ground Plane 1 66 83 PGA5807A EV...

Page 4: ...07A plus ADS5296A For more information pertaining to the ADS5296A device see http www ti com product ads5296a TSW1400 EVM The high speed LVDS deserializer board is required for capturing data from the PGA5807A EVM and its analysis using the TSW1400 graphical user interface GUI called High Speed Data Converter Pro HSDCpro For more information pertaining to the TSW1400 EVM see http focus ti com docs...

Page 5: ...ation procedures 2 GUI Software Installation The PGA5807A EVM and the TSW1400 EVM both require software installations The following two sections explain where to find and how to install the software properly Ensure that no USB connections are made to the EVMs until after the installations are complete 2 1 TSW1400 EVM GUI Installation High Speed Data Converter Pro HSDCpro From the Texas Instruments...

Page 6: ...re 3 Figure 3 HSDCpro Install b Read the License Agreement from Texas Instruments and select I accept the License Agreement and press the Next button as shown in Figure 4 Figure 4 HSDCpro Install c 6 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation SLAU538 October 2013 Module Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 7: ...nse Agreement and press the Next button as in Figure 5 Figure 5 HSDCpro Install d Press the Next button as shown in Figure 6 Figure 6 HSDCpro Install e 7 SLAU538 October 2013 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation Module Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 8: ...gress Figure 7 HSDCpro Install f The window shown in Figure 8 appears indicating Installation Complete Press the Next button Figure 8 HSDCpro Install g 8 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation SLAU538 October 2013 Module Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 9: ...t might be requested depending on whether or not the PC already has the National Instruments MCR installer If requested hit the Restart button to complete the installation Figure 10 HSDCpro Install i 9 SLAU538 October 2013 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation Module Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 10: ... Unzip the folder and run the Setup bat file as administrator by right clicking on it and selecting Run as administrator as shown in Figure 11 Figure 11 PGA5807 GUI Install a Set the destination directories for the PGA5807 GUI installation or leave as default and press the Next button as shown in Figure 12 Figure 12 PGA5807 GUI Install b 10 PGA5807A 8 Channel High Bandwidth Analog Front End Evalua...

Page 11: ...3 Figure 13 PGA5807 GUI Install c Read the License Agreement from National Instruments and select the I accept the License Agreement button and then press the Next button as shown in Figure 14 Figure 14 PGA5807 GUI Install d 11 SLAU538 October 2013 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation Module Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 12: ...re 15 PGA5807 GUI Install e The window shown in Figure 16 should appear showing that installation is in progress Figure 16 PGA5807 GUI Install f 12 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation SLAU538 October 2013 Module Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 13: ...on the window in Figure 17 appears Press the Finish button to continue Figure 17 PGA5807 GUI Install g 13 SLAU538 October 2013 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation Module Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 14: ... Input Output and ADS5296A only ADC Input Figure 18 highlights which SMAs are to be used for each configuration Note The PGA5807A output channels do not numerically match the input channels of the ADS5296A hence there is a mapping from one to the other The silkscreen designators are named in such a way as to describe the mapping For instance the signal input to channel 1 of the PGA5807A at SMA J10...

Page 15: ...consequences on the device and is therefore not a recommended implementation Figure 19 TSW1400 and PGA5807A Setup 1 Mate the TSW1400 EVM at connector J4 to the PGA5807A EVM at connector J1 through the high speed ADC interface connector 2 Connect the DC 5 V output of the provided AC to DC power supply to J12 5V_IN of the TSW1400 EVM and the input of the power supply cable to a 110 230 VAC source 3 ...

Page 16: ...AL oscillator 1 GND or 3 3 3V JP12 short pins 1 2 XTAL XTAL_CDC Sampling clock Selects path for XTAL osc signal 1 to transformer or 3 to CDC input JP13 short pins 1 2 XTAL CLK_CDC Sampling clock Selects input source to CDC input 1 XTAL osc or 3 external source input to SMA J5 CLK_IN JP8 short pins 2 3 SE DIFF Sampling clock Selects ADC sampling clock configuration 1 Single ended 3 Differential mus...

Page 17: ... Testing PGA5807A Figure 20 PGA5807A EVM Default Header Configuration 17 SLAU538 October 2013 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation Module Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 18: ...ls by changing the position of a few 0 Ω jumper resistors As an example Figure 21 shows one page of the EVM schematics see Section 6 for full schematics The table on the bottom right side of this schematic page shows which 0 Ω resistors must be installed for each configuration The configuration pictured routes the PGA output from channel 1 to channel 5 of the ADS5296A Figure 21 PGA5807A EVM Schema...

Page 19: ...5 For a detailed explanation of the High Speed Data Converter Pro software GUI please consult the TSW1400 User s Guide SLWU079B available on the Texas Instruments website 4 1 TSW1400 and PGA5807 GUI Setup 1 With the setup outlined in Figure 19 established launch the High Speed Data Converter Pro GUI The GUI should automatically detect the serial number of the TSW1400 EVM connected as shown in Figu...

Page 20: ...device by clicking on the Blue arrow in the upper left corner of the HSDCpro GUI Scroll down and select PGA5807 as shown in Figure 25 Figure 25 TSW1400 GUI Setup d 70 Click the Yes button to update the ADC firmware on the TSW1400 FPGA as depicted in Figure 26 Figure 26 TSW1400 GUI Setup e 20 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation SLAU538 October 2013 Module Submit Documentat...

Page 21: ...igure 27 TSW1400 GUI Setup f Once loaded the plug in PGA5807 GUI will appear as a new tab within the HSDCpro GUI as shown in Figure 28 Figure 28 PGA5807 Plug in GUI Setup 21 SLAU538 October 2013 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation Module Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 22: ...hown in Figure 29 Figure 29 PGA5807 Plug in GUI Setup h As shown in Figure 30 the PGA5807 tab contains all controls pertaining to the PGA5807 device installed on the EVM Figure 30 PGA5807 Tab in the PGA5807 GUI 22 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation SLAU538 October 2013 Module Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 23: ...ply current drop from 650 mA 750 mA to 350 mA 450 mA If the DC current is approximately 480 mA with both power down boxes unchecked it indicates that the ADS5296A is not receiving the sampling clock Please ensure that the 3 pin headers are configured as described in Section 3 2 Before continuing ensure that both power down boxes are left unchecked At this point the GUI is confirmed to be communica...

Page 24: ...t EVM configuration and minimal bench equipment 1 Within the ADS5296 tab press on the sub tab labeled Test Pattern and select RAMP PATTERN within the TEST_PATT menu as shown in Figure 32 Figure 32 ADS5296A Setup for RAMP Test 24 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation SLAU538 October 2013 Module Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 25: ...e the plot type from Real FFT to Codes c Enter 80M in the field labeled ADC Output Data Rate d Press the Capture button Figure 33 HSDCpro GUI Setup for RAMP Test 25 SLAU538 October 2013 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation Module Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 26: ...wn in Figure 35 to view all 8 channels and confirm that a saw tooth waveform has been captured Also confirm in the menu to the left side that the min code is 0 and the max code is 4095 corresponding to a 12 bit ADC Figure 35 RAMP Capture by Channel 26 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation SLAU538 October 2013 Module Submit Documentation Feedback Copyright 2013 Texas Instrum...

Page 27: ...DC code for each subsequent sample Figure 36 Zoom on RAMP Capture 6 Reset the ADS5296 so that the RAMP test pattern is off as shown in Figure 37 Figure 37 Turn off RAMP Test Pattern 27 SLAU538 October 2013 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation Module Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 28: ...ce as it is not phase locked to the input signal The XTAL should be disabled by moving jumper JP11 from the position labeled CDC_3 3V to the position labeled GND in the silkscreen Also JP9 must change position from XTAL to CLK_IN in the silkscreen to enable the SMA J5 CLK_IN Figure 38 and Figure 39 show the jumper positions before and after this change respectively Figure 38 Jumper JP11 and JP9 Po...

Page 29: ...or high performance results the instrument should have low phase noise and low harmonic distortion In addition a filter is recommended on the input c The two signal generators in items a and b above should be phase locked so that coherency is established This is achieved connecting the two via a BNC cable One instrument will provide 10 MHz output while the other instrument will receive 10 MHz inpu...

Page 30: ... labeled Auto Calculation of Coherent Frequencies Note the ADC Input Target Frequency box will automatically be updated with the required coherent frequency d Change the frequency on the signal generator providing the analog input signal to match the value shown in the ADC Input Target Frequency box 4 99633789MHz e Press the Capture button 30 PGA5807A 8 Channel High Bandwidth Analog Front End Eval...

Page 31: ... loss and filter insertion loss which can vary among parts If needed reset the signal amplitude level until the Fund value is approximately 1 0 dBFs as this is the condition for which the datasheet specifications are set The input level was iteratively adjusted to achieve 1 0 dBFs as seen in Figure 42 Figure 42 ADS5296A Only Sinusoidal Capture 1 31 SLAU538 October 2013 PGA5807A 8 Channel High Band...

Page 32: ...by connecting the two via a BNC cable One instrument will provide 10 MHz output while the other instrument will receive 10 MHz input Figure 43 PGA5807A ADS5296A Gain Test Setup 2 Click on the PGA5807 tab as shown in Figure 44 a The default state for PGA_GAIN is 18dB Note The PGA5807A gain and filter bandwidth can be set in one of two ways through the SPI or through dedicated device pins Both optio...

Page 33: ...the PGA5807A should be adjusted and a re capture done iteratively until the Fund value is approximately 1 0 dBFs As 1 0 dBFs is the ADC level at which datasheet specifications are set the SNR and THD of the signal chain can be taken from the table to left at this value of Fund Figure 45 PGA5807A ADS5296A SNR THD Gain Test Capture 1 33 SLAU538 October 2013 PGA5807A 8 Channel High Bandwidth Analog F...

Page 34: ...e ADC tab and pressing Capture results in Figure 47 Take the difference in the Fund value shown here to the previous capture This difference should equal the difference in PGA_GAIN values between the two captures or 18 dB In this example the difference is 17 4 dB 34 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation SLAU538 October 2013 Module Submit Documentation Feedback Copyright 201...

Page 35: ...ntrol to HIGH This will disable the SPI CONTROL SECTION and enable the DEVICE PIN CONTROL SECTION as shown in Figure 48 Figure 48 PGA5807 GUI Setup for PGA5807A ADS5296A Gain Test 3 7 Click on the ADC tab and press the Capture button to see the result shown in Figure 49 35 SLAU538 October 2013 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation Module Submit Documentation Feedback Copyri...

Page 36: ...5807A ADS5296A Gain Test 4 9 Click on the ADC tab and press the Capture button to see the result shown in Figure 51 Again take the difference in the Fund value shown here to previous capture This difference should equal the differerence in GAIN x value that was set or 18dB 36 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation SLAU538 October 2013 Module Submit Documentation Feedback Cop...

Page 37: ...h tab of the PGA5807 software GUI Read Me First PGA5807 and ADS5296 After launching HSDCpro the PGA5807 GUI can be invoked in two ways normal mode or simulation mode Simulation mode is used in the event that no PGA5807A EVM is available When this is the case the message shown in Figure 52 will appear automatically shortly after choosing the PGA5807A device in HSDCpro drop down menu Figure 52 PGA58...

Page 38: ...First as shown in Figure 53 Simulation checkbox will be unchecked if EVM is connected The two sections in the upper right corner of this tab SIMULATION and RECORD PLAYBACK COMMAND SEQUENCE are common to all tabs within the PGA5807 GUI The RECORD PLAYBACK COMMAND SEQUENCE section allows the user to Record a sequence of commands Save the sequence that was recorded to a file Playback a sequence that ...

Page 39: ...OF ADS5296 shown in the table at the bottom of the tab The table includes the maximum sampling clock speed supported for each mode Ensure that the clock source is within this limit for a particular mode Figure 55 PLAYBACK COMMAND SEQUENCE 5 2 PGA5807 tab The second tab under the PGA5807 GUII tab is PGA5807 As shown in Figure 56 this tab contains three sections DEVICE PIN CONTROL SECTION SPI CONTRO...

Page 40: ...y as the name implies it provides static logic levels to PGA5807A device pins for programming the reset PGA gain power down and filter bandwidth As Figure 58 shows when the RESET Pin 60 is held High all controls in this section are enabled and the SPI interface is disabled causing SPI CONTROL SECTION to become greyed and disabled not shown in Figure 58 The PGA RESET PIN INFO is provided as a remin...

Page 41: ...button in the GAIN section is selected Figure 59 Gain Info Button The SPI CONTROL SECTION writes to the device s SPI interface for programming the software reset PGA gain and filter bandwidth As Figure 60 shows this section is enabled only when the RESET Pin 60 pin is set LOW Figure 60 Gain Info Button 41 SLAU538 October 2013 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation Module Sub...

Page 42: ...l automatically update to reflect the current state of the device Figure 61 shows that when the value of register 0x3B containing field PGA_GAIN was written as 0x0 and then as 0x20 the PGA_GAIN control updated its value to reflect the present state of the device Figure 61 Custom WRITE READ 42 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation SLAU538 October 2013 Module Submit Documenta...

Page 43: ...ttern Digital Signal Processing and Channel Filter For an in depth explanation of the ADS5296 GUI and all its features please refer to Section 5 of the ADS5296A User s Guide SLAU537 Figure 62 ADS5296 Tab 43 SLAU538 October 2013 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation Module Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 44: ...07A EVM Schematics Figure 63 PGA5807A Schematic Sh 1 of 16 PGA5807A Device 44 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation Module SLAU538 October 2013 Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 45: ... 79 81 81 83 83 85 85 87 87 89 89 91 91 93 93 95 95 97 97 99 99 61 61 62 62 101 101 102 102 103 103 104 104 105 105 106 106 107 107 108 108 109 109 110 110 111 111 112 112 113 113 114 114 115 115 116 116 117 117 118 118 119 119 120 120 J1B 1 3 2 JP4 0 1uF 1 2 C12 0 1uF 1 2 C11 Z_SH H3 M S A D E N 1 5 2 3 4 J2 0 1uF 1 2 C10 1 8V_AVDD 1 8V_LVDD 1 8V_AVDD 1 8V_AVDD 1 8V_AVDD 1 8V_AVDD SCLK ADCRESETZ ...

Page 46: ...TAL DIFF SE XTAL_CDC XTAL 1 3 2 JP11 1 3 2 JP12 1 3 2 JP13 1 3 2 JP9 1 3 2 JP8 1 3 2 JP10 DIFF SE 0Ohm 1 1 2 2 R8 0Ohm 1 1 2 2 R11 Change to 130 82ohm like ADS5295 Jumper Selection for Clock Signal Path Differential Input Single End Input External Signal Generator Drive On board 80M XTAL Drive Ext Signal Generator Drive through CDC Default On board 80M XTAL Drive through CDC R16 82 OHM R17 82 OHM ...

Page 47: ...19 A 1 1 Transformer is needed here 0 1uF 1 2 C26 PGA_VCM 0Ohm DNI R26 24 9 Ohm R24 24 9 Ohm R29 0 1uF 1 2 C24 0 1uF 1 2 C22 ADT1 1WT 4 5 6 3 2 1 T3 0 1uF 1 2 C30 0 1uF 1 2 C32 GND GND GND 6 8 pF 1 2 C27 10 ohm 1 2 R20 10 ohm 1 2 R34 0Ohm R23 0Ohm R30 0Ohm R35 0Ohm R21 A 1 1 Transformer is needed here 0 1uF 1 2 C28 PGA_VCM 0Ohm DNI R27 24 9 Ohm R25 24 9 Ohm R31 0 1uF 1 2 C36 0 1uF 1 2 C34 ADT1 1WT...

Page 48: ...73 A 1 1 Transformer is needed here 0 1uF 1 2 C63 PGA_VCM 0Ohm DNI R80 24 9 Ohm R78 24 9 Ohm R84 0 1uF 1 2 C60 0 1uF 1 2 C58 ADT1 1WT 4 5 6 3 2 1 T9 0 1uF 1 2 C66 0 1uF 1 2 C68 GND GND GND 6 8 pF 1 2 C62 10 ohm 1 2 R74 10 ohm 1 2 R88 0Ohm R77 0Ohm R83 0Ohm R89 0Ohm R75 A 1 1 Transformer is needed here 0 1uF 1 2 C64 PGA_VCM 0Ohm DNI R81 24 9 Ohm R79 24 9 Ohm R85 0 1uF 1 2 C48 0 1uF 1 2 C46 ADT1 1WT...

Page 49: ... C74 0 ohm R91 0 ohm R105 SMA_TO_ADC_INPUT PGA_OUT_TO_ADC_INPUT PGA_OUTPUT_TO_SMA 0 ohm DNI R90 0 ohm DNI R103 0 ohm R109 0 ohm R110 T Resistor 0Ohm R99 0Ohm R108 Fork Resistor Resistor Installtion for Different Applications Signal Path T Resistor Fork Resistor R109 R110 PGA_Output to ADC_Input PGA_Output to SMA_Output SMA_Input to ADC_Input R99 R108 R92 R106 Don t Care Don t Care R99 R108 R90 R10...

Page 50: ... 2 1 T14 0 1uF 1 2 C147 GND 0 1uF 1 2 C142 0 1uF 1 2 C146 0 ohm R207 0 ohm R221 SMA_TO_ADC_INPUT PGA_OUT_TO_ADC_INPUT PGA_OUTPUT_TO_SMA 0 ohm DNI R206 0 ohm DNI R219 0 ohm R225 0 ohm R226 T Resistor 0Ohm R215 0Ohm R224 Fork Resistor Resistor Installtion for Different Applications Signal Path T Resistor Fork Resistor PGA_Output to ADC_Input PGA_Output to SMA_Output SMA_Input to ADC_Input Don t Care...

Page 51: ... 2 1 T12 0 1uF 1 2 C134 GND 0 1uF 1 2 C129 0 1uF 1 2 C133 0 ohm R181 0 ohm R195 SMA_TO_ADC_INPUT PGA_OUT_TO_ADC_INPUT PGA_OUTPUT_TO_SMA 0 ohm DNI R180 0 ohm DNI R193 0 ohm R199 0 ohm R200 T Resistor 0Ohm R189 0Ohm R198 Fork Resistor Resistor Installtion for Different Applications Signal Path T Resistor Fork Resistor PGA_Output to ADC_Input PGA_Output to SMA_Output SMA_Input to ADC_Input Don t Care...

Page 52: ... 2 1 T16 0 1uF 1 2 C160 GND 0 1uF 1 2 C155 0 1uF 1 2 C159 0 ohm R233 0 ohm R247 SMA_TO_ADC_INPUT PGA_OUT_TO_ADC_INPUT PGA_OUTPUT_TO_SMA 0 ohm DNI R232 0 ohm DNI R245 0 ohm R251 0 ohm R252 T Resistor 0Ohm R241 0Ohm R250 Fork Resistor Resistor Installtion for Different Applications Signal Path T Resistor Fork Resistor PGA_Output to ADC_Input PGA_Output to SMA_Output SMA_Input to ADC_Input Don t Care...

Page 53: ...m R259 0 ohm R273 SMA_TO_ADC_INPUT PGA_OUT_TO_ADC_INPUT PGA_OUTPUT_TO_SMA 0 ohm DNI R267 0 ohm DNI R276 0 ohm R277 T Resistor 0Ohm R258 0Ohm R271 Fork Resistor Resistor Installtion for Different Applications Signal Path T Resistor Fork Resistor PGA_Output to ADC_Input PGA_Output to SMA_Output SMA_Input to ADC_Input Don t Care Don t Care Default 0 ohm DNI R275 0 ohm DNI R266 0 ohm DNI R278 PGA_OUT5...

Page 54: ...m R285 0 ohm R299 SMA_TO_ADC_INPUT PGA_OUT_TO_ADC_INPUT PGA_OUTPUT_TO_SMA 0 ohm DNI R293 0 ohm DNI R302 0 ohm R303 T Resistor 0Ohm R284 0Ohm R297 Fork Resistor Resistor Installtion for Different Applications Signal Path T Resistor Fork Resistor PGA_Output to ADC_Input PGA_Output to SMA_Output SMA_Input to ADC_Input Don t Care Don t Care Default 0 ohm DNI R301 0 ohm DNI R292 0 ohm DNI R304 PGA_OUT6...

Page 55: ...m R318 0 ohm R327 SMA_TO_ADC_INPUT PGA_OUT_TO_ADC_INPUT PGA_OUTPUT_TO_SMA 0 ohm DNI R312 0 ohm DNI R325 0 ohm R330 T Resistor 0Ohm R311 0Ohm R324 Fork Resistor Resistor Installtion for Different Applications Signal Path T Resistor Fork Resistor PGA_Output to ADC_Input PGA_Output to SMA_Output SMA_Input to ADC_Input Don t Care Don t Care Default 0 ohm DNI R323 0 ohm DNI R310 0 ohm DNI R329 PGA_OUT7...

Page 56: ...m R344 0 ohm R353 SMA_TO_ADC_INPUT PGA_OUT_TO_ADC_INPUT PGA_OUTPUT_TO_SMA 0 ohm DNI R338 0 ohm DNI R351 0 ohm R356 T Resistor 0Ohm R337 0Ohm R350 Fork Resistor Resistor Installtion for Different Applications Signal Path T Resistor Fork Resistor PGA_Output to ADC_Input PGA_Output to SMA_Output SMA_Input to ADC_Input Don t Care Don t Care Default 0 ohm DNI R349 0 ohm DNI R336 0 ohm DNI R355 PGA_OUT8...

Page 57: ...D 4 7K R364 GND CS 1 CLK 2 DI 3 DO 4 GND 5 ORG 6 NC 7 VCC 8 93LC46BT I SN U20 10K Ohm 1 2 R365 3 3V_USB 2 2K R373 GND 3 3V_USB GND 27pF 1 2 C231 GND GND 1 8V_USB 3 3V_USB GND GND 1 kOhm 100MHz L3 Inductor Iron 68 ohm 100MHz FB1 Inductor Iron 1 3 4 2 12MHz Y1 100uF 1 2 C227 10 R363 22pF 1 2 DNI C230 1K R372 10K Ohm 1 2 R366 10K Ohm 1 2 R367 10K Ohm 1 2 R368 27pF 1 2 C232 0 1UF 1 2 C234 0 1UF 1 2 C2...

Page 58: ...C95 GND GND 0 1uF 1 2 C96 1uF 1 2 C93 GND GND 0 1uF 1 2 C94 TP27 D C 5 1 ohm 1 2 R133 5 1 ohm 1 2 R127 1K OHM 1 2 R129 1K OHM 1 2 R126 100PF C92 100PF C91 0 ohm 1 1 2 2 R136 0 ohm DNI 1 1 2 2 R130 TP28 TP25 PGA_VCM PGA_VCM_FORCE ADC_VCM TP26 ADC_VCM 0Ohm DNI R125 0Ohm DNI R135 2 5V_REF GND 1 Resistors needed here OPA4353EA 2 3 1 A U5A OPA4353EA 6 5 7 B U5B PGA_VCM 0 ohm DNI 1 1 2 2 R134 VCM 0 ohm ...

Page 59: ...56K 1 2 R147 56K 1 2 R146 10UF C120 10UF C116 RED J20 BLACK J24 0 1uF 1 2 C114 0 1uF 1 2 C115 0 1uF 1 2 C103 0 1uF 1 2 C106 0 1uF 1 2 C102 0 1uF 1 2 C110 0 1uF 1 2 C117 0 1uF 1 2 C121 GND GND 5V 3 3V_AVDD PURE GREEN PURE GREEN 332 1 2 R154 LNJ308G8PRA LED1 LNJ308G8PRA LED2 WHITE J27 10UF C107 1uF 1 2 C108 5V 1 8V_AVDD is for ADS5296 3 3_AVDD is for PGA5807 WHITE J26 5V_IN 1 8V_LVDD is for ADS5296 ...

Page 60: ...F AVX 0603YC105KAT2A CAP CER 1 0UF 16V X7R 10 0603 C111 C118 10 C84 C100 C105 C107 C112 C113 C116 C119 C120 C219 10UF AVX TAJB106K016RNJ CAP TANT 10UF 16V 10 1210 1 C220 0 01uF MURATA GRM155R71E103KA01D CAP CER 0 01UF 25V 10 X7R 0402 3 C221 C223 C225 4 7uF AVX TAJA475K016RNJ CAP TANT 4 7UF 16V 10 1206 2 C222 C224 0 1UF TAIYO YUDEN EMK105BJ104KV F CAP CER 0 1UF 16V 10 X5R 0402 1 C226 10uF MURATA GR...

Page 61: ...5 R128 R130 R134 R135 R138 R140 R143 R144 R156 R157 R158 R159 R161 R162 R163 R180 R185 R191 R193 R206 R211 R217 R219 R232 R237 R243 R245 R263 R266 R267 R269 R275 R276 R278 R289 R292 R293 R295 R301 R302 R304 R310 R312 R315 R321 R323 R325 R329 R336 R338 R341 R347 R349 R351 R355 2 R16 R17 82 OHM VISHAY CRCW060382R0FKEA RESISTOR THICK FILM 82 OHM 1 0 10W SMT0603 32 R24 R25 R29 R31 R42 R43 R48 R49 R60 ...

Page 62: ...d 1 J26 Keystone 5002 Tespoints White 1 U1 ADS5296A Texas Instruments ADS5296AIRGC TI Supplied Device 1 U2 80 MHZ ECS INC ECS 3953M 800 BN OSCILLATOR 80 MHZ 4 PIN 1 U3 CDCLVP1102 Texas Instruments CDCLVP1102RGTT IC CLK BUFF 1 2 LVPECL SGL 16QFN 8 U4 U10 U11 U12 U13 U14 U15 U16 TEXAS INSTRUMENTS OPA842IDBVT IC WIDEBAND LOW DISTORTION UNITY GAIN STABLE VOLTAGE FEEDBACK OPAMP SOT23 5 DBV 1 U5 2 7 V T...

Page 63: ...gure 86 illustrate the PCB layouts for the EVM Figure 79 PGA5807A EVM Top Layer Assembly Drawing Top View 63 SLAU538 October 2013 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation Module Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 64: ...Figure 80 PGA5807A EVM Bottom Layer Assembly Drawing Bottom View 64 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation Module SLAU538 October 2013 Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 65: ...807A EVM Layout Figure 81 PGA5807A EVM Top Side 65 SLAU538 October 2013 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation Module Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 66: ...t www ti com Figure 82 PGA5807A EVM Ground Plane 1 66 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation Module SLAU538 October 2013 Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 67: ...EVM Layout Figure 83 PGA5807A EVM Power Split Plane 1 67 SLAU538 October 2013 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation Module Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 68: ...www ti com Figure 84 PGA5807A EVM Power Split Plane 2 68 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation Module SLAU538 October 2013 Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 69: ... EVM Layout Figure 85 PGA5807A EVM GND Split Plane 2 69 SLAU538 October 2013 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation Module Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 70: ...out www ti com Figure 86 PGA5807A EVM Bottom Side 70 PGA5807A 8 Channel High Bandwidth Analog Front End Evaluation Module SLAU538 October 2013 Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 71: ...ency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC or ICES 003 rules which are designed to provide reasonable protection against radio frequency interference Operation of the equipment may cause interference with radio communications in which case the user at his own expense will be required to take whatever measures may be required t...

Page 72: ... its gain should be so chosen that the equivalent isotropically radiated power e i r p is not more than that necessary for successful communication This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated Antenna types not included in this l...

Page 73: ...tained the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect to this product Also please do not transfer this product unless you give the same notice above to the transferee Please note that if you could not follow the instructions above you will be subject to penalties of Radio Law of Japan Texas Instruments Japan Limited address 24 1 Nishi Shinjuku 6 c...

Page 74: ...derations per the user guidelines Exceeding the specified EVM ratings including but not limited to input and output voltage current power and environmental ranges may cause property damage personal injury or death If there are questions concerning these ratings please contact a TI field representative prior to connecting interface electronics including input power and intended loads Any loads appl...

Page 75: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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