background image

2.2

Signal Definitions of J1 (25-Pin Male DSUB)

www.ti.com

System Setup

Table 1

lists the different signals connected to J1 on the PGA112_Test_Board. This table also identifies

signals connected to pins on J1 that are not used on the GA112_Test_Board.

Table 1. Signal Definition of J1 (25-Pin Male DSUB) on PGA112_Test_Board

J1 Pin

Signal

Used On This EVM?

PGA112 Pin

1

DAC A

Yes

DAC1

2

DAC B

Yes

DAC2

3

DAC C

Yes

DAC3

4

DAC D

Yes

V

REF

_DAC

5

ADS1+

Yes

ADS1+

6

ADS1–

Yes

ADS1–

7

ADS2+

Yes

ADS2+

8

ADS2–

Yes

ADS2–

9

I2C_SCK

No

10

I2C_SDA2

No

11

ONE_WIRE

No

12

I2C_SCK_ISO

No

13

I2C_SDA_ISO

No

14

X

No

15

XTR_LOOP–

No

16

INA–

No

17

V

DUT

Yes

V

DUT

18

V

CC

No

V

CC

19

+15V

No

20

–15V

No

21

GND

Yes

GND

22

SPI_SCK

Yes

SPI_SCK

23

SPI_CS1

Yes

SPI_CS1

24

SPI_DOUT

Yes

SPI_DOUT

25

SPI_DIN1

Yes

SPI_DIN1

SBOU073 – February 2009

PGA112 Evaluation Module

7

Submit Documentation Feedback

Summary of Contents for PGA112

Page 1: ... the EVM 12 9 Connecting the USB Cable 13 10 PGA112EVM Default Jumper Settings 14 11 PGA112EVM Software Functioning Properly 16 12 PGA112EVM Software No Communication With the USB DAQ Platform 17 13 Scaled Inputs to PGA112 113 18 14 Selection of Internal Reference or DAC Reference 18 15 PGA112 113 Bit Read Tables 19 16 PGA112 Measurement Module Tab 20 17 PGA112 113 Self Test Function 22 List of Ta...

Page 2: ...you check the TI web site at http www ti com to verify that you have the latest software It is also recommended that you watch the QuickStart Video included on the compact disk before using the PGA112EVM The complete kit includes the following items PGA112 test PCB USB DAQ platform PCB USB cable CD ROM containing this user s guide product software and a demonstration video The following document p...

Page 3: ...www ti com Overview Figure 1 Hardware Included with the PGA112EVM SBOU073 February 2009 PGA112 Evaluation Module 3 Submit Documentation Feedback ...

Page 4: ...quipment The information in a caution or a warning is provided for your protection Please read each caution carefully Figure 2 shows the system setup for the PGA112EVM The PC runs software that communicates with the USB DAQ Platform The USB DAQ Platform generates the analog and digital signals used to communicate with the PGA112_Test_Board Connectors on the PGA112_Test_Board allow the user to conn...

Page 5: ...a block diagram of the PGA112_Test_Board The functionality of this PCB is relatively simple It provides connections to the I2 C and general purpose input outputs GPIO on the USB DAQ Platform board It also provides connection points for external connections of the shunt voltage bus voltage and GND Figure 3 PGA112_Test_Board Block Diagram See Figure 4 for an illustration of the PGA112_Test_Board sch...

Page 6: ...System Setup www ti com Figure 4 PGA112_Test_Board Schematic PGA112 Evaluation Module 6 SBOU073 February 2009 Submit Documentation Feedback ...

Page 7: ...gnal Used On This EVM PGA112 Pin 1 DAC A Yes DAC1 2 DAC B Yes DAC2 3 DAC C Yes DAC3 4 DAC D Yes VREF_DAC 5 ADS1 Yes ADS1 6 ADS1 Yes ADS1 7 ADS2 Yes ADS2 8 ADS2 Yes ADS2 9 I2C_SCK No 10 I2C_SDA2 No 11 ONE_WIRE No 12 I2C_SCK_ISO No 13 I2C_SDA_ISO No 14 XTR_LOOP No 15 XTR_LOOP No 16 INA No 17 VDUT Yes VDUT 18 VCC No VCC 19 15V No 20 15V No 21 GND Yes GND 22 SPI_SCK Yes SPI_SCK 23 SPI_CS1 Yes SPI_CS1 ...

Page 8: ...J2 Pin Signal Used On This EVM PGA112 Pin 1 NC No 2 CTRL1 Yes CTRL1 3 CTRL2 Yes CTRL2 4 CTRL3 Yes CTRL3 5 CTRL4 Yes CTRL4 6 CTRL5 Yes CTRL5 7 CTRL6 Yes CTRL6 8 CTRL7 Yes CTRL7 9 CTRL8 Yes CTRL8 10 MEAS1 No 11 MEAS2 No 12 MEAS3 No 13 MEAS4 No 14 MEAS5 No 15 MEAS6 No 16 MEAS7 No 17 MEAS8 No 18 SPI_SCK Yes SPI_SCK 19 SPI_CS2 Yes SPI_CS2 20 SPI_DOUT2 Yes SPI_DOUT2 21 SPI_DIN2 Yes SPI_DIN2 22 VDUT Yes ...

Page 9: ... are included in a separate document available for download at www ti com The block diagram shown in Figure 5 gives a brief overview of the platform The primary control device on the USB DAQ Platform is the TUSB3210 Figure 5 USB_DAQ_Platform Block Diagram The PGA112EVM hardware setup involves connecting the two PCBs of the EVM together applying power connecting the USB cable and setting the jumper...

Page 10: ...the EVM together applying power and connecting an external shunt and load The external connections may be the real world system that the PGA112 will be incorporated into Figure 6 shows the typical hardware connections Figure 6 Typical Hardware Connections PGA112 Evaluation Module 10 SBOU073 February 2009 Submit Documentation Feedback ...

Page 11: ...r gently push on both sides of the D SUB connectors as shown in Figure 7 Make sure that the two connectors are completely pushed together that is loose connections may cause intermittent operation Figure 7 Connecting the Two EVM PCBs SBOU073 February 2009 PGA112 Evaluation Module 11 Submit Documentation Feedback ...

Page 12: ... power to the EVM Always connect power before connecting the USB cable If you connect the USB cable before connecting the power the computer will attempt to communicate with an unpowered device that will not be able to respond Figure 8 Connecting Power to the EVM PGA112 Evaluation Module 12 SBOU073 February 2009 Submit Documentation Feedback ...

Page 13: ...ically changes to Found New Hardware USB Human Interface Device This pop up indicates that the device is ready to be used The USB DAQ platform uses the Human Interface Device Drivers that are part of the Microsoft Windows operating system In some cases the Windows Add Hardware Wizard will pop up If this prompt occurs allow the system device manager to install the Human Interface Drivers by clickin...

Page 14: ...ect this jumper to the VREF_PGA pin doing so will allow you to use higher gains because the voltage at the VREF pin of the PGA112 113 will subtract from your input voltage Also you may want to debug your own SPI commands You can easily do this debugging by moving the DIO_112 113 CS_112 113 and SCK pins from the default INT positions to the external position EXT Likewise you can evaluate the output...

Page 15: ...s jumper selects external power or bus power External power is applied on J5 or T3 9V dc Bus power is 5V from the JUMP1 EXT USB External power is typically used because the USB power is noisy JUMP2 EXT Same as JUMP1 This jumper determines where the PGA112 gets its power supply In the VDUT position the EVM provides power The JUMP3 EE ON default setting is the VDUT position In the VS_EXT position th...

Page 16: ...EVM software Step 1 Software can be downloaded from the PGA112EVM web page or from the disk included with the PGA112EVM which contains a folder called Install_software Step 2 Find the file called setup exe Double click the file to start the installation process Step 3 Follow the on screen prompts to install the software Step 4 To remove the application use the Windows Control Panel utility Add Rem...

Page 17: ...cognizes the device If the sound is on you will hear the distinctive sound that you expect when a USB device is properly connected to the PC Figure 12 PGA112EVM Software No Communication With the USB DAQ Platform The PGA112EVM software has four different tabs that allow you to access different features of the PGA112 or PGA113 The Scaled Inputs tab allows the user to select which input will be used...

Page 18: ...a sine wave or a precision external input The Reference Input field allows the user to read the actual value of the onboard 2 5V reference The default jumper connection for this onboard reference is to the internal VREF_INT however the reference DAC that controls the output shift on the OPA333 operational amplifier may also be selected as the reference When the internal 2 5V reference is selected ...

Page 19: ...Tables This tab has the following controls Show the selection of either the PGA112 or the PGA113 Indicate which SPI bits are enabled for the selected device with a 1 Translation tables at the bottom of the window show the corresponding scope and binary gain SBOU073 February 2009 PGA112 Evaluation Module 19 Submit Documentation Feedback ...

Page 20: ...Choose the input source with the Scaled Inputs radio buttons Select the desired PGA112 or PGA113 internal MUX channel Select the internal binary or scope gain Displays the values of the inputs that will be placed on each MUX channel Select either a 3V or 5V supply and cycle the power for the ADS1100 measurement ADC Select the PGA112 or PGA113 output 2 5V reference CH0 input or CH1 input to be read...

Page 21: ...own Step 3 Measure the input voltage and output voltage using an external DVM or the ADS1100 for the minimum and maximum inputs Step 4 Calculate the actual gain using these equations Therefore the gain is calculated by Equation 4 Note that the gain is a slope term that requires two points of measurement typically at the min and max endpoints The offset VOS and the reference VREF terms drop out of ...

Page 22: ...12 Software Overview www ti com The Self Test function is illustrated in Figure 17 This function can be used to Figure 17 PGA112 113 Self Test Function PGA112 Evaluation Module 22 SBOU073 February 2009 Submit Documentation Feedback ...

Page 23: ... 5 0603 ECG VA V SMD 8 2 100 R14 R15 R16 RES 100 OHM YAEGO 9C06031A1000JLHF 0 5 1 5 1 10W 5 0603 T SMD 9 2 res array AR1 AR2 RES ARRAY CTS 746X101103JP 0 11 0 22 10K OHM CORPORATIO 10TRM BUSS N SMD RESISTOR ELE CTROCOMPON ENT 10 3 BNC_VERT 113F_BNC BNC_CHEAP TYCO 5227699 1 2 7 8 10 112F_BNC ELECTRONICS Vin_Ext1 AMP 11 1 Female J2 DB25RA FE CONN D SUB 5747846 5 3 82 3 82 RCPT R A 25POS GOLD 12 1 Ma...

Page 24: ... 99 1 99 STRIP SCK_EXT HEADER 100 CH0_113 SNGL STR Vref_112 Vcc 36POS cut int Vref_113 ONE position CH1_112 Jumpers CH0_112 Vout_112 GND2 GND1 Vref_Div1 GND3 Vref_DAC SPI_SCK1 Vdut Vdiff_out1 Vin_Ref1 VDAC2 Vout_113 Vref_int VDAC1 Vo112_Fil Vo113_Fil 25 11 HEADER CS_112 SCK CONN 3M ESD 929647 09 36 I 1 99 1 99 STRIP Vin_Ref HEADER 100 DIO_112 SNGL STR JPO_113 36POS cut into CS_113 three position J...

Page 25: ...e product This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application engineer or visit www ti com esh No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine process or combination in which such TI produ...

Page 26: ...ice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertis...

Reviews: