Texas Instruments PCM4222EVM, User Manual

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2.8 DSD Output Mode Configuration
Hardware Configuration
The PCM4222 supports a one-bit Direct Stream Digital (DSD) data output, which operates at either 64x or
128x the base PCM output sampling rate. The PCM4222 allows both the DSD and PCM output modes to
be enabled simultaneously. The DSD data for the left and right channels and the associated bit clock are
output at the DSD data port, or header J5.
Table 18 lists the pin configuration for header J5.
Table 18. DSD Data Port Header Pin Configuration
Header J5 Pin Number DSD Data Port Signal Name, Description
1 DSDCLK, DSD Bit Clock Output
3 DSDL, One-bit DSD Data Output for the Left Channel
5 DSDR, One-bit DSD Data Output for the Right Channel
2,4,6,7,8,9,10 Ground
The DSD output mode is enabled or disabled using the DSDEN input (pin 22). This input is controlled via
the DSDEN element on switch SW1.
Table 19 summarizes the operation of this switch. When the DSD
output is disabled, DSDCLK (pin 27), DSDL (pin 28), and DSDR (pin 29) are forced low.
Table 19. DSD Output Mode Configuration
Switch SW1, DSDEN DSD Output Mode
LO Disabled
HI Enabled
The DSD output data rate may be set to 64x or 128x the base PCM rate (typically 44.1kHz). The output
rate is selected via the DSDMODE input (pin 24). This input is controlled via the DSDMODE element on
switch SW1.
Table 20 summarizes the operation of this switch.
Table 20. DSD Output Rate Selection
Switch SW1, DSDMODE DSD Output Data Rate
LO 64x Oversampled Data with Output Rate = MCKI
÷
4
HI 128x Oversampled Data with Output Rate = MCKI
÷
2
For more information regarding DSD output mode operation, timing, and specifications, see the PCM4222
datasheet .
SBAU124 – December 2006 PCM4222EVM User's Guide 15
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