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Table 3-3. PCM182xEVM /PCM182xQ1EVM MD1 Modes
MD1 Modes
MD1
MSZ (0 = Slave, 1 = Master)
MD0 Functional Mode
0
0
DRE Disabled
1
0
The DRE is enabled with DRE_LVL = –36 dB and
DRE_MAXGAIN = 24 dB
MCLK
1
MCLK input in master mode
Table 3-4. PCM182xEVM /PCM182xQ1EVM Audio Output Format
Audio Output Data Format
FMT0
Audio Serial Interface Format
0
2-channel output with inter IC sound (I2S) mode
1
2-channel output with time division multiplexing (TDM) mode
All hardware pins are tied low by default, placing the device in slave mode with a linear phase filter, DRE
disabled, and 2-channel I2S audio output. Note that DRE is not supported for PCM1821/PCM1821-Q1 and only
applies to PCM1820/PCM1822/PCM1820-Q1/PCM1822-Q1. For more information on the operating modes of
the PCM182x device, see the PCM182x Stereo Channel, 32-Bit, 192-kHz, Burr-Brown
™
Audio ADC data sheet.
Hardware Configuration
SBAU363A – FEBRUARY 2021 – REVISED MARCH 2022
PCM182xEVM/PCM182xQ1EVM EVM User's Guide
5
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