Texas Instruments PCA9306, User Manual, Page: 3 / 13

BUS1 BUS2
SLAVE/MASTER
C
LOAD2
SDA2
SCL2
SDA1
SCL1
PCA9306 MASTER/SLAVE
R
PU1
V
DPU1
I2C
Control
SCL
SCL
R
PU1
I2C
Control
SDA
R
PU2
R
PU2
SDA
1
V
REF1
V
REF2
GND
EN
V
DPU2
200
l Q
Gate Bias
Gate Bias
C
LOAD2
C
LOAD1
C
LOAD1
PCA9306EVM
2
8
7
4 5
6 3
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EVM Hardware Block Diagram and Images
3 SCPU039 – October 2018
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Copyright © 2018, Texas Instruments Incorporated
PCA9306 I
2
C Buffer Evaluation Module
2 EVM Hardware Block Diagram and Images
The PCA9306EVM is designed to perform voltage level translation between two buses. The two
voltage nodes are voltage device pull-up 1 (V
DPU1
) and voltage device pull-up 2 (V
DPU2
). The EVM
divides the buses into BUS1 and BUS2. All the pull-ups and capacitive loads are reference to the bus
they are used on, for example resistor pull-up 1 (R
PU1
) is on BUS1. Figure 2 shows the high level block
diagram for the PCA9306EVM with respect to how it is connected between I
2
C devices. Figure 3
illustrates the EVM schematic.
Figure 2. Block level diagram of PCA9306EVM in system