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2P5V_RX
2P5V_TX
SPLIT PLANES AND BULK DECOUPLING
3P3V
_ROSA_PWR
VCC
2.5V
GND
POWER AND LOCAL DECOUPLING
Note: Isolate the VCC Nets on
either side of the Header
Pins. Connect them only
through a Wide Trace directly
between the pins on the Bottom
Layer of the Board.
2P5V_VDD
2.5V EXTERNAL INPUT
3.3V EXTERNAL INPUT
VCC
3.3V
- DNI
- DNI
2P5V_INV
VINV_C
1+
VINV_C
1-
2P5V_SOURCE
2P5V_SOURCE
2P5V_SOURCE
2P5V_RX
2P5V_TX
2P5V_RX
2P5V_TX
2P5V_VDD
2P5V_VDD
2P5V_TX
2P5V_RX
2P5V_SOURCE
2P5V_VDD
2P5V_SOURCE
2P5V_NEG
3P3V_SOURCE
3P3V_ROSA
3P3V_SOURCE
C24
1uF
L13
C33
100pF
C55
1uF
L11
C30
10uF
C25
0.1uF
C34
10uF
C14
0.1uF
P5
Banana-Jack
1
C6
0.1uF
R1
50
C8
1uF
C13
0.1uF
U1F
ONET1131Ex
VCC_TX1
11
VCC_TX2
14
C9
10uF
C21
0.1uF
L10
C20 DNI - 100pF
C19
DNI - 0.1uF
L16
U1K
ONET1131Ex
VDD
15
C46
0.1uF
L8
JMP6
2 Pin Header
1
2
C31
1uF
C12
0.1uF
C15
22uF
C26
10uF
P1
Banana-Jack
1
JMP3
DNI - 2 Pin Header
1
2
C48
1uF
C22
22uF
C32
0.1uF
C23
10uF
L14
C37
100pF
C36
0.1uF
L15
C11
0.1uF
U1E
ONET1131Ex
VCC_RX1
27
VCC_RX2
30
C17
DNI - 10uF
JMP4
2 Pin Header
1
2
JMP5
2 Pin Header
1
2
C18
DNI - 1uF
C28
0.1uF
P2
Banana-Jack
1
TPS60400
U4
IN
2
OUT
1
GND
4
C1
-
3
C1
+
5
L6
C29
100pF
C27
1uF
U1G
ONET1131Ex
GND1
3
GND2
6
GND3
19
GND4
22
GND_PAD
33
C35
1uF
C49
1uF
Copyright © 2016, Texas Instruments Incorporated
www.ti.com
Schematics and Bill of Materials
15
SLLU256 – October 2016
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Copyright © 2016, Texas Instruments Incorporated
ONET1131EC Evaluation Module
7
Schematics and Bill of Materials
This section contains the EVM schematics and BOM.
7.1
Schematics
Figure 14
,
Figure 15
, and
Figure 16
illustrate the EVM schematics.
Figure 14. Schematic (1 of 3)