Timers
8-4
8.2.1
Timer Interrupt Levels
Table 8–1. Timer Interrupts Levels
Timer
Corresponding Level 1 Interrupt
Required Sensitivity Setup
1
INT23
Edge
2
INT22
Edge
3
INT8
Edge
The timers are counters that receive a dedicated clock from clock generator
module #2 (either CK_REF or CK_GEN2 output divided by 2). This clock can
be prescaled (divided down) as controlled by the prescale clock timer value
(PTV) field of the control timer register (shown in Table 8–2, PTV Divisors:
32-Bit Timers).
Table 8–2. PTV Divisors: 32-Bit Timers
PTV
Divisor
0
2
1
4
2
8
3
16
4
32
5
64
6
128
7
256
The timer interrupt period is calculated as follows:
t
int
= t
clk
x (LO 1) x 2
(PTV+1)
where:
t
clk
is the clock period of the input clock.
The load timer register (LOAD_TIM) holds the value loaded when the
timer passes through 0 or when it starts.
PTV is the prescaler field located in the control timer register.
Table 8–3 shows the characteristics for all three timers for different input
frequencies.
