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Texas Instruments OMAP5910, Technical Reference Manual

The Texas Instruments OMAP5910 is an advanced electronic device, offering exceptional functionalities and high performance. To make the most out of this product, it is advisable to refer to the comprehensive "Reference Manual" available for download, free of charge, from our website.

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Real-Time Clock

7-171

MPU Public Peripherals

7.13.2.1

Time and Calendar Registers/Alarm Registers

To read or write correct data to and from the time and calendar registers/alarm
registers, the MPU must first poll the BUSY bit of the STATUS register until
BUSY is equal to zero. From this time, and for a time of 15 

µ

s (the available

access period), the MPU can safely access the time and calendar registers/
alarm registers. At the end of the access period, the MPU must restart the
previous sequence. If the MPU accesses the time and calendar registers
outside of the access period, the access is not ensured (see Figure 7–60).

Figure 7–60. Time and Calendar Registers and Alarm Register Access

Read BUSY bit

CLK_32 KHz

BUSY

TIPB

NSTROBE

Timer counter

Available TC

registers access

15 

µ

s

15 

µ

s

Available TC

registers access

15 

µ

s

Available TC

registers access

RTC update

32766

32767

0

1

Any read/write TC registers access

Forbidden TC

registers access

7.13.2.2

General Registers

The MPU can access the STATUS_REG and the CTRL_REG at any time
(except the CTRL_REG[5] bit, which must be changed only when the RTC is
stopped).

For the INTERRUPTS_REG, the MPU must respect the available access
period to prevent spurious interrupt.

Summary of Contents for OMAP5910

Page 1: ...OMAP5910 Dual Core Processor Technical Reference Manual Literature Number SPRU602B January 2003 ...

Page 2: ...nt that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or end...

Page 3: ...on ment Notational Conventions This document uses the following conventions Program listings program examples and interactive displays are shown in a special typeface similar to a typewriter s Examples use a bold version of the special typeface for emphasis interactive displays use a bold version of the special typeface to distinguish commands that you enter from items that the system displays suc...

Page 4: ...n instruction that has an optional parameter LALK 16 bit constant shift The LALK instruction has two parameters The first parameter 16 bit con stant is required The second parameter shift is optional As this syntax shows if you use the optional second parameter you must precede it with a comma Square brackets are also used as part of the pathname specification for VMS pathnames in this case the br...

Page 5: ...om Texas Instruments TMS320C55x DSP CPU Reference Guide SPRU371D TMS320C55x DSP Functional Overview SPRU312 TMS320C55x DSP Function Library DSPLIB Programmer s Reference SPRU422D TMS320C55x Technical Overview SPRU393 TMS320C55x DSP Programmer s Guide SPRU376A TMS320C55x DSP Mnemonic Instruction Set Ref Guide SPRU374F TMS320C55x Assembly Language Tools User s Guide SPRU280D TMS320C55x Optimizing C ...

Page 6: ...censed to Texas Instruments TMS320C5510 TMS320C55x C55x and Code Composer Studio are trademarks of Texas Instruments Microsoft Windows Windows CE Windows CE Platform Builder and Windows NT are trademarks of Microsoft Corporation Other trademarks are the property of their respective owners ...

Page 7: ... MPU Core 2 4 2 3 Instruction Cache 2 5 2 3 1 Operation 2 5 2 3 2 Validity 2 5 2 4 Data Cache 2 6 2 4 1 D Cache Operation 2 6 2 4 2 Validity 2 7 2 4 3 Double Mapped Space 2 8 2 5 Write Buffer 2 8 2 5 1 Operation 2 9 2 5 2 SWAP Instruction 2 9 2 6 Coprocessor 15 2 10 2 6 1 CP15 Access 2 10 2 6 2 Register Descriptions 2 10 2 7 MPU Memory Management Unit 2 26 2 7 1 Translation Look Aside Buffer 2 26 ...

Page 8: ...nment 2 75 2 12 1 ETM Features 2 75 2 12 2 ETM Interface 2 75 2 12 3 Operation 2 77 2 12 4 Additional Reference Materials 2 78 3 DSP Subsystem 3 1 Describes the OMAP5910 multimedia processor DSP subsystem 3 1 Architecture Overview 3 2 3 1 1 DSP Core 3 5 3 2 TMS320C55x DSP CPU Overview 3 6 3 2 1 On Chip Memory 3 6 3 2 2 Hardware Acceleration Modules 3 7 3 2 3 CPU Overview 3 7 3 3 DSP Memory 3 9 3 3...

Page 9: ... 3 1 Internal Memory Interface 4 12 4 3 2 External Memory Interface Slow 4 13 4 3 3 External Memory Interface Fast 4 25 4 4 Traffic Controller Memory Interface Registers 4 42 4 5 Interfacing Memories With the OMAP5910 Device 4 57 5 System DMA Controller 5 1 Describes the system DMA controller for the OMAP5910 multimedia processor 5 1 Introduction 5 2 5 2 External Connections 5 8 5 3 Generic Channe...

Page 10: ...pabilities 6 24 6 7 2 OMAP5910 Native and Compatibility Modes 6 24 6 7 3 OMAP5910 Generic Pin Multiplexing and Pullup Pulldown Control 6 25 6 7 4 OMAP5910 MMC SD Pin Multiplexing 6 26 6 7 5 OMAP5910 Pullups and Pulldowns 6 26 6 8 OMAP5910 Configuration Registers 6 27 6 9 Device Identification 6 70 6 9 1 Identification Code Register 6 70 6 9 2 Die Identification ID 6 71 7 MPU Public Peripherals 7 1...

Page 11: ...7 8 1 I2C Protocol Description 7 57 7 8 2 OMAP5910 I2C Master Slave I2C Controller 7 64 7 8 3 Programming 7 87 7 8 4 Flowcharts 7 88 7 9 LED Pulse Generator 7 100 7 9 1 Features 7 100 7 9 2 LPG Design 7 101 7 9 3 LPG Power Management 7 101 7 9 4 LPG Registers 7 101 7 10 McBSP2 7 104 7 10 1 McBSP2 Application Example Communication Interface 7 108 7 11 USB Function Overview 7 117 7 12 MMC SD Host Co...

Page 12: ...8 3 Watchdog Timer 8 10 8 3 1 Programming the Watchdog Timer in Watchdog Mode 8 12 8 3 2 Programming the Watchdog Timer in Timer Mode 8 12 8 3 3 Watchdog Timer Registers 8 13 8 4 Interrupt Handlers 8 15 8 4 1 Level 1 Interrupts 8 16 8 4 2 Level 2 Interrupts 8 17 8 5 DSP Interrupt Interface 8 26 8 5 1 Functional Description 8 26 8 5 2 Edge Triggered Interrupts 8 26 8 5 3 Level Sensitive Interrupts ...

Page 13: ...3 General Purpose I O 10 7 10 3 1 Input Outputs of the GPIO Module 10 7 10 3 2 GPIO Port Registers 10 7 10 4 UART1 UART2 and UART3 IrDA 10 11 11 LCD Controller 11 1 Describes the LCD controller module of the OMAP5910 device 11 1 Module Overview 11 2 11 2 Display Specifications 11 7 11 3 LCD Controller Operation 11 9 11 3 1 Frame Buffer 11 9 11 4 Lookup Palette 11 14 11 5 Color Grayscale Dithering ...

Page 14: ...FO Polled Mode 12 42 12 5 5 FIFO DMA Mode 12 42 12 5 6 Sleep Mode 12 44 12 5 7 Break and Time out Conditions 12 45 12 5 8 Programmable Baud Rate Generator 12 45 12 5 9 Hardware Flow Control 12 46 12 5 10 Software Flow Control 12 47 12 5 11 Autobauding Mode 12 48 12 6 UART Autobaud Configuration Example 12 50 12 6 1 UART SW Reset 12 51 12 6 2 UART FIFO Configuration 12 51 12 6 3 Baud Rate Data and ...

Page 15: ...2 3 Data Register DATA 13 13 13 2 4 Control Register CTRL 13 14 13 2 5 Status Register STAT_FLG 13 17 13 2 6 Receive FIFO Status Register RXFSTAT 13 22 13 2 7 System Configuration Register 1 SYSCON1 13 22 13 2 8 System Configuration Register 2 SYSCON2 13 24 13 2 9 Device Status Register DEVSTAT 13 26 13 2 10 Start of Frame Register SOF 13 29 13 2 11 Interrupt Enable Register IRQ_EN 13 30 13 2 12 I...

Page 16: ... 6 11 Non Isochronous Non Control OUT Endpoint Receive Interrupt Handler 13 105 13 6 12 Non Isochronous Non Control IN Endpoint Transmit Interrupt Handler 13 105 13 6 13 SOF Interrupt Handler 13 105 13 6 14 Summary of USB Related Interrupts 13 113 13 7 DMA Operation 13 114 13 7 1 Receive DMA Channels Overview 13 114 13 7 2 Non Isochronous OUT USB HOST LH DMA Transactions 13 114 13 7 3 Isochronous ...

Page 17: ...cture Pointers 14 84 14 6 4 NULL Pointers 14 91 14 6 5 Endianism and USB Host Controller Access to System Memory 14 91 14 7 OMAP5910 Local Bus 14 93 14 7 1 LB Register Descriptions 14 93 14 7 2 LB MPU Time out Register LB_MPU_TIMEOUT 14 94 14 7 3 LB Hold Timer Register LB_HOLD_TIMER 14 95 14 7 4 LB Priority Register LB_PRIORITY_REG 14 95 14 7 5 LB Clock Divider Register LB_CLOCK_DIV 14 96 14 7 6 L...

Page 18: ...xternal Master Mode 15 11 15 2 4 CLKM1 15 12 15 2 5 CLKM2 15 14 15 2 6 CLKM3 15 17 15 2 7 Clock Distribution and Synchronization 15 19 15 2 8 Low Power Mode 15 20 15 3 Power Management 15 21 15 3 1 DSP Idle Modes 15 24 15 3 2 MPU Idle Modes 15 26 15 3 3 Traffic Controller Idle Modes 15 30 15 3 4 Chip Idle and Wake Up Control 15 32 15 3 5 Power Saving Capability 15 38 15 3 6 ULPD Power Management S...

Page 19: ...31 2 13 Level 1 Descriptors 2 32 2 14 Section Translation 2 34 2 15 Page Table Entry Level 2 Descriptor 2 35 2 16 Tiny Page Translation 2 37 2 17 Small Page Translation 2 38 2 18 Large Page Translation 2 40 2 19 Domain Access Control Register Format 2 42 2 20 Sequence for Checking Faults 2 44 2 21 Nonaligned Read Word Access 2 45 2 22 MPUI Simplified Block Diagram 2 55 2 23 MPU TI Peripheral Bus B...

Page 20: ...y a Write Byte 4 39 4 17 SDRAM Write Single Followed by Write Burst 6 on the Same Bank and Different Page 4 40 4 18 SDRAM Read Single Half Word Followed by a Read Burst 8 With Page Crossing 4 41 4 19 External Memory Interconnection Using Intel Flash Memory 4 58 4 20 External Memory Interconnection Using Hitachi Flash Memory 4 59 5 1 Highlight of DMA Controller 5 2 5 2 DMA Controller Block Diagram ...

Page 21: ... Value 7 65 7 31 Setup Procedure 7 88 7 32 Master Transmitter Mode RM 1 7 89 7 33 Master Receiver Mode RM 1 Polling 1 Software Counter Number of the Receive Data Fixed 7 90 7 34 Master Receiver Mode RM 1 Polling 2 Number of the Receive Data is Variable Data Contents Dependent 7 91 7 35 Master Transmitter Mode RM 0 Polling 7 92 7 36 Master Receiver Mode RM 0 Polling 7 93 7 37 Master Transmitter Mod...

Page 22: ...2 DSP Timers 8 3 8 3 DSP Interrupt Handler Cascade 8 15 8 4 Level 2 Interrupt Control Flow 8 18 8 5 Interrupt Channel Implementation 8 27 8 6 Level Sensitive Interrupt Clear Commands 8 31 9 1 Highlight of Public Peripherals Area 9 2 9 2 McBSP1 Interface Diagram 9 5 9 3 I2S Audio Codec Interface 9 7 9 4 Waveform Example 9 11 9 5 McBSP3 Interface Diagram 9 12 9 6 Optical Audio Interface 9 15 9 7 Wav...

Page 23: ...mory Organization 11 13 11 9 16 BPP Frame Buffer Memory Organization 11 13 11 10 Dither Logic 11 27 11 11 Passive Mode Pixel Clock and Data Pin Timing 11 29 11 12 Active Mode Pixel Clock and Data Pin Timing 11 30 11 13 Active Mode End of Line Timing 11 34 11 14 Passive Mode End of Line Timing 11 34 11 15 Active Mode End of Frame Timing 11 37 11 16 Passive Mode End of Frame Timing 11 38 11 17 Signa...

Page 24: ...r 13 94 13 20 Prepare for Control Read Status Stage Routine 13 95 13 21 USB Function Device State Transitions 13 97 13 22 Typical Operation for USB Device State Changed Interrupt Handler 13 98 13 23 Attached Unattached Handler 13 99 13 24 USB Reset Handler Flowchart I 13 101 13 25 USB Reset Handler Flowchart II 13 102 13 26 Typical Operation for USB Suspend Resume General USB Interrupt Handler 13 ...

Page 25: ...OD_USB_HOST_HMC_MODE_R Set to 12 14 66 14 19 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 13 14 67 14 20 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 14 14 68 14 21 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 15 14 69 14 22 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 16 14 70 14 23 OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 17 14 71 14 24 OMAP5910 With CONF_MOD_USB_HOS...

Page 26: ...tion 15 12 15 6 DSP Clock Distribution 15 14 15 7 Traffic Controller Clock Distribution 15 17 15 8 OMAP5910 Clock Distribution and Synchronization 15 19 15 9 Low Voltage Mode 15 20 15 10 Power Management State Machine 15 22 15 11 Wake up Control Module 15 23 15 12 Code Example 15 28 15 13 Chip Idle and Wake Up Control 15 32 15 14 ULPD Controlled Wake Up Sequences 15 37 15 15 External Power Control...

Page 27: ... Bits in Domain Access Control Register 2 42 2 25 Interpreting Access Permission 2 43 2 26 DSP Memory Management Unit Registers 2 47 2 27 Prefetch Register PREFETCH_REG Offset Address hex 00 2 48 2 28 Prefetch Status Register WALKING_ST_REG Offset Address hex 04 2 48 2 29 Control Register CNTL_REG Offset Address hex 08 2 49 2 30 Fault Address Register MSB FAULT_AD_H_REG Offset Address hex 0C 2 49 ...

Page 28: ... Public Bridge Registers 2 68 2 61 TIPB Control Register TIPB_CNTL Offset x00 2 68 2 62 TIPB Bus Allocation Register TIPB_BUS_ALLOC Offset x04 2 68 2 63 MPU TIPB Control Register MPU_TIPB_CNTL_REG Offset x08 2 69 2 64 Enhanced TIPB Control Register ENHANCED_TIPB_CNTL Offset x0C 2 69 2 65 Address Debug Register ADDRESS_DBG Offset x10 2 69 2 66 Data Debug Register LSB DATA_DEBUG_LOW Offset x14 2 69 ...

Page 29: ...S Register EMRS Mode EMIFF_MRS 4 53 4 22 Time Out 1 Register TIMEOUT1 4 54 4 23 Time Out 2 Register TIMEOUT2 4 54 4 24 Time Out 3 Register TIMEOUT3 4 54 4 25 Endianism Register ENDIANISM 4 55 4 26 EMIF Fast Interface SDRAM Configuration Register 2 EMIFF_SDRAM_CONFIG_2 4 55 4 27 EMIF Slow Wait State Configuration EMIFS_CFG_DYN_WAIT 4 56 5 1 Possible Data Transfers 5 7 5 2 Possible Transfer Sizes an...

Page 30: ...A_LCD_BOT_F2_L 5 58 5 33 LCD Bottom Address for Frame Buffer 2 Upper Bits Register DMA_LCD_BOT_F2_U 5 58 6 1 Timer Level 1 Interrupt 6 3 6 2 PTV Value and Corresponding Division Value 6 4 6 3 Timer Characteristics 6 4 6 4 Timer Registers 6 6 6 5 Control Timer Register CNTL_TIMER 6 6 6 6 Load Timer Register LOAD_TIMER 6 7 6 7 Read Timer Register READ_TIMER 6 7 6 8 Watchdog Timer Level 1 Interrupt 6...

Page 31: ... 44 Pulldown Control 2 Register PULL_DWN_CTRL_2 6 53 6 45 Pulldown Control 3 Register PULL_DWN_CTRL_3 6 59 6 46 Gate and Inhibit Control 0 Register GATE_INH_CTRL_0 6 60 6 47 Voltage Control 0 Register VOLTAGE_CTRL_0 6 62 6 48 Test Debug Control 0 Register TEST_DBG_CTRL_0 6 63 6 49 Module Configuration Control 0 Register MOD_CONF_CTRL_0 6 64 6 50 ID Code Register IDCODE 6 70 6 51 ID Code Register I...

Page 32: ...ster PWL_CTRL 7 51 7 44 PWT Registers 7 53 7 45 PWT Frequency Control Register FRC 7 54 7 46 PWT Volume Control Register VRC 7 54 7 47 PWT General Control Register GCR 7 54 7 48 Buzzer Frequencies 7 55 7 49 Buzzer Volume 7 56 7 50 Signal Pads 7 58 7 51 Reset State of I2C Signals 7 58 7 52 I2C Registers 7 67 7 53 I2C Module Version Register I2C_REV 7 68 7 54 I2C Interrupt Enable Register I2C_IE 7 6...

Page 33: ... MMC_CMD Pullups 7 125 7 93 MMC_DAT Pullups 7 125 7 94 MMC SD Registers 7 126 7 95 MMC Command Register MMC_CMD 7 127 7 96 MMC Argument Low Register MMC_ARGL 7 130 7 97 MMC Argument High Register MMC_ARGH 7 130 7 98 MMC System Configuration Register MMC_CON 7 131 7 99 MMC_CLK SPI_CLK High Low Time Computation 7 134 7 100 MMC System Status Register MMC_STAT 7 135 7 101 Response Types 7 136 7 102 MM...

Page 34: ...ter ALARM_YEARS_REG 7 181 7 139 RTC Control Register RTC_CTRL_REG 7 182 7 140 RTC Status Register RTC_STATUS_REG 7 183 7 141 RTC Interrupts Register RTC_INTERRUPTS_REG 7 183 7 142 RTC Compensation LSB Register RTC_COMP_LSB_REG 7 184 7 143 RTC Compensation MSB Register RTC_COMP_MSB_REG 7 184 7 144 Memory Map Summary 7 195 7 145 Registers Accessible From TIPB 7 196 7 146 FAC Registers 7 202 7 147 Fr...

Page 35: ...Receive Control Register 2 Configuration DSP_Write 0x80a1 RCR2 9 9 9 8 Transmit Control Register 1 Configuration DSP_Write 0x00a0 XCR1 9 9 9 9 Transmit Control Register 2 Configuration DSP_Write 0x80a1 XCR2 9 10 9 10 McBSP3 Pin Descriptions 9 11 9 11 Available McBSP3 Signals in R 0 Mode 9 13 9 12 Available McBSP3 Signals in R 1 Mode 9 13 9 13 McBSP3 Interrupt Mapping 9 14 9 14 DMA Request Mapping ...

Page 36: ...gister INTERRUPT_CONTROL_REG 10 10 10 7 Interrupt Mask Register INTERRUPT_MASK_REG 10 10 10 8 Interrupt Status Register INTERRUPT_STATUS_REG 10 10 10 9 MPU GPIO Pin Control Register PIN_CONTROL_REG 10 11 10 10 DSP GPIO Pin Control Status Register PIN_CONTROL_STATUS_REG 10 11 11 1 Interface to LCD Panel Signal Descriptions 11 6 11 2 Bits Per Pixel Encoding for Palette Entry 0 Buffer 11 11 11 3 Colo...

Page 37: ...rol Register LCR 12 23 12 19 UART Mode Line Status Register LSR 12 24 12 20 Supplementary Status Register SSR 12 26 12 21 Modem Control Register MCR 12 26 12 22 Modem Status Register MSR 12 27 12 23 UART Mode Interrupt Enable Register IER 12 28 12 24 UART Mode Interrupt Identification Register IIR 12 29 12 25 Enhanced Feature Register EFR 12 29 12 26 EFR 0 3 Software Flow Control Options 12 30 12 ...

Page 38: ...65 Scratchpad Register SPR 12 72 12 66 Divisor Latch Low Register DLL 12 72 12 67 Divisor Latch High Register DLH 12 72 12 68 Transmission Control Register TCR 12 73 12 69 Trigger Level Register TLR 12 73 12 70 Transmit FIFO Trigger Level Setting Summary 12 74 12 71 Receive FIFO Trigger Level Setting Summary 12 74 12 72 Mode Definition 1 Register MDR1 12 75 12 73 Mode Definition Register 2 MDR2 12...

Page 39: ...lues 13 48 13 24 Transmit Endpoint Configuration Registers EP1_TX EP15_TX 13 50 13 25 Autodecoded Versus Non Autodecoded Control Requests 13 75 13 26 USB Interrupt Type by Endpoint Type 13 113 14 1 USB Host Controller Registers 14 8 14 2 OHCI Revision Number Register HcRevision 14 10 14 3 HC Operating Mode Register HcControl 14 10 14 4 HC Command and Status Register HcCommandStatus 14 13 14 5 HC I...

Page 40: ...LB Abort Data Register LB_ ABORT_DATA 14 98 14 45 LB Abort Status Register LB_ABORT_STATUS 14 99 14 46 LB IRQ Output Register LB_IRQ_OUTPUT 14 99 14 47 LB IRQ Input Register LB_IRQ_INPUT 14 100 14 48 Local Bus MMU Registers 14 102 14 49 LB MMU Walking Status Register LB_MMU_WALKING_ST_REG 14 103 14 50 LB MMU Control Register LB_MMU_CNTL_REG 14 104 14 51 LB MMU Fault Address High Register LB_MMU_FA...

Page 41: ...set Address 0x08 15 67 15 22 DSP Reset Control 2 Register DSP_RSTCT2 Offset Address 0x14 15 68 15 23 DSP System Status Register DSP_SYSST Offset Address 0x18 15 68 15 24 DPLL Control Registers 15 71 15 25 DPLL Control Register CTL_REG 15 72 15 26 ULPD Registers MPU Base Address FFFE 0800 15 73 15 27 Counter 32 LSB Register COUNTER_32_LSB_REG 15 74 15 28 Counter 32 MSB Register COUNTER_32_MSB_REG 1...

Page 42: ...omponents and features of the OMAP5910 processor and provides a high level view of the device architecture Topic Page 1 1 Overview 1 2 1 2 Description 1 4 1 3 Features 1 6 1 4 Architecture 1 8 1 5 Memory Maps 1 9 1 6 Software Compatibility 1 11 Chapter 1 ...

Page 43: ...wo key components of the OMAP5910 processor are A TI reduced instruction set computer RISC microprocessor unit MPU subsystem The MPU subsystem is based on the TI925T control proces sor peripherals and other components The TI925T processor is based on the Advanced RISC Machines ARM9TDMI technology A TI digital signal processor DSP subsystem The DSP subsystem incorporates a TI TMS320C55x DSP periphe...

Page 44: ... JTAG emulation I F OSC 12 MHz Clock OSC OMAP5910 ETM9 Timers 3 MPU DSP shared peripherals Mailbox MPU private peripherals Timers 3 16 Memory interface Reset External clock MPU Bus 32 kHz 1 5M bits traffic controller TC Watchdog timer Level 1 2 interrupt handlers Configuration registers Clock and reset management Watchdog timer Level 1 2 Private peripherals GPIO I F USB Function I F Camera I F MPU...

Page 45: ...ice is designed to run leading open and embedded RISC based operating systems as well as the Texas Instruments TI DSP BIOS software kernel foundation and is available in a 289 ball MicroStar BGA package The OMAP5910 is targeted for the following applications Applications processing devices Mobile communications J 802 11 J Bluetooth wireless technology J Proprietary government and other Video and i...

Page 46: ... Host Camera I F I2S audio codec Speakers Optical or touchscreen device Keyboard GPIO 19 Smart card Bluetooth baseband Bluetooth RF Power control I C USB plug Camera Control 32 kHz RTC 32 kHz Clock XDS 510 emulator pad Agilent TPA 301 LCD display Note For detailed information on DSP and MPU connections to peripherals see Figure 1 1 IrDA Battery 6 x 5 or 8 x 8 PWT Buzzer PWL MMC SD or memory HDQ 1 ...

Page 47: ...ement without DSP intervention DSP MMU for address translation and access permission checks System DMA controller with J Six ports and nine independently programmable generic channels J An additional dedicated DMA channel tied to the liquid crystal display LCD controller J Ability to transfer 8 16 or 32 bit data between the external memory the MPU and peripherals with byte alignment and packing ca...

Page 48: ...ring between the traffic controller and the MPU DSP controllers to facilitate fully synchronous and synchronous scalable mode clock operations JTAG port for test debug and emulation Clock management J One digital phase locked loop DPLL and three clock management units for MPU DSP and traffic controller clock generation and management J System power management for idle mode and power down functions...

Page 49: ... serial port H MCSI1 Multichannel serial voice interface H MCSI2 Multichannel serial voice interface J Shared peripherals H UART1 UART modem with autobaud 16C750 compatible H UART2 UART modem with autobaud 16C750 compatible H UART3 UART modem with IrDA 16C750 compatible H Fourteen general purpose input output GPIO H Mailbox 1 4 Architecture The OMAP5910 device includes the MPU subsystem the DSP su...

Page 50: ...vectors 0xFFFF FFFF TI peripherals and control registers DSP coprocessor interface Reserved not used for OMAP Local bus interface Internal memory interface External fast memory interface External slow memory interface cs0 cs1 cs2 cs3 0xFFFF 0000 0xF000 0000 0xE000 0000 0x8000 0000 0x3000 0000 0x2000 0000 0x1000 0000 0x0000 0000 DSP space Local bus Internal SRAM SDRAM space Flash space Reserved 0x2...

Page 51: ...y Single access random access memory External memory CE0 space External Memory CE1 space External memory CE2 space External memory CE3 space Program and data read only memory SARAM PDROM External External External External 96K bytes Byte Address Size The programmable DSP MMU configures how the DSP external address range is physically mapped to the MPU address range For more information see Section...

Page 52: ...update operations can be applied to registers that include reserved bits provided the register is initialized by writing 0 to all reserved bits when the register is first used These conventions allow use of reserved bits to enable new features in future implementations Initialization of the complete register including reserved bits is required to avoid problems in these future devices when a new d...

Page 53: ... unit MPU subsystem Topic Page 2 1 Introduction 2 2 2 2 MPU Core 2 4 2 3 Instruction Cache 2 5 2 4 Data Cache 2 6 2 5 Write Buffer 2 8 2 6 Coprocessor 15 2 10 2 7 MPU Memory Management Unit 2 26 2 8 DSP Memory Management Unit 2 47 2 9 MPU Interface 2 55 2 10 MPU TI Peripheral Bus Bridges 2 65 2 11 Endianism Conversion 2 71 2 12 ETM Environment 2 75 Chapter 2 ...

Page 54: ...see Section 2 8 DSP Memory Management Unit System DMA controller see Chapter 5 System DMA Controller LCD controller see Chapter 11 LCD Controller MPU TIPB bridge see Section 2 10 MPU TI Peripheral Bus Bridges Clock manager see Chapter 15 Clock Generation and System Reset Management Interrupt handler see Section 6 4 1 MPU Level 1 Interrupt Handler Section 6 4 2 MPU Level 2 Interrupt Handler and Sec...

Page 55: ...F JTAG emulation I F OSC 12 MHz Clock OSC OMAP5910 ETM9 Timers 3 MPU DSP shared peripherals Mailbox MPU private peripherals Timers 3 16 Memory interface Reset External clock MPU Bus 32 kHz 1 5M bits traffic controller TC Watchdog timer Level 1 2 interrupt handlers Configuration registers Clock and reset management Watchdog timer Level 1 2 Private peripherals GPIO I F USB Function I F Camera I F MP...

Page 56: ...re incorporates A coprocessor 15 CP15 and protection module Data and program memory management units MMUs with table look aside buffers A separate 16K byte instruction cache and 8K byte data cache Both are two way associative with virtual index virtual tag VIVT A 17 word write buffer WB A local bus interface The OMAP5910 device uses the TI925T core in little endian mode only To reduce effective me...

Page 57: ... and data is written to the cache following a least recently used LRU replacement algo rithm For best performance enable the I cache as soon as possible after reset If the I cache is disabled it is not searched All instruction fetches generate a single 16 bit or 32 bit external access An instruction miss generates line load 2 3 2 Validity The flush I cache instruction is fetched at cycle time 0 fo...

Page 58: ...t is searched whenever the processor performs a data load or store If the cache hits on a load data is returned to the core regardless of the C_MMU bit If a cache read misses the C_MMU bit is examined If it is 1 a line fetch is performed and the line is written to the cache following an LRU least recently used replacement algorithm If C_MMU is 0 a single external access is performed and the cache ...

Page 59: ...d so virtual addresses are always in use The TLB descriptors in memory can be cached or not cached When software is switching virtual address maps take care to invalidate the data cache so that the wrong data value is not returned that is so that a false D cache hit does not occur To do this the CP15 register allows software to invalidate the entire D cache As noted before disabling the D cache an...

Page 60: ...t be marked as uncacheable 2 5 Write Buffer The write buffer WB increases system performance and can buffer up to seventeen 32 bit words of data The MMU attributes B B_MMU and C C_MMU which are part of the TLB descriptor and the CP15 control register W bit W_CP15 control WB behavior Clearing W_CP15 and C_CP15 upon reset ensures that all accesses are non bufferable until the MMU is enabled To use t...

Page 61: ...rnal write access is complete 2 5 2 SWAP Instruction When bit L of the CP15 TI925T configuration register is set the write phase of the SWAP instruction interlocked read write is treated as unbuffered when data belongs to an noncacheable nonbuffered NCNB or NCB region even if it is marked as buffered The S_LOCK signal is active through the read and write accesses If the read of the SWAP instructio...

Page 62: ... of the MCR and MRC instructions Figure 2 2 MRC MCR Bit Pattern 31 28 27 24 23 22 21 20 19 18 17 16 Cond 1110 Opcode_1 L Crn 15 12 11 8 7 5 4 3 0 Rd 1111 Opcode_2 1 CRm The CRn field specifies the coprocessor register to access The CRm field and opcode_2 fields specify a particular action when addressing some registers or shadow registers The TI925T takes the undefined instruction trap upon execut...

Page 63: ...ss control Domain access control Read Write 31 0 4 Unpredictable Ignored 5 Fault status Fault status Read Write 8 0 6 Fault address Fault address Read Write 31 0 7 Unpredictable Cache operations Write only 31 0 8 Unpredictable TLB operations Write only 31 0 9 Unpredictable Ignored 10 TLB lock down TLB lock down Read Write 31 0 11 Unpredictable Ignored 12 Unpredictable Ignored 13 PID PID Read Write...

Page 64: ...on register sets the value of these fields as follows 915 in TI925T mode 925 in Windows CE mode 3 0 Reserved Contains the microprocessor revision number 2 Table 2 6 CP15 Cache Information Register CIR Bit Name Value Function 31 29 Reserved 0 Read as 0 28 25 Cache type Cache type read as 0010 The cache provides clean cache entry and flush cache entry with a cache index in addition of the operations...

Page 65: ...es that D cache is really direct map 13 12 D cache information Indicate line length of D cache same format as for I cache 11 9 Reserved 0 Read as 0 8 6 I cache information Base value of I cache size 0000 512 bytes 0001 1K byte 0010 2K bytes 0011 4K bytes 0100 8K bytes 0101 16K bytes 0110 32K bytes 0111 64K bytes Note 2 bits 8 6 bits 5 3 bits 1 0 gives the number of lines 5 3 I cache information Ba...

Page 66: ... be written using a read modify write routine Reading from CP15 register 1 reads the control bits The CRm and opcode_2 fields are ignored when reading CP15 register 1 but must be zero Writing to CP15 register 1 sets the control bits The CRm and opcode_2 fields are not used when writing CP15 register 1 but must be zero All control bits but V are set to zero upon reset Table 2 7 CP15 Control Registe...

Page 67: ...25T on the OMAP5910 device supports only little endian mode due to the system architecture of the device This bit must always be written as 0 0 Little endian 1 Reserved do not use 6 4 1 Read as 1 Write is ignored 3 W Write buffer enable disable 2 C Data cache enable disable 0 Data cache disabled 1 Data cache enabled 1 A Alignment fault enable disable 0 Address alignment fault checking disabled 1 A...

Page 68: ... instruction with delayed execution A similar situation occurs when the MMU is disabled The following code segment example shows correct MMU enabling which takes into account the latency to transition to virtual addressing ldr r0 bVirtualStart Load r0 with virtual jump location Enable the MMU mrc p15 0 r1 c1 c0 0 Read the control register orr r1 r1 BIT0 Set the M bit to enable MMU nop mcr p15 0 r1...

Page 69: ...Figure 2 4 Format of the CP15 Domain Access Control Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 D15 D14 D13 D12 D11 D10 D9 D8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Reading from CP15 register 3 returns the value of the domain access control register The CRm and opcode_2 fields are SBZ when reading this register Writing to CP15 register 3 writes the value of the ...

Page 70: ...s as zero 8 0 Read as 0 7 4 Domain Specify which of the 16 domains D15 D0 was being accessed when the last fault occurred 3 0 Status Indicate the type of fault due to the last access being attempted The encoding of these bits is shown in Table 2 23 Priority Encoding of the Fault Status Register The FSR is only updated for data access faults not for instruction fetch faults When a fault occurs duri...

Page 71: ... cache 0b000 0b0111 SBZ MCR p15 0 Rd c7 c7 0 Flush I cache 1 0b000 0b0101 SBZ MCR p15 0 Rd c7 c5 0 Flush I cache entry 0b001 0b0101 VA MCR p15 0 Rd c7 c5 1 Flush D cache 1 2 0b000 0b0110 SBZ MCR p15 0 Rd c7 c6 0 Flush D cache entry 2 0b001 0b0110 VA MCR p15 0 Rd c7 c6 1 Clean D cache entry 0b001 0b1010 VA MCR p15 0 Rd c7 c10 1 Clean and flush D cache entry 0b001 0b1110 VA MCR p15 0 Rd c7 c14 1 Flu...

Page 72: ...lush the entire cache this requires two CP15 operations bear in mind the VIVT clean algorithm You can clean and flush individual entries in one CP15 operation 3 Figure 2 6 shows the format of the Rd value for all D cache operations on a single entry 4 TI925T supports high performance full cache clean operation with the VIVT algorithm Figure 2 6 D Cache Clean Flush Single Entry Operand Format 31 X ...

Page 73: ...b0101 SBZ MCR p15 0 Rd c8 c5 0 Flush I TLB entry 0b001 0b0101 VA MCR p15 0 Rd c8 c5 1 Flush D TLB 0b000 0b0110 SBZ MCR p15 0 Rd c8 c6 0 Flush D TLB 0b001 0b0110 VA VA MCR p15 0 Rd c8 c6 1 Flush I D TLB 0b000 0b0111 SBZ MCR p15 0 Rd c8 c7 0 2 6 2 4 TLB Lock Down Registers There is a TLB lock down register for both TLBs the value of opcode_2 deter mines which TLB register is accessed Opcode_2 0 sele...

Page 74: ...e TLB if loaded between the entry 0 and the entry pointed to by the base value register Flush operations invalidate both locked and non locked entries An entry can also be maintained in the TLB during a global flush if the preserved bit was set during the loading of this entry in the TLB A flush entry operation invalidates a TLB entry regardless of its state preserved unpreserved The flush operati...

Page 75: ...ead TI925T configuration 0b000 0b0001 Value MRC p15 0 Rd c15 c1 0 Read I_max 0b000 0b0010 Value MRC p15 0 Rd c15 c2 0 Set I_max 0b000 0b0010 Value MCR p15 0 Rd c15 c2 0 Read I_min 0b000 0b0011 Value MRC p15 0 Rd c15 c3 0 Set I_min 0b000 0b0011 Value MCR p15 0 Rd c15 c3 0 Read thread ID 0b000 0b0100 Value MRC p15 0 Rd c15 c4 0 Set thread ID 0b000 0b0100 Value MCR p15 0 Rd c15 c4 0 TI925T_status 0b0...

Page 76: ... 1 D 31 selects the set targeted by the clean operation 1 T Transparent mode 0 Line loads follow line copy backs adding some additional latency This is the default state after reset 1 When TI925T is connected to a 16 bit external memory line loads can hide line copy backs There is no extra latency If the external memory is 32 bits wide setting this bit to 1 generates an error during copy back 0 L ...

Page 77: ...Name Function 31 dcache_dirty When at 1 indicates the data cache may contain lines marked as dirty 4 S_abort When at 1 indicates that external abort occurred This bit is set to zero upon reset and when read by TI925T 3 dtlb_mode When at 1 indicates that DTLB counter is in random mode Default is set to sequential mode This bit is set to zero upon reset 2 Itlb_mode When at 1 indicates that ITLB coun...

Page 78: ...ages consist of 1K byte blocks of memory Sections and large pages are supported to allow mapping of large regions of memory while using only a single entry in the TLB 2 7 1 Translation Look Aside Buffer The TLB contains entries for virtual to physical address translation and ac cess permission checking If the TLB contains a translated entry for the virtual address the access control logic determin...

Page 79: ...oarse tables The second level tables can hold large small and tiny page translations entries 2 7 3 Domains and Access Permissions The MMU also supports domains Domains are areas of memory that can be defined to have individual access rights The CP15 domain access control reg ister can specify access rights for up to 16 separate domains This register is shared by the instruction access permission l...

Page 80: ...ause and address of the abort see Section 2 6 Coprocessor 15 for more details on CP15 2 7 5 Address Translation Translation information which consists of both the address translation data and the access permission data resides in a translation table located in physi cal memory The MMU provides the logic needed to traverse this translation table obtain the translated address and check the access pe...

Page 81: ...to the TLB Figure 2 10 Address Translation Process Virtual address Page domain fault No access D0 Reserved 10 Section domain fault Alignment fault Misaligned Page translation fault Invalid Section transistor fault Section Get level 1 descriptor Page Check address alignment Invalid Manager 0 1 Client 0 1 Check domain status Check access permissions Violation Section permission fault Physical addres...

Page 82: ...r points to the base of a table in physical memory which contains section and page table descriptors The 14 LSBs of the TTB register are always set to zero so the table must start on a 16K byte boundary Figure 2 11 Translation Table Base Register 31 16 Translation Table Base TTB 15 14 13 0 Translation Table Base The translation table has up to 4096 32 bit entries each describing 1M byte of virtual...

Page 83: ...tion table level 1 descriptors see Section 2 7 6 3 This address selects a four byte translation table entry which is a level 1 descriptor for either a section or a page table Figure 2 12 Accessing the Translation Table Level 1 Descriptors 31 20 19 18 12 14 13 2 1 0 0 0 Virtual Address Table index Section index Translation base Translation table base First level descriptor Table index Translation b...

Page 84: ...FINE_PG_BASE Base address used to access the fine page table entry The fine page table index selecting an entry is derived from the virtual address as illustrated in Figure 2 16 Tiny Page Translation 11 9 RESERVED Reserved Must be written as 0 8 5 DOMAIN Specify which one of the sixteen domains held in the domain access control register contains the primary access controls 4 RESERVED Reserved Must...

Page 85: ... 3 2 RESERVED Reserved Must be written as 0 1 0 RESERVED Reserved Must be written as 1 Table 2 20 Level 1 Section Descriptor Bit Name Function 31 20 SECTION_BASE The 12 MSBs of the address of the section in physical memory section base address 19 12 Reserved Must always be written to as 0 11 10 AP Specify the access permissions for this section see Table 2 24 9 Reserved Must always be written to a...

Page 86: ...d before the physical address is put on the address bus Figure 2 14 Section Translation 31 20 19 18 12 14 13 2 1 0 0 0 Virtual address Table index Section index Translation base Translation table base First level descriptor Table index Translation base 31 31 31 0 0 0 14 13 Physical address Section index AP C B Domain 1 1 0 Section base address Section base address 12 31 0 9 8 5 4 3 2 1 20 19 12 11...

Page 87: ...es have 1024 entries and each entry describes 1K byte These entries provide a base address for tiny small or large pages Small page descriptors must be repeated in four consecutive entries Large page descrip tors must be repeated in 64 consecutive entries The two least significant bits indicate the page size and validity and are interpreted as follows Table 2 21 Level 2 Section Descriptor Bit Name...

Page 88: ...7 6 6 Translating Tiny Pages References Figure 2 16 illustrates the complete translation sequence for a 1K byte tiny page Page translation involves one additional step beyond that of a section translation the level 1 descriptor is the page table descriptor and is used to point to the level 2 descriptor or page table entry For pages the access per missions are contained in the level 2 descriptor an...

Page 89: ...Translation table index First level descriptor Table index Translation base 31 31 31 0 0 0 14 13 L2 table index C B Domain 1 1 1 Fine page table base address Page table base address 31 0 9 8 5 4 2 1 12 12 11 Page base address 31 0 Page index Page base address 31 0 10 10 10 9 Page index 1 1 2 1 0 12 1110 1 2 3 4 5 6 7 8 9 ap Second level descriptor Physical address 10 9 0 ...

Page 90: ...ies must be used for a small page in a fine page table Figure 2 17 Small Page Translation 31 20 19 18 12 14 13 2 1 0 0 0 Virtual address Table index L2 table index Translation base Translation table index First level descriptor Table index Translation base 31 31 31 0 0 0 14 13 L2 table index C B Domain 1 1 0 Page table base address Page table base address 31 0 9 8 5 4 2 1 10 10 9 Page base address...

Page 91: ...ects the conditions that pro duce these faults If a fault is detected as the result of a memory access the MMU aborts the access and signals the fault condition to the MPU The MMU is also capable of retaining the type and address information of the abort The MPU recognizes two types of aborts data and prefetch aborts The MMU has no FAR or FSR registers The MMU detects access violations before star...

Page 92: ...e base First level descriptor Table index Translation base 31 31 31 0 0 0 14 13 L2 table index C B Domain 1 1 0 Page table base address Page table base address 31 0 9 8 5 4 2 1 10 10 9 Page base address 31 0 Page index Page base address 31 0 8 16 12 11 Page index 1 0 2 1 0 12 1110 1 2 3 4 5 6 7 8 9 ap0 Second level descriptor Physical address 16 15 0 ap1 ap2 ap3 16 15 16 15 ...

Page 93: ... of the Fault Status Register Source Priority Domain 3 0 FAR Highest priority Alignment 0b0001 Invalid VA of access causing abort External abort on transaction First level 0b1100 Invalid VA of access causing abort Second level 0b1110 Valid Transaction Section 0b0101 Invalid VA of access causing abort Page 0b0111 Valid Domain Section 0b1001 Valid VA of access causing abort Page 0b1011 Valid Permiss...

Page 94: ...en 2 bit domains Figure 2 19 Domain Access Control Register Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Table 2 24 defines how the bits within each domain are interpreted to specify the access permissions Table 2 24 Interpreting Access Bits in Domain Access Control Register Value Access Type Description 0b00 No ...

Page 95: ...0 No access No access Generates a permission fault 01 00 1 0 Read only No access Supervisor read only permitted 01 00 0 1 Read only Read only Any write generates a permission fault 01 00 1 1 Reserved Reserved Generates a permission fault 01 01 x x Read write No access Access allowed only in supervisor mode 01 10 x x Read write Read only User writes cause a permission fault 01 11 x x Read write Rea...

Page 96: ... Section permission fault Physical address No access D0 Reserved 10 Section Page Client 0 1 Violation Subpage permission fault Check access permissions Get page table entry 2 7 11 1 Alignment Fault If an alignment fault is enabled bit 1 in CP15 control register 1 the MMU gen erates an alignment fault upon 16 bit and 32 bit data accesses that are improperly aligned not on an address multiple of 2 a...

Page 97: ... This happens if bits 1 0 of the descriptor are both 0 A page translation fault is generated if the page table entry is marked as invalid This happens if bits 1 0 of the page table entry are both 0 2 7 11 3 Domain Fault There are two types of domain faults section and page In both cases the level 1 descriptor holds the 4 bit domain field that selects one of the sixteen 2 bit domains in the domain ...

Page 98: ...ith great care This section describes the restrictions The accesses listed below can be aborted and restarted safely In the case of an interlocked read write SWAP instruction in which the read aborts the write does not happen Reads Unbuffered writes Level 1 descriptor fetch Level 2 descriptor fetch Interlocked read write SWAP Cacheable reads line fetches A cache line fetch can be safely aborted on...

Page 99: ...In general the MMU is initialized at boot time but it also can be reprogrammed dynamically The MMU is programmed through the TI peripheral bus registers The DSP MMU registers are listed in Table 2 26 and detailed in this section Table 2 26 DSP Memory Management Unit Registers Name Description R W Size Address Reset Value PREFETCH_REG Prefetch register R W 16 bits FFFE D200 0x0000 WALKING_ST_REG Pr...

Page 100: ...H_REG Read RAM MSB R W 16 bits FFFE D24C 0x0000 READ_RAM_L_REG Read RAM LSB R W 16 bits FFFE D250 0x0000 Table 2 27 Prefetch Register PREFETCH_REG Offset Address hex 00 Bit Function Size Access Value at Hardware Reset 15 Reserved 1 14 The data to prefetch is data when 1 program when 0 1 R W 0 13 0 MSB of virtual address tag of the TLB entry to be prefetched 14 R W 0 Table 2 28 Prefetch Status Regi...

Page 101: ... Enables MMU Active high 1 R 0 0 Resets module Active low 1 R 0 Table 2 30 Fault Address Register MSB FAULT_AD_H_REG Offset Address hex 0C Bit Function Size Access Value at Hardware Reset 15 9 Reserved 7 8 The access that generated a permission fault is data when 1 or program when 0 1 R 0 7 0 MSB of virtual address of the access that generated a permission fault 8 R 0 Table 2 31 Fault Address Regi...

Page 102: ...3 IT Acknowledge Register IT_ACK_REG Offset Address hex 18 Bit Function Size Access Value at Hardware Reset 15 1 Reserved 15 0 Write a 1 to this bit to acknowledge the interrupt A write of 0 has no effect a write of 1 clears the bit automatically 1 W 0 Table 2 34 TTB Register MSB TTB_H_REG Offset Address hex 1C Bit Function Size Access Value at Hardware Reset 15 0 MSB of TTB 16 R 0 Table 2 35 TTB ...

Page 103: ...Access Value at Hardware Reset 15 2 Reserved 14 1 Read data in TLB when 1 1 R W 0 0 Load data in TLB when 1 1 R W 0 Table 2 38 CAM Entry Register MSB CAM_H_REG Offset Address hex 2C Bit Function Size Access Value at Hardware Reset 15 6 Reserved 10 5 0 Table index level 1 MSB 6 R W 0 Table 2 39 CAM Entry Register LSB CAM_L_REG Offset Address hex 30 Bit Value Function Size Access Value at Hardware R...

Page 104: ... not valid 1 CAM entry valid 1 0 00 Section 1 MB 2 R W 0 01 Large pages 64 KB 10 Small pages 4 KB 11 Tiny page 1 KB Table 2 40 RAM Entry Register MSB RAM_H_REG Offset Address hex 34 Bit Function Size Access Value at Hardware Reset 15 0 MSB physical address 16 R W 0 Table 2 41 RAM Entry Register LSB RAM_L_REG Offset Address hex 38 Bit Function Size Access Value at Hardware Reset 15 10 LSB physical ...

Page 105: ...40 Bit Function Size Access Value at Hardware Reset 15 1 Reserved 15 0 Toggle bit Active high Always 0 when read 1 R W 0 Table 2 44 CAM Entry Register MSB READ_CAM_H_REG Offset Address hex 44 Bit Function Size Access Value at Hardware Reset 15 10 Reserved 6 9 0 Table index level 1 MSB 10 R W 0 Table 2 45 CAM Entry Register LSB CAM_CAM_L_REG Offset Address hex 48 Bit Value Function Size Access Valu...

Page 106: ...t valid 1 CAM entry valid 1 0 00 Section 1 MB 2 R W 0 01 Large pages 64 KB 10 Small pages 4 KB 11 Tiny page 1 KB Table 2 46 RAM Entry Register MSB READ_RAM_H_REG Offset Address hex 4C Bit Function Size Access Value at Hardware Reset 15 0 MSB physical address 16 R W 0 Table 2 47 RAM Entry Register LSB READ_RAM_L_REG Offset Address hex 50 Bit Function Size Access Value at Hardware Reset 15 10 LSB ph...

Page 107: ...the DSP and the DSP peripheral buses except the private peripherals Thus the TI925T and the system DMA controller have both read and write access to the complete DSP I O space 128K bytes including the control registers of the internal DSP peripherals such as the DSP TIPB bridge itself Figure 2 22 MPUI Simplified Block Diagram MPU bus interface System DMA controller interface API port Arbiter progr...

Page 108: ...ode HOM the MPUI interface does not have access to the DARAM 0x00 0000 to 0x00 FFFF All SARAM 0x01 0000 to 0x04 FFFF is accessible by the MPUI but the type of access depends on the DSP status HOM or single access mode SAM and on the MPUI size register DSP_API_CONFIG The following rules apply Before the MPU reset resetting the DSP MPUI logic is released the MPUI cannot access any SARAM After the MP...

Page 109: ...re not supported MPU and system DMA should access all traffic controller resources EMIFS EMIFF and IMIF directly through the traffic controller and not via the MPUI port and DSP MMU 2 9 2 MPUI Registers Table 2 48 lists the MPUI registers Table 2 49 through Table 2 56 describe the register bits Table 2 48 MPUI Registers Register Name Description R W Size Address FFFE x Reset Value CTRL_REG Control...

Page 110: ...10 device and can be disregarde Note the lower the number the higher the priority 3 R W 000 000 MPU 1 DMA 2 reserved port 3 001 MPU 1 DMA 3 reserved port 2 010 MPU 2 DMA 1 reserved port 3 011 MPU 2 DMA 3 reserved port 1 1X0 MPU 3 DMA 1 reserved port 2 1X1 MPU 3 DMA 2 reserved port 1 17 16 Control byte swap on the MPUI DSP interface 2 R W 11 00 Turn off byte swap for all accesses 01 Byte swap only ...

Page 111: ...rt from the DSP This can be masked by setting CTRL_REG 3 to 0 2 Time out event occurred This can be masked by setting CTRL_REG 1 to 0 But masking the time out interrupt can cause system to wait forever if DSP never responds to the MPU request 3 Burst access detected This cannot be masked These interrupt sources are assigned to the IRQ_ABORT line of the level 1 MPU interrupt handler The DEBUG_FLAG ...

Page 112: ...ved 3 12 11 Encoded access mode for MPUI 2 R 00 00 SAM_M and SAM_R 01 SAM_M and HOM_R 10 HOM_M and SAM_R 11 HOM_M and HOM_R 10 9 Chip select Saved on abort These bits indicate wheth er memory space or TIPB space was accessed just before the abort was generated 2 R 00 01 Memory access 10 Peripheral bus or MPUI control register access 8 7 Burst size saved on abort 3 R 000 6 Read not write on MPUI bu...

Page 113: ...ring suspend mode for example after hitting an emulator breakpoint The register is for OMAP5910 device chip designers to use for debugging Table 2 53 Status Register STATUS_REG Offset x10 Bit Value Function Size Access Value at Hardware Reset 12 11 Current access in progress is 2 R 11 00 MPU access 01 DMA access 10 Reserved port access should not occur 11 No access 10 3 Current value of time out c...

Page 114: ...SP_STATUS_REG Offset x14 Bit Value Function Size Access Value at Hardware Reset 11 HOM or SAM for accessing DSP peripherals from DSP 1 R 1 0 SAM 1 HOM 10 HOM or SAM for accessing MPUI peripherals from DSP 1 R 1 0 SAM 1 HOM 9 Asynchronous reset controlled by emulation 1 R 1 8 Idle peripherals 1 R 1 0 Functional mode 1 Idle Linked to bit 7 of the ISTR register from DSP 7 Idle peripherals 1 R 1 0 Fun...

Page 115: ...SP which is the CPUAVIS bit 1 R 1 2 XF is a signal from the C55x DSP core On standard DSP devices such as the TMS320C5510 XF is con nected to a pin and used as an external flag The OMAP5910 device does not have an XF pin so this bit is provided to show tha value of the XF bit in the DSP core status register ST3 1 R 1 1 Reset signal from MPU to DSP 1 R 1 0 Master reset active low 1 R 1 Table 2 55 D...

Page 116: ...0 through SARAM 11 on 8K boundaries Table 2 57 Decoding SARAM 0 Through SARAM 11 on 8K Boundaries SARAM APISIZE 15 0 11 7 3 0 0X0000 0X0001 0000 0000 0000 0X0002 0X0003 0000 0000 0001 0X0004 0X0005 0000 0000 0011 0X0006 0X0007 0000 0000 0111 0X0008 0X0009 0000 0000 1111 0X000A 0X000B 0000 0001 1111 0X000C 0X000D 0000 0011 1111 0X000E 0X000F 0000 0111 1111 0X0010 0X0011 0000 1111 1111 0X0012 0X0013...

Page 117: ...nected on the private periph eral bus for low latency access by an operating system and the camera is located on the public peripheral bus for access by the DMA The private and public peripheral bridges are compatible with the TIPB specification Figure 2 23 MPU TI Peripheral Bus Bridge Connections System DMA controller MPU TI bridge private bridge shared Logic Mux Logic TI peripheral bus Private T...

Page 118: ...te TIPB strobe 1 and 0 are derived from the traffic controller clock CLKM3 For both TIPBs you can use bits 3 0 strobe 0 and bits 7 4 strobe 1 of the TIPB control register TIPB_CNTL to configure the access factor and consequently the strobe frequencies as shown in Table 2 58 Table 2 58 Access Factor Number of Wait States Access Factor Strobe Frequency 0 TC Clk 1 1 TC Clk 2 2 TC Clk 3 3 TC Clk 4 15 ...

Page 119: ... any TI peripheral access has a size mismatch In case of abort or size mismatch the address and data of the corresponding access are saved in the following registers ADDRESS_DBG DATA_DEBUG_LOW DATA_DEBUG_HIGH DEBUG_CNTR_SIG 2 10 7 TIPB Bridge Registers Table 2 59 and Table 2 60 list the TIPB bridge registers Table 2 61 through Table 2 68 describe the register bits Table 2 59 TIPB Private Bridge Re...

Page 120: ...0xFFFF DEBUG_CNTR_SIG Debug control signals R 8 bits FFFE D31C 0xF8 Table 2 61 TIPB Control Register TIPB_CNTL Offset x00 Bit Description Size Access Reset Value 15 8 TIPB bus access time out 8 R W 0xFF 7 4 Division factor of nASTROBE 1 4 R W 0x1 3 0 Division factor of nASTROBE 0 4 R W 0x1 Table 2 62 TIPB Bus Allocation Register TIPB_BUS_ALLOC Offset x04 Bit Value Description Size Access Reset Val...

Page 121: ...when MPU TIPB access is timed out 1 R W 1 2 When high incoming signals from MPU and DMA are clocked Used when running at high frequency 1 R W 1 1 When low an interrupt is sent to the MPU when a TIPB write access is aborted or when any TIPB access has a size mismatch When high the interrupt is masked 1 R W 1 0 A value of 1 enables the time out feature 1 R W 1 Table 2 65 Address Debug Register ADDRE...

Page 122: ...Signals Register DEBUG_CNTR_SIG Offset x1C Bit Description Size Access Reset Value 8 Burst access 1 R 0 7 6 Peripheral memory access size on TIPB 1 R 3 5 4 Memory access size on TIPB 1 R 3 3 Not supervisor mode on TIPB 1 R 1 2 Read not write on TIPB 1 R 0 1 Flag set to 1 when there is a mismatch between memory access size and peripheral memory access size 1 R 0 0 Flag set to 1 when TIPB access is ...

Page 123: ... program code and data from big endian to little endian mode when writing to the system memory and from little endian to big endian mode when reading back from the system memory for all the data access sizes when the logic is enabled Endianism conversion is performed in hardware so that the data swapping is transparent to software reduce software overhead to format the data A bypass path is also i...

Page 124: ...ord is written from the DSP to the system memory but beginning at an odd address for example 0x000002 or with the bit byte_nword set to 0 In the DSP the data is organized in DSP data format see Table 2 71 but the 16 bit words are swapped in order to reorganize the 32 bit data in little endian mode 32 bit word is read from the system memory to the DSP but beginning at an odd address for example 0x0...

Page 125: ...ian Conversion 32 Bit Aligned Data DSP big endian Byte 3 Byte 2 Byte 1 Byte 0 Byte 0 Byte 1 Byte 2 Byte 3 Traffic controller little endian Flash little endian SDRAM little Internal SRAM little endian EMIF EMIF Packing and unpacking controls EMIF Controls DSP write swapping buffers DSP read swapping buffers DSP endian conversion for 32 bit aligned data Controls Controls Bytes steering logic write B...

Page 126: ...s Control DSP endian conversion MPUI boundary Controls MPUI port Byte 0 Byte 1 Byte 1 Byte 0 API write swapping buffers API read swapping buffers Bytes steering logic write Bytes steering logic read 16 System DMA controller little endian System DMA bus Big endian Little endian peripheral bus Note The steering logic puts the byte word double word in appropriate formats The MPUI port has a 16 bit da...

Page 127: ... logical signal interface contains 13 trace interface pins and nine JTAG interface pins The ETM trace interface has the following signals TRACEPKT 0 7 The TRACEPKT signals comprise the 8 bit data trace packets packaged address and data information PIPESTAT 0 2 The PIPESTAT signals are used to output the MPU pipeline at the MPU execute stage on every TRACECLK and are used by software to reconstruct...

Page 128: ...nterface Refer to Section 6 8 Configuration Module and Section A 2 I O Functional Multiplexing for details on pin multiplexing Figure 2 26 Trace Signals Multiplexing Camera interface ETM 9 MPU Agilent E5903A 301 TPA or 16700A series logic analyzer With E959A 002 TPA trace _pipestat_ 2 0 trace _pkt_ 7 0 trace _sync trace _clk OMAP5910 Pin multiplexing logic ...

Page 129: ...vides two types of trace port equipment Dedicated trace port analyzer TPA E5903A 301 A 16700A series logic analyzer used with an analysis probe E9595A 002 The Code Composer Studio IDE provides support only for the TPA setup The Code Composer Studio IDE provides a complete interface to the ETM including the setup of the trace registers trigger points and sequencing of trace operations When a trace ...

Page 130: ...rest include ETM9 Rev 0 0a Technical Reference Manual ARM DDI 0157B Trace Port Analysis for ARM ETM Users Guide Agilent Publications publication number E5903 97000 Embedded Trace Macrocell Rev 1 Specification ARM IHI 0014E Documentation is also available from Advanced RISC Machines directly via http www arm com ...

Page 131: ...e 3 1 Architecture Overview 3 2 3 2 TMS320C55x DSP CPU Overview 3 6 3 3 DSP Memory 3 9 3 4 DMA Controller 3 16 3 5 TIPB Bridge 3 27 3 6 MPU Interface 3 33 3 7 EMIF 3 36 3 8 DSP Memory Management Unit 3 37 3 9 DSP Subsystem Clocking and Reset Control 3 38 3 10 System Operating Details 3 39 Chapter 3 ...

Page 132: ...RAM Memories Flash and SRAM Memories DSP MMU 16 16 32 16 32 32 32 32 32 32 16 MPU Private Peripheral Bus DSP Public Shared Peripheral Bus 32 MPU Public 16 DSP DSP Public Peripherals McBSP1 McBSP3 MPU Public Peripherals USB Host I F JTAG Emulation I F OSC 12 MHz Clock OSC OMAP5910 ETM9 Timers 3 MPU DSP Shared Peripherals Mailbox MPU Private Peripherals Timers 3 16 Memory Interface Reset External Cl...

Page 133: ...er DSPTM_CK 1 INT WD Timer DSPWD_CK 1 INT Interrupt handler DSP_INTH_CK Interrupt I F DSP_INTH_CK GPIO I F 1 INT to MPU and or DSP MPU_GPIO_CK Mailbox UART1 2 3 MPU DSP shared peripherals MPUI MPU public TIPB bridge MPU MPU subsystem DSP private peripheral bus DSP public peripheral bus MPU public peripheral bus 16 16 McBSP1 Audio PCM I2S via McBSP DSPXOR_CK 2 INT 2DMA DSP public peripherals McBSP3...

Page 134: ...at connects the CPU to external and loosely coupled memories J A 6 channel DMA controller that can copy memory contents from one address to another without CPU intervention J MPUI that permits high bandwidth parallel access to DSP resources by the MPU and system DMA J TIPB bridge that provides two external bus interfaces for private and public peripherals DSP subsystem peripherals J Three general ...

Page 135: ...IPB bridge EMIF DSP CPU core plus hardware accelerator DCT IDCT motion estimation half pixel interpolation DMA controller 6 channels 5 ports Feedback test logic Trace FIFO Shared T I P B bridge M P U I M I F C D E F DMA I Cache SARAM 96K bytes DARAM 64K bytes Instruction cache 3x8K bytes PDROM 32K bytes P B C D E F DMA P B C D E F DMA P P B C D ...

Page 136: ...16M bytes total addressable memory space Single instruction repeat or block repeat operations for program code Conditional execution Seven stage pipeline for high instruction throughput Instruction buffer unit that loads parses queues and decodes instruc tions to decouple the program fetch function from the pipeline Program flow unit that coordinates program actions among multiple parallel CPU fun...

Page 137: ...le the program fetch function from the pipeline The program flow unit PU coordinates program actions among multiple parallel CPU functional units The address data flow unit AU provides data address generation and in cludes a 16 bit arithmetic unit capable of performing arithmetic logical shift and saturation operations The data computation unit DU contains the primary computation units of the CPU ...

Page 138: ...a registers 0 3 Coefficient data pointer AC0 AC1 AC2 AC3 MAC MAC 40 bit ALU Shifter Transition registers Bit operations Smemory Xmemory Ymemory Cmemory ALU 16 bit Program address bus PAB 24 Data read address buses BAB CAB DAB 3 x 24 Data read address buses bb cb db 3 x 16 Data write buses EB FB 2 x 16 For details on CPU architecture and instruction set see the following documents TMS320C55x Techni...

Page 139: ...perands from memory or write up to 32 bits to memory To achieve maximum performance from the architecture the programmer must pay close attention to placement of code and data struc tures within the on chip memory resources For more details see TMS320C55x DSP Programmers Guide SPRU376 Chapters 3 and 4 Loosely coupled memory devices can be accessed via the traffic controller module This flexible me...

Page 140: ...ernal data program or DMA bus The DARAM memory consists of 8 blocks of 8K bytes each The SARAM 96K bytes can support one memory access in one CPU clock cycle into each RAM block This access can be a 32 bit value Ac cesses can be made from any internal data program or DMA bus The SARAM memory consists of 32 blocks of 8K bytes each The PDROM 32K bytes can support one memory read in one CPU clock cyc...

Page 141: ...for cache access i e a branch not taken is always assumed With this feature no branch continuous fetches are no wait state operations The instruction cache returns one 32 bit word for each fetch Fetches are always aligned on a 32 bit boundary When a cache miss occurs wait states are inserted that are dependent upon the external memory access time The I cache retrieves instructions from ex ternal m...

Page 142: ... External memory space ranges from 0x50000 to 0xFF8000 if the internal PDROM is enabled or to 0xFFFFFF if the PDROM is not enabled To access memory external to the DSP subsystem the EMIF issues a memory access request The access request is passed through the DSP memory man agement unit MMU which if enabled and configured by the MPU translates the DSP virtual address into a physical address that is...

Page 143: ...Timer CLKM2 L2 Int handler 00000 00800 01000 01800 02000 02800 03000 03800 04000 04800 05000 05800 06000 06800 07000 07800 08000 08800 09000 09800 0A000 0A800 0B000 0B800 0C000 0C800 0D000 0D800 0E000 0E800 0F000 0F800 10000 10800 11000 11800 12000 I O Space 00800 00400 00000 00C00 01000 01400 01800 00C00 02000 02800 02400 02C00 03000 03400 03800 03C00 04000 04800 04400 04C00 05000 05400 05800 05C...

Page 144: ...ffered serial ports McBSPs for synchronous serial communications J Two multichannel serial interfaces MCSIs Configuration and data registers for all peripherals reside in the DSP subsys tem I O space which consists of 64K word addresses with each peripheral mapping into a 1K word section of I O memory To read or write these regis ters you must access the DSP I O space either through C language con...

Page 145: ...od x008000 CLKM 2 04000 Strobe 1 x009000 Level 2 interrupt handler 04800 Fixed strobe period x0010000 UART1 08000 Strobe2 x0010800 UART2 08400 Strobe2 x0011800 McBSP1 08c00 Strobe2 x0012000 MCSI2 09000 Strobe2 x0012800 MCSI1 09400 Strobe2 x0017000 McBSP3 0B800 Strobe2 x019800 UART3 0CC00 Strobe2 x01C800 UART1 2 3 sharing switch 0E400 Strobe2 x001E000 GPIO 0F000 Strobe2 x001F000 Mailbox 0F800 Strob...

Page 146: ...able certain transfers between the MPUI and memory Six logical channels which allow the DMA controller to keep track of the context of six independent block transfers plus a seventh logical channel for MPUI transfers Bits for assigning each channel a low priority or a high priority Event synchronization DMA transfers in each channel can be made dependent on the occurrence of selected events An int...

Page 147: ...affic controller DSP MMU On chip SARAM ROM SRAM Flash SBFlash SDRAM DSP private peripheral bus DSP public peripheral bus MPU public peripheral bus 16 16 MPUI MPU MPU subsystem MPU System DMA MPU public TIPB bridge GPIO I F 1 INT to MPU and or DSP MPU_GPIO_CK Mailbox UART1 2 3 MPU DSP shared peripherals McBSP1 audio PCM I2S via McBSP DSPXOR_CK 2 INT 2DMA DSP public peripherals McBSP3 optical McBSP ...

Page 148: ...grammable service chain that is used by each of the standard ports The complete operation of the OMAP5910 DSP DMA controller is described in detail in the Direct Memory Access DMA Controller section of the TMS320C55x Peripherals Reference Guide literature number SPRU317 The OMAP5910 DSP DMA controller is consistent with SPRU317 with the following exceptions and clarifications All references to EHP...

Page 149: ...M A R P B C D E F D M A R P B C D E F D M A R P B C D E F D M A R IOD IOE D M A R D M A W D M A W D M A W D M A W D M A W M 1 M 6 5 4 3 2 1 M 6 5 4 3 2 1 M 6 5 4 3 2 Channel 1 FIFO Channel 2 FIFO Channel 3 FIFO Channel 4 FIFO Channel 5 FIFO Channel 6 FIFO Example DMA configuration Ch1 Not active Ch2 Peripheral SARAM Ch3 Not active Ch4 SARAM Peripheral Ch5 Not active Ch6 SARAM DARAM MPUI Ch MPUI EM...

Page 150: ...O writes to the peripheral port do not begin until the synchronization event is detected When the channel is operating in frame synchronization mode DMA_CCR_FS 1 several prereads may occur to the point of filling the FIFO while the channel is awaiting the synchronization event destination synchronization Case 3 Source port is SARAM DARAM EMIF or MPUI destination port is SARAM DARAM EMIF or MPUI Th...

Page 151: ...rce start address lower bits 0C04h DMA_CSSA_U0 Channel 0 source start address upper bits 0C05h DMA_CDSA_L0 Channel 0 destination start address lower bits 0C06h DMA_CDSA_U0 Channel 0 destination start address upper bits 0C07h DMA_CEN0 Channel 0 element number 0C08h DMA_CFN0 Channel 0 frame number 0C09h DMA_CSFI0 Channel 0 source frame index 0C0Ah DMA_CSEI0 Channel 0 source element index 0C0Bh DMA_C...

Page 152: ... element index 0C2Bh DMA_CSAC1 Channel 1 source address counter 0C2Ch DMA_CDAC1 Channel 1 destination address counter 0C2Dh DMA_CDEI1 Channel 1 destination element index 0C2Eh DMA_CDFI1 Channel 1 destination frame index 0C2Fh Channel 2 DMA_CSDP2 Channel 2 source destination parameters 0C40h DMA_CCR2 Channel 2 control 0C41h DMA_CICR2 Channel 2 interrupt control 0C42h DMA_CSR2 Channel 2 status 0C43h...

Page 153: ...CICR3 Channel 3 interrupt control 0C62h DMA_CSR3 Channel 3 status 0C63h DMA_CSSA_L3 Channel 3 source start address lower bits 0C64h DMA_CSSA_U3 Channel 3 source start address upper bits 0C65h DMA_CDSA_L3 Channel 3 destination start address lower bits 0C66h DMA_CDSA_U3 Channel 3 destination start address upper bits 0C67h DMA_CEN3 Channel 3 element number 0C68h DMA_CFN3 Channel 3 frame number 0C69h ...

Page 154: ...ber 0C88h DMA_CFN4 Channel 4 frame number 0C89h DMA_CSFI4 Channel 4 source frame index 0C8Ah DMA_CSEI4 Channel 4 source element index 0C8Bh DMA_CSAC4 Channel 4 source address counter 0C8Ch DMA_CDAC4 Channel 4 destination address counter 0C8Dh DMA_CDEI4 Channel 4 destination element index 0C8Eh DMA_CDFI4 Channel 4 destination frame index 0C8Fh Channel 5 DMA_CSDP5 Channel 5 source destination parame...

Page 155: ...N5 Channel 5 element number 0CA8h DMA_CFN5 Channel 5 frame number 0CA9h DMA_CSFI5 Channel 5 frame index 0CAAh DMA_CSEI5 Channel 5 element index 0CABh DMA_CSAC5 Channel 5 source address counter 0CACh DMA_CDAC5 Channel 5 destination address counter 0CADh DMA_CDEI5 Channel 5 destination element index 0CAEh DMA_CDFI5 Channel 5 destination frame index 0CAFh ...

Page 156: ...REQ_01 00001 MCSI1 RX DMA_REQ_02 00010 MCSI2 TX DMA_REQ_03 00011 MCSI2 RX DMA_REQ_04 00100 Ext_nDMA_req_0 MPUIO2 DMA_REQ_05 00101 Ext_nDMA_req_1 MPUIO4 DMA_REQ_06 00110 Reserved DMA_REQ_07 00111 McBSP1 TX DMA_REQ_08 01000 McBSP1 RX DMA_REQ_09 01001 McBSP3 TX DMA_REQ_10 01010 McBSP3 RX DMA_REQ_011 01011 UART1 TX DMA_REQ_012 01100 UART1 RX DMA_REQ_013 01101 UART2 TX DMA_REQ_014 01110 UART2 RX DMA_RE...

Page 157: ... The TIPB bridge consists of two components The private TIPB bridge provides a preconfigured bus interface to periph erals residing on the the DSP private TIPB The public TIPB bridge provides a user configurable interface to peripher als on the DSP public TIPB It includes functions to tailor the interface timing to the complement of peripherals operating at a given time The TIPB bridge also contai...

Page 158: ... INT WD Timer DSPWD_CK 1 INT Interrupt handler DSP_INTH_CK Interrupt I F DSP_INTH_CK GPIO I F 1 INT to MPU and or DSP MPU_GPIO_CK Mailbox UART1 2 3 MPU DSP shared peripherals MPUI MPU public TIPB bridge MPU MPU subsystem DSP private peripheral bus DSP public peripheral bus MPU public peripheral bus 16 16 McBSP1 audio PCM I2S via McBSP DSPXOR_CK 2 INT 2DMA DSP public peripherals McBSP3 optical McBS...

Page 159: ...Read 2 CPU priority Priority modes 1 Read Write Read 1 Bus error Application flag error 0 Read Clear Read 0 in HOM 0 Mode SAM or HOM 1 HOM Read Read Mode bit This bit is a read only indication of whether the MPUI is in host only mode HOM or in single access mode SAM HOM and SAM are described in Section 3 6 MPU Interface Bus error This bit is set to 1 if the TIPB bridge generates a bus error due to...

Page 160: ...s Strb2 field sets the access rate for the following peripherals J UART3 test J McBSP1 audio PCM J McBSP3 optical J MCSI 1 J MCSI 2 J GPIO J Mailbox J DSP MPUI register The control mode register bits 5 3 and 8 6 contain the number of wait states required to generate the appropriate strobe frequency see Table 3 8 Table 3 8 Wait States Number of Wait States Strobe Period 0 DSP clk 2 1 DSP clk 3 2 DS...

Page 161: ...erve power The active idle status of the various domains is controlled by the idle control register When the DSP software executes the IDLE instruction the clock domains are configured according to the settings of the ICR see Table 3 9 The current idle domain status is reflected by the state of the ISTR see Table 3 10 The idle domains are 0 CPU 1 DMA 2 Cache 3 Peripherals 4 DPLL 5 EMIF The DSP DPL...

Page 162: ...e Read 0 0 CPU idle domain Read Write Read 0 Note When the DSP subsystem comes out of IDLE the ICR configuration is retained until modified by the CPU The next time an IDLE instruction is executed the same domains enter the idle state Table 3 10 Idle Status Register ISTR ISTR 15 0 Description DSP Access MPU Access Reset Value 15 8 Not connected Read Read 0x0 7 Reserved idle status Read Read 0 6 Re...

Page 163: ...and system DMA always masters the transfer operation It initiates the read or write of DSP memory or peripherals The MPU also controls the parameters of the MPUI by configuring the MPUI_CTRL_REG and the MPUI_DSP_MPUI_CONFIG register There are 5 additional registers the MPU can read to observe the state of the MPUI MPUI_DEBUG_ADDR MPUI_DEBUG_DATA MPUI_DEBUG_FLAG MPUI_STATUS_REG MPUI_DSP_STATUS_REG ...

Page 164: ...and HOM_R bit bit 9 of the ST3 register The appropriate bit is written to request the SAM_M HOM_M or SAM_P HOM_P change The mode change is not reflected on bits 8 and 9 in ST3 until the internal controller has actually completed the mode switch Therefore the DSP polls bits 8 and 9 after requesting a mode change to ensure the mode change is complete The HOM_M SAM_M and HOM_R SAM_R status can be obs...

Page 165: ...OM_R bit a request for sharing is sent to the MPUI If the MPUI clears the HOM_R bit the clearing indicates that the MPU no longer has exclusive ownership of the MPU RAM 1 On The MPUI RAM is owned only by the host processor If you set the HOM_R bit a request for host only mode is sent to the MPUI If the MPUI sets the HOM_R bit the setting indicates that the host processor has exclusive ownership of...

Page 166: ...bal control register GCR EMIF global reset register GRR 3 7 1 EMIF Global Control Register EMIF_GCR The EMIF global control register GCR configures general operation of the EMIF module The EMIF GCR appears at word address 0x0800 in the DSP I O space Table 3 11 EMIF Global Control Register EMIF GCR Bit Name Function Type Reset Value 15 12 Reserved R 0 11 8 Reserved RW 0 7 WPE Write posting enable W...

Page 167: ... space Address translation is performed by a translation table struc ture TTB that maps the most significant bits of the DSP byte address onto another set of most significant bits of a 32 bit MCU byte address The least sig nificant bits of the DSP generated byte address are not altered when forming the new address The TTB translations are expedited by a cache like transla tion look aside buffer me...

Page 168: ...tion for the OMAP5910 device The DSP subsystem master clock DSP_CK is enabled at reset until the DSP is enabled The EN_DSPCK bit in the clock control register ARM_CKCTL allows turning off the DSP_CK while the DSP is still in a reset state The CLKM2 module generates the individual clock domains for the DSP subsystem These clock signals have programmable frequencies based on divisors of several poss...

Page 169: ...igured 3 10 2 DSP Public Peripherals The public TIPB connects the DSP public peripherals to the DSP CPU to pro vide a flexible communications scheme where the DSP or MPU domains can access these devices Because the peripheral registers are also mapped in the MPU memory space the MPU domain can access these peripherals indi rectly via the MPUI and public TIPB bridge This results in a pseudodynamic ...

Page 170: ...l Mode Register 3 10 4 Boot Mode for DSP Subsystem The OMAP5910 device contains a bootloader that is a ROM based utility residing in the DSP subsystem ROM It consists of a program code that facili tates downloading bootloading of DSP code into the DSP subsystem internal memory from either the DSP EMIF interface to the traffic controller or the MPUI interface when it is held in reset by the MPU The...

Page 171: ...pends on the value of BOOT_MOD 3 0 bits If BOOT_MOD 3 0 is equal to 0000 the on chip ROM is not available and the boot address is located off chip If BOOT_MOD 3 0 is not equal to 0000 the on chip ROM is enabled and the boot address is located at the on chip ROM The boot modes supported are listed in Table 3 13 Table 3 13 Boot Modes BOOT_MOD 3 0 Boot Process Starting Address of DSP MPU 0000 No boot...

Page 172: ... Least significant word of destination address for the 1st section Can be from 0000h to FFFFh Emifaddr 3h 1st word of 1st section to transfer Emifaddr 4h 2nd word of 1st section to transfer N1th word of 1st section to transfer Number of elements of the 2nd section to transfer N2 Most significant word of destination address for the 2nd section Can be 0 1 or 2 Least significant word of destination a...

Page 173: ...ransfer from this section the next word should be zero to indicate end of the source program Otherwise another section is assumed to follow Emifaddr 1h MSB of number of elements of the first section to transfer N1 Emifaddr 2h Least significant word of destination address for the 1st section Can be from 0000h to FFFFh Emifaddr 3h Most significant word of destination address for the 1st section Can ...

Page 174: ...am 3 10 4 3 Bootloader Description When the MPU releases the DSP subsystem from reset if pins BOOT_MOD 3 0 0000 then the address 0xFFFF00 is mapped into external memory space If pins BOOT_MOD 3 0 0000 then the address 0xFFFF00 maps to internal ROM that has vector to the bootloader at 0xFF800 At this point the bootloader starts to execute It checks to see if the DSP subsystem in is SAM If not it ke...

Page 175: ... OMAP5910 multimedia processor memory interface traffic controller TC Topic Page 4 1 Introduction 4 2 4 2 Memory Map 4 6 4 3 Memory Interfaces 4 12 4 4 Traffic Controller Memory Interface Registers 4 42 4 5 Interfacing Memories With the OMAP5910 Device 4 57 Chapter 4 ...

Page 176: ...AM DMA H W accelerators MPU peripheral bridge LCD I F MPU interface SRAM SDRAM memories Flash and SRAM memories DSP MMU 16 16 32 16 32 32 32 32 32 32 16 MPU Private Peripheral Bus DSP public shared peripheral bus 32 MPU public 16 DSP DSP public peripherals McBSP1 McBSP3 MPU public peripherals USB host I F JTAG Emulation I F OSC 12 MHz Clock OSC OMAP5910 ETM9 Timers 3 MPU DSP shared peripherals Mai...

Page 177: ... 32 Slow I F DMA Fast I F DMA SRAM DMA Local bus DMA System MPUI MPU Local bus 32 32 32 32 32 32 32 32 Local bus 32 32 32 Slow Fast SRAM Local TIPB MPUI DMA Traffic controller MPU bus MMU 32 MPU TI peripheral bus public interface TI peripheral bus private E I F S M KB port port port port port DMA controller I M I F E M I F F MPU bus To from DSP MMU MPU TI peripheral bus private 16 port To from MPU...

Page 178: ...rnal memory interface slow EMIFS An asynchronous synchro nous interface to handle flash ROM RAM etc Internal memory is memory that is part of the OMAP5910 device and consists of 192K bytes of SRAM The TC accesses the internal memory using an internal memory interface IMIF that is part of the TC Four hosts access the system resources using the TC MPU The MPU is connected to the TC via the MPU bus T...

Page 179: ...d on the correct bit boundary For example 32 bit access must be aligned on 32 bit boundary 16 bit access must be aligned on 16 bit boundary and so forth Access duration management wait state insertion to enable the connection of slow memory devices Memory control signal generation chip select memory specific protocol generation Single accesses for 8 bit or 16 bit words except the TC supports 16 bi...

Page 180: ...ee Table 4 12 EMIF Slow Interface Configuration Register EMIFS_CONFIG_REG Table 4 2 Device Types Associated With Chip Select CS Device CS0 External asynchronous RAM External asynchronous ROM or flash External synchronous burst flash CS1 External asynchronous RAM External asynchronous ROM or flash External synchronous burst flash CS2 External asynchronous RAM External asynchronous ROM or flash Exte...

Page 181: ...rved 1400 0000 1FFF FFFF Internal Memory Interface SRAM Internal RAM 2000 0000 2002 FFFF 192K bytes 8 16 32 R W Reserved 2003 0000 2FFF FFFF DSP Processor Address Space DSP MPUI Interface MPUI Port RAM E000 0000 E0FF FFFF 16M bytes 16 32 R W MPUI DSP Peripherals I O Space E100 0000 E101 FFFF 128K bytes 16 R W DSP Private TIPB Peripherals Strobe0 DSP TI peripheral bus E100 0000 E100 07FF 2K bytes 1...

Page 182: ... GPIOs E101 E000 E101 E7FF 2K bytes 16 R W Reserved E101 E800 E101 EFFF 6K bytes MPU Address Space MPUI port interrupt control and status registers E102 0000 E102 0003 4 bytes 16 R W Reserved E102 0004 EFFF FFFF Reserved F000 0000 FFFD 0000 MPU Public TIPB Peripherals Strobe 0 UART1 FFFB 0000 FFFB 07FF 2K bytes 8 R W UART2 FFFB 0800 FFFB 0FFF 2K bytes 8 R W McBSP2 FFFB 1000 FFFB 17FF 2K bytes 16 R...

Page 183: ...FFB 9FFF 2K bytes 8 R W USB host FFFB A000 FFFB A7FF 2K bytes 32 R W FAC FFFB A800 FFFB AFFF 2K bytes 16 R W Reserved FFFB B000 FFFB BFFF 4K bytes HDQ 1 Wire FFFB C000 FFFB C7FF 2K bytes 8 R W TIPB switches FFFB C800 FFFB CFFF 2K bytes 16 R W LED1 FFFB D000 FFFB D7FF 2K bytes 8 R W LED2 FFFB D800 FFFB DFFF 2K bytes 8 R W Reserved FFFB E000 FFFB FFFF 8K bytes MPU Public TIPB Peripherals Strobe 1 Re...

Page 184: ...300 FFFE C4FF 512 bytes MPU Timer 1 FFFE C500 FFFE C5FF 256 bytes 32 R W MPU Timer 2 FFFE C600 FFFE C6FF 256 bytes 32 R W MPU Timer 3 FFFE C700 FFFE C7FF 256 bytes 32 R W MPU watchdog timer FFFE C800 FFFE C8FF 256 bytes 32 R W MPUI FFFE C900 FFFE C9FF 256 bytes 32 R W MPU private TIPB bridge FFFE CA00 FFFE CAFF 256 bytes 32 R W MPU level 1 interrupt handler FFFE CB00 FFFE CBFF 256 bytes 32 R W Tra...

Page 185: ... bridge FFFE D300 FFFE D3FF 256 bytes 16 R W JTAG ID code FFFE D400 FFFE D4FF 256 bytes 32 R W Reserved FFFE D500 FFFE D7FF System DMA controller FFFE D800 FFFE DFFF 2K bytes 16 R W Reserved FFFE E000 FFFE FFFF 2K bytes each Each register must always be accessed using the appropriate data access width as indicated in this table Failure to do so may result in unexpected behavior including a TIPB bu...

Page 186: ... bit 20 LRU_SEL in FUNC_MUX_CTRL_0 See Chapter 6 MPU Private Peripherals for details on configuration registers Least recently used J A round robin arbitration scheme The highest priority requestor is the one that least recently accessed the memory Dynamic priority J Dynamic priority uses high and low priority queues J Each requestor except the MPU has a time out register allocated to it see Time ...

Page 187: ...ry Interface Slow The EMIFS interfaces with and handles all transactions to flash memory ROM asynchronous memories and synchronous burst flash The interface can drive up to four devices by assignment to one of four chip selects Each chip select has a corresponding register to specify the protocol used for the associated external device Table 4 4 shows the EMIFS signal list Table 4 4 External Memor...

Page 188: ...CS2 functionality In this case capability of the EMIFS interface is reduced from a maximum of four external devices to a maximum of three external devices 4 3 2 1 EMIFS Priority Handler This memory interface has two software selectable priority algorithms for resolving simultaneous access requests least recently used and dynamic priority The priority scheme is shared with the IMIF and EMIFF and is...

Page 189: ... priority queue provides a fixed priority 4 3 2 2 EMIFS Operation This interface generates the appropriate signal timings to drive the following types of devices or compatible devices Intel fast boot block flash 23FxxxF3 AMD simultaneous read write boot sector flash AM29DLxxxG AMD burst mode flash AM29BLxxxC Intel StrataFlash memory 28FxxxJ3A Intel synchronous StrataFlash memory 28FxxxK3 K18 Intel...

Page 190: ...To use the external flash device with the synchronous flash burst protocol the following configuration must be set in the flash device and in the EMIFS chip select configuration registers see Table 4 13 EMIF Slow Chip Select Configuration Registers Read mode Frequency configuration Data output configuration Burst order The EMIF only supports linear burst order Burst length CLK configuration Flash ...

Page 191: ...FCLKDIV Settings and Resulting EMIFS Reference Clock FCLKDIV EMIFS Reference 00 TC clock 1 01 TC clock 2 10 TC clock 4 11 TC clock 6 Depending on the chip select mode configuration the EMIFS reference clock can be output at the FLASH CLK output pin In asynchronous read and write modes EMIFS reference clock is not output and the FLASH CLK pin remains low In synchronous modes EMIFS reference clock i...

Page 192: ...drive time follows FLASH CS_ X activation no setup time guar anty The FLASH ADV output is asserted with the address for use with Intel and AMD burst flash protocols Read data is latched on the same TC clock rising edge that deactivates the FLASH OE signal In asynchronous mode the internal EMIFS reference clock is not provided outside the EMIFS The FLASH CLK signal remains low Figure 4 3 shows typi...

Page 193: ...e 4 4 and Figure 4 5 When crossing a page boundary as in Figure 4 5 the RDWST parameter is used again for the first access on the new page PGWST sets the delay between subsequent words in the page range 0 15 The resulting delay is equal to PGWST 1 x EMIFS_ref This is represented by P cycles in Figure 4 4 and Figure 4 5 BW defines the word length of the access which is equal to the memory data bus ...

Page 194: ... Add5 Add6 Add7 D0 D1 D2 D3 D7 N cycles P cycles High D4 D6 D5 TC Clock internal EMIFS Ref internal Figure 4 5 Asynchronous Page Mode 8x16 Bit Read With Page Crossing on 16 Bit Width Device 4 Words per Page Low FLASH CLK FLASH CS_ X FLASH ADV FLASH A 24 1 FLASH D 15 0 FLASH OE FLASH RDY FLASH BE 1 0 Add0 Add1 Add2 Add3 Addr4 Add5 Add6 Add7 D0 D1 D2 D3 D7 N cycles N cycles P cycles P cycles High D4...

Page 195: ...les Data output of the device is stable on the rising edge of FLASH CLK specified with a setup and hold time referenced to this edge Two configuration registers are used in this operating mode FCLKDIV Specifies the frequency ratio between the TC clock and FLASH CLK see Table 4 13 EMIF Slow Chip Select Configuration Registers RDWST Specifies the number of FLASH CLK cycles between the falling edge o...

Page 196: ... FLASH OE 2 TC clock cycles RDWST 1 xFDIV TC clock cycles RDWST 1 xFDIV TC clock cycles RDWST 1 xFDIV TC clock cycles 6 TC clock cycles RDWST 1 xFDIV TC clock cycles Synchronous Burst Read Operation 1 2 Synchronous Burst Read Operation 2 2 First data valid on this edge Defined by first access latency in Flash configuration register Data strobing edges FLASH BAA 4 TC clock cycles 1 TC clock cycles ...

Page 197: ... rising edge of FLASH WE data hold time specified is 0 ns minimum which can be ensured by one TC clock cycle The FLASH WE low pulse duration is programmable for each device through the WELEN field in the flash configuration register The number of wait states between write operations is programmable for each device through the WRWST field in the configuration register The duration from falling FLAS...

Page 198: ... device In dynamic not ready mode FLASH RDY is used by the external device to indicate to OMAP5910 that it will be going inactive after the current access completes The programming of FLASH RDY modes is described in Table 4 27 EMIF Slow Wait State Configuration 4 3 2 10 EMIFS Dual Port RAM Interface Mode The OMAP5910 EMIFS includes a programmable mode associated with the FLASH CS2 chip select pin ...

Page 199: ... Bus Description SDRAM A 12 0 O 12 0 SDRAM address bus SDRAM D 15 0 I O 15 0 Data from SDRAM SDRAM CLK I O Clock to SDRAM SDRAM BA 1 0 O 1 0 SDRAM bank select SDRAM CKE O SDRAM clock enable SDRAM RAS O SDRAM RAS SDRAM CAS O SDRAM CAS SDRAM WE O SDRAM write enable SDRAM DQML O Lower byte 3 state SDRAM DQMU O Upper byte 3 state 4 3 3 1 EMIFF Priority Handler This memory interface has two software se...

Page 200: ...low priority queue order is H MPU H DSP H Local bus H DMA all channels including LCD J The high priority queue order is H DMA transfer involving LCD channel H DSP H Local bus H DMA transfer involving channels other than LCD channel Fixed priority is a special case of dynamic priority To create a fixed priority all time out registers must have a value of 0 This way any request made goes into the hi...

Page 201: ... with the burst size of the SDRAM MRS configuration register which must always be set with continuous burst Depending on the system loading within the device and the specific configurations and interactions between the different initiators burst transfers may or may not be achieved on the EMIFF by any specific initiator However the SDRAM request management logic within the SDRAM controller allows ...

Page 202: ...is set the OMAP configures SDRAM banks to write out the EMIFF_MRS register as EMRS commands instead of MRS commands Reading from the EMIF fast interface SDRAM MRS register does not generate any external transactions Note The SDRAM requires 100 µs to stabilize after power up Software is respon sible for performing the initial setup of SDRAM For more information see Table 4 20 EMIF Fast Interface SD...

Page 203: ...ck generator and system reset module In idle mode the traffic controller clock is stopped If the clock remains idle for more than 64 milliseconds and the SDRAM was not entered into self refresh mode SDRAM data corruption results Setting the RFRSH_STBY bit in the EMIF fast interface SDRAM configuration register 2 EMIFF_SDRAM_CONFIG_2 avoids SDRAM data corruption by automati cally placing the SDRAM ...

Page 204: ...RAM CLK is disabled using these steps 1 Set the PDE bit field of the EMIF slow interface configuration register 2 Set one or both of the following bit fields in the EMIF fast SDRAM configuration register 1 a Set the SLRF to place the SDRAM into self refresh mode b Set the PWD to place the SDRAM into power down mode 3 Set the CLK bit field of the EMIF fast interface SDRAM configuration register 1 t...

Page 205: ...32 Bit Word With Burst Stop ACTV0 ACCESS_GRANT COMMAND ADDRESS DQ CURRENT_COL CURRENT_SIZE DVALID SAVE_ADD LAST_DATE ACCESS_REG 2 A NA STOP WRITE B0 R0 0 1 C0 D B0 C0 C0 1 C0 1 C0 2 Ignored D NA Note WRITE burst reduced to 2 is interrupted by a STOP command because no new request is pending ...

Page 206: ...rd With Burst Stop ACTV0 ACCESS_GRANT COMMAND ADDRESS DQ CURRENT_COL CURRENT_SIZE DVALID SAVE_ADD LAST_DATE ACCESS_REG A NA STOP WRITE B0 R0 D Ignored NA 0 C0 2 C0 1 B0 C0 Note WRITE burst reduced to 1 is interrupted by a STOP command because no new request is pending ...

Page 207: ...ND ADDRESS DQ CURRENT_COL CURRENT_SIZE DVALID SAVE_ADD LAST_DATE ACCESS_REG 2 STOP WRITE B0 R0 0 C0 D B1 C1 C1 C0 1 C1 1 D WRITE 2 B0 C0 D D D D D D D C1 1 C1 2 C1 3 C1 4 C1 5 C1 6 C1 7 C1 8 C1 2C1 3 C1 4C1 5 C1 6C1 7 7 6 5 4 3 2 1 0 Output column counter Note WRITE burst reduced to 1 is followed by a WRITE 8 in a different bank and in a page already active ...

Page 208: ...Half Word With Burst Stop ACTV0 ACCESS_GRANT COMMAND ADDRESS DQ CURRENT_COL CURRENT_SIZE DVALID SAVE_ADD LAST_DATE ACCESS_REG 2 STOP READ B0 R0 0 C0 Q B0 C0 C0 1 L 3 Note READ burst reduced to 1 is interrupted by a STOP command because no new request is pending ...

Page 209: ...AND ADDRESS DQ CURRENT_COL CURRENT_SIZE DVALID SAVE_ADD LAST_DATE ACCESS_REG 2 STOP READ B0 R0 0 C0 Q B1 C1 C1 C0 1 C1 1 Q READ 2 B0 C0 Q Q Q Q Q Q Q C1 1 C1 2 C1 3 C1 4 C1 5 C1 6 C1 7 C1 8 C1 2C1 3 C1 4C1 5 C1 6C1 7 7 6 5 4 3 2 1 0 Output column counter L 3 Note READ burst reduced to 1 is followed by a READ burst 8 in a different bank and in a page already active ...

Page 210: ...T_COL CURRENT_SIZE DVALID SAVE_ADD LAST_DATE ACCESS_REG 2 STOP WRITE B0 R0 1 C0 B1 C1 C0 1 C0 1 C1 2 Q READ 2 B0 C0 Q Q Q Q Q Q Q C1 C1 1 C1 2 C1 3 C1 4 C1 5 C1 6 C1 7 C1 1 C1 2 C1 3 C1 4 C1 5 C1 6 L 3 C1 8 C1 7 7 6 5 4 3 2 1 0 0 D Ignored D Note WRITE burst reduced to 2 is interrupted by a READ request pending on a bank and row already active ...

Page 211: ...NT COMMAND ADDRESS DQ CURRENT_COL CURRENT_SIZE DVALID SAVE_ADD LAST_DATE ACCESS_REG 2 STOP WRITE B0 R0 0 C0 C0 1 STOP 2 B0 C0 D D D D D D C5 1 C5 2 C5 3 C5 4 C5 5 C5 1 C5 2 C5 3 C5 4 C5 6 C5 5 4 3 2 1 0 D DEA C ACTV0 WRIT E trc 9 tras 5 B0 R0 B0 R5 C5 5 Note WRITE burst reduced to 1 is followed by a WRITE 6 in the same bank but on a different page ...

Page 212: ...ADDRESS DQ CURRENT_COL CURRENT_SIZE DVALID SAVE_ADD LAST_DATE ACCESS_REG 2 STOP READ B0 R0 3 C0 B1 C1 C0 1 C0 1 C0 2 Q 2 B0 C0 Q Q Q D D D C0 3 C0 4 C1 1 C1 2 C0 3 C1 5 C1 6 L 3 C1 3 C1 7 1 0 2 1 0 2 STOP WRITE C0 2 Note READ burst reduced to 4 is interrupted by a WRITE request reduced to 3 pending on a bank and row already active ...

Page 213: ... ACTV0 ACCESS_GRANT COMMAND ADDRESS DQ CURRENT_COL CURRENT_SIZE DVALID SAVE_ADD LAST_DATE ACCESS_REG 2 STOP READ B0 R0 0 C0 C0 1 2 B0 C0 D C5 1 Q DEA C ACTV0 WRIT E trc 9 tras 4 B0 R0 B0 R5 C5 0 B0 C5 L 3 DQMU DQML DQMx Note READ burst reduced to 1 is followed by a single byte WRITE in the same bank but on a different page ...

Page 214: ...ND ADDRESS DQ CURRENT_COL CURRENT_SIZE DVALID SAVE_ADD LAST_DATE ACCESS_REG 2 STOP WRIT E B0 R0 0 C0 C0 1 STOP 2 B0 C0 D D D D D D C5 1 C5 2 C5 3 C5 4 C5 5 C5 1 C5 2 C5 3 C5 4 C5 6 C5 5 4 3 2 1 0 D DEA C ACTV0 WRIT E trc 9 tras 5 B0 R0 B0 R5 C5 5 Note WRITE burst reduced to 1 is followed by a WRITE 6 in the same bank but on a different page ...

Page 215: ...CURRENT_SIZE LAST_DATA SAVE_ADDR DATA_READY_STROBE ACTV0 DEAC STOP READREAD ACTV0 READ STOP 7 0 C1 C0 C1 8 C1 7 C1 6 C1 5 C1 4 C1 3 C1 2 00 C1 1 C0 1 Q B1 R1 B1 R1 B1 C1 B0 C0 B0 R0 1 2 3 4 5 6 0 C1 1 C1 7 C1 6 C1 5 C1 4 C1 3 C1 2 00 Detection of new row Q Q Q Q Q Q Q Q B1 00 READ burst reduced to 1 followed by a READ burst 8 in a different bank and in a page already active with a page crossing 1 ...

Page 216: ...w interface configuration register R W 32 bits 0xFFFE CC0C 0x0000 00yy See Table 4 12 for details on the y values EMIFS_CS0_CONFIG EMIF slow interface chip select configuration register nCS0 R W 32 bits 0xFFFE CC10 0x0000 FFFB EMIFS_CS1_CONFIG EMIF slow interface chip select configuration register nCS1 R W 32 bits 0xFFFE CC14 0x0010 FFFB EMIFS_CS2_CONFIG EMIF slow interface chip select configurati...

Page 217: ...t state configuration register R W 32 bits 0xFFFE CC40 0x0000 0000 Table 4 9 IMIF Priority Register IMIF_PRIO Bit Field Description Access Reset Value 31 0 Reserved Reserved for future expansion These pins must always be written as 0 R All 0s Table 4 10 EMIF Slow Priority Register EMIFS_PRIO Bit Field Description Access Reset Value 31 0 Reserved Reserved for future expansion These pins must always...

Page 218: ...ower down not enabled 1 Power down enabled 2 PWD_EN IMIF power down enable Controls IMIF internal clock enable R W 0 0 IMIF power down not enabled 1 IMIF power down enabled Also note that PWD_EN is one of the prerequisites to meet TC idle PWD_EN must be set before the memory interface can acknowledge a TC idle request 1 BM MPU boot mode This bit is sampled at reset from the MPU_BOOT device pin BM ...

Page 219: ... 0 0 The address is incremented for the second 16 bit access default 1 The address is not incremented for the second 16 bit access This bit is valid only when EMIFS is configured for 16 bit data bus width BW 0 This bit has no effect for read operations 20 BW Specifies EMIFS data bus width R W 0 16 bit bus This is the appropriate setting for OMAP5910 1 Reserved Do not use this setting on OMAP5910 B...

Page 220: ...fined Writes must be zero R W U 2 RT Retiming control register R W 0 0 The data is not retimed 1 The data coming from the external bus is retimed with the CLK 1 0 FCLKDIV EMIFS internal reference clock divider R W 11 00 Reference clock TC clock divided by 1 01 Reference clock TC clock divided by 2 10 Reference clock TC clock divided by 4 11 Reference clock TC clock divided by 6 Table 4 14 Memory T...

Page 221: ...n to support 2 clock cycle duration since FLASH CLK may be divided Page crossing is supported in page mode ROM burst read In asynchronous read mode FLASH ADV is activated during one FLASH CLK cycle in order to ensure compatibility with burst flash Table 4 16 EMIF Fast Interface SDRAM Configuration Register 1 EMIFF_SDRAM_CONFIG Bit Field Value Description Access Reset Value 31 28 Reserved Read is u...

Page 222: ...gurations based on clock latencies See Table 4 18 R W 00 00 SDF0 reset value 01 SDF1 10 SDF2 11 SDF3 23 8 ARCV Autorefresh counter register value Sets the interval between partial refresh requests to the SDRAM See Section 4 3 3 4 SDRAM Autorefresh Initialization for formula and example R W 0x6188 7 4 SDRAM_TYPE Set the SDRAM internal organization see Table 4 17 R W 0000 3 2 ARE Autorefresh enable ...

Page 223: ...clock 0 SLRF When set places the SDRAM in self refresh mode Mode is automatically exited upon the generation of any SDRAM access R W 0 This register is used to configure the SDRAM interface timing autorefresh setup and powerdown modes of the EMIFF interface Table 4 17 describes the internal organization Table 4 18 describes the frequency range Table 4 17 SDRAM Internal Organization Register Value ...

Page 224: ...1101 8 4 1110 16 2 1111 16 4 Unavailable bank number not supported Do not use this setting Note Reset value 0x0h Table 4 18 Frequency Range ac Parameters SDF0 Cycles SDF1 Cycles SDF2 Cycles SDF3 Cycles trc 9 5 3 2 tras 5 3 2 2 trp 3 2 2 2 trcd 3 2 2 2 trrd 2 2 2 2 tdpl trwl tdal trsc 2 2 2 Write is never interrupted by precharge command directly Neither read or write with auto precharge is support...

Page 225: ...arge command directly Neither read or write with autoprecharge is supported For 60 MHz timing can be met by using the SDF1 timing configuration This register when written programs the SDRAM MRS default and EMRS configuration registers In default mode a write to the register initiates an MRS request to the SDRAM In EMRS mode a write to this same register initiates an EMRS request Reading this regis...

Page 226: ... CAS latency 3 default at reset 3 S I Serial 0 This bit must be 0 Interleave 1 Reserved Do not use this setting R W 0 2 0 PGBL Specifies page burst length to be programmed into SDRAM MRS configuration register The length must always be programmed as full page burst length 111 This length is not necessarily the burst length at which the EMIFF operates but rather a setting for the SDRAM MRS register...

Page 227: ...re 10 15 degrees Celsius maximum case temperature 11 85 degrees Celsius maximum case temperature Bit descriptions are given with respect to standard SDRAM devices and must be verified with the actual SDRAM chosen for the application 2 0 PASR SDRAM EMRS register partial array self refresh coverage setting R W See Note 1 000 All banks 001 Half array 010 Quarter array 011 Reserved 100 Reserved 101 Re...

Page 228: ...ed Read is undefined Writes must be zero R All 0 23 16 Local bus R W 0x00 15 8 Reserved Read is undefined Writes must be zero R W All 0 7 0 DMA R W 0x00 Table 4 23 Time Out 2 Register TIMEOUT2 Bit Field Description Access Reset Value 31 24 Reserved Read is undefined Writes must be zero R All 0 23 16 DSP R W 0x00 15 8 Reserved Read is undefined Writes must be zero R W All 0 7 0 LCD R W 0x00 Table 4...

Page 229: ...ld Value Description Access Reset Value 31 2 Reserved Read is undefined Writes must be zero R All 0 1 RFRSH_ RST SDRAM self refresh on warm reset RFRSH_RST determines what action the TC SDRAM controller takes toward setting SDRAM to self refresh mode in the event of a warm system reset R W 1 0 SDRAM is not entered to self refresh mode 1 SDRAM is entered to self refresh mode upon warm system reset ...

Page 230: ... classic not ready for EMIFS CS3 1 Enable dynamic not ready for EMIFS CS3 2 DYNW_CS2 Specifies function of FLASH RDY for CS2 R W 0 0 Enable classic not ready for EMIFS CS2 1 Enable dynamic not ready for EMIFS CS2 1 DYNW_CS1 Specifies function of FLASH RDY for CS1 R W 0 0 Enable classic not ready for EMIFS CS1 1 Enable dynamic not ready for EMIFS CS1 0 DYNW_CS0 Specifies function of FLASH RDY for C...

Page 231: ...ram code uses two Intel 28F64J3A memories and data uses Intel 28F32J3A The power supply voltages for these memories range from 2 7 V to 3 V Hitachi memory has a total capacity of 96M bits in this example Two flash memories are used for program code and one flash memory is used for data The power supply voltage also ranges from 2 7 V to 3 V Hitachi SDRAM HM52Y64165F has a total capacity of 64M bits...

Page 232: ...Flash STS A 0 A 21 1 DQ 15 0 INTEL 28F32J3A X16 NC NC fdata 7 0 fdata 15 8 NC NC VCC R for Data for Code for Code 2 5 V 2 8 V 2 7 V 3 0 V OMAP5910 2 7 V 3 0 V 2 7 V 3 0 V 2 7 V 3 0 V SDRAM_CLK SDRAM CKE SDRAM RAS SDRAM CAS SDRAM WE SDRAM DQMU SDRAM DQML SDRAM D 15 0 SDRAM BA 1 0 SDRAM A 11 0 SDRAM A 12 FLASH RDY FLASH CS0 FLASH RP FLASH OE FLASH WE FLASH A 24 FLASH A 23 1 FLASH D 15 0 FLASH BAA FL...

Page 233: ...HI 32M TOSHIBA X8 X8 X16 Flash R B A 20 0 DQ 15 0 HITACHI 32M X16 NC NC fdata 7 0 fdata 15 8 NC VCC VCC VCC R for Data for Code for Code 2 5 V 2 8 V 2 7 V 3 0 V OMAP5910 2 7 V 3 0 V 2 7 V 3 0 V 2 7 V 3 0 V SDRAM_CLK SDRAM CKE SDRAM RAS SDRAM CAS SDRAM WE SDRAM DQMU SDRAM DQML SDRAM D 15 0 SDRAM BA 1 0 SDRAM A 11 0 SDRAM A 12 FLASH RDY FLASH CS0 FLASH RP FLASH OE FLASH WE FLASH A 24 FLASH A 23 1 FL...

Page 234: ...ribes the system DMA controller for the OMAP5910 multimedia processor Topic Page 5 1 Introduction 5 2 5 2 External Connections 5 8 5 3 Generic Channels 5 9 5 4 LCD Dedicated Channel 5 26 5 5 DMA Request Mapping 5 32 5 6 Registers 5 34 Chapter 5 ...

Page 235: ...RAM SDRAM memories Flash and SRAM memories DSP MMU 16 16 32 16 32 32 32 32 32 32 16 MPU private peripheral bus DSP public shared peripheral bus 32 MPU public 16 DSP DSP public peripherals McBSP1 McBSP3 MPU public peripherals USB Host I F JTAG emulation I F OSC 12 MHz Clock OSC OMAP5910 ETM9 Timers 3 MPU DSP shared peripherals Mailbox MPU Private Peripherals Timers 3 16 Memory interface Reset Exter...

Page 236: ...IN DOUT Addr LCD FIFO 64 x17 Bits Interrupt generator Event synchro Dma _nreq 5 0 Ndma_req 5 0 TI dma _lcd_ram 15 0 System DMA controller Request Allocator To interleaver LCD Port Din Dout DIN DOUT Addr DIN DOUT Addr DIN DOUT Addr DIN DOUT Addr DIN DOUT Addr FIFO 0 R W Unit 0 FIFO 8 R W Unit 8 Configuration register bank 8 Configuration register bank 0 LCD R Addr CFG LCD peripheral bus Port Port P...

Page 237: ... scheduled through software parameters available to the user Thus the user is able to control the sharing of a port between channels by the assignment of priority levels The system DMA controller has nine independently programmable generic channels plus one channel that is specifically dedicated only to transfers from either the IMIF or the EMIFF ports to the LCD port By dynamically assigning one ...

Page 238: ...loca tion versus processor MPU or DSP access Through the assignment of priority levels for each channel the user can determine how the ports are shared between channels Concurrent DMA transfers capability Start of transfer on peripheral request or host request Byte alignment capability Byte packing unpacking Byte transfer count Configurable indexes through memory for each channel source and destin...

Page 239: ... local bus ports All LCD DMA accesses are performed in bursts of 8 x16 bits The LCD video buffer data must be a multiple of 16 bytes The start address and end address must be aligned on a 16 bit boundary General purpose channel priority on the external EMIFF IMIF bus is software programmable LCD channel FIFO size is 64x17 bits The interface between the LCD controller and the DMA controller uses a ...

Page 240: ...nation 32 Bit Non TIPB 8 bit TIPB Valid only with no packing s8 Valid s8 Not allowed Valid s8 Not allowed Valid s8 8 bit non TIPB Valid only with no packing s8 Valid s8 Not allowed Valid s8 s16 Not allowed Valid s8 s16 32 16 bit TIPB Not allowed Valid s16 Valid only with no packing s16 Valid s16 Not allowed Valid s16 16 bit non TIPB Valid with s8 and no packing Valid s8 Valid only with no packing ...

Page 241: ...own in Figure 5 3 Figure 5 3 System DMA External Connections TIPB DMA_IT_NF 5 0 LCD protocol specific TIPB protocol TIPB protocol DMA_REG DMA configuration bus MIF EMIFS port IMIF port EMIFF port Local bus port Local bus LCD controller LCD display MPUI port TIPB port T I P B IMIF EMIFS EMIFF P1 P0 System DMA controller TIPB bridge ...

Page 242: ...shared by several channel requests Therefore these requests are time multiplexed by the port For example in Figure 5 4 a DMA port must service requests from three DMA channels Channel 0 as a source port read requests r0 Channel 3 as a destination port write requests w3 Channel 5 as a destination port write requests w5 Figure 5 4 shows how these requests are multiplexed in time by the port Figure 5...

Page 243: ...igure 5 5 Basic Flow of DMA Transfer MPU loads the transfer configuration registers DMA channel IDLE No request Transfer one element frame Transfer completed Interrupt generated Yes Synchronized request Hardware signal OK No No Yes Yes DMA request No ...

Page 244: ... request J An entire frame A complete frame of several elements is transferred in response to a DMA request All the transfers can be synchronized on DMA requests regardless of their sources and destinations DMA requests can come from DMA ports Each channel can be triggered by one DMA request among 31 One DMA request can trigger several channels at the same time The relevant bits are extracted from...

Page 245: ...s copied in the active set of registers You can then pro gram the programming set to configure the next transfer while the current transfer is running This feature can be used in two ways J Continuous operation You can change the programming registers while the current configu ration is executed The next transfer is transferred with a new context but without stopping the DMA J Repetitive operation...

Page 246: ...igh priority level When a DMA port receives requests from several channels it looks at their priorities Requests from high priority channels are served first Requests from low priority channels are served only if there are no requests from high priority channels on the port This can occur if there are no high priority channels activated if the high priority channels are stalled by a slow source or...

Page 247: ...te 14 Byte 15 Byte 16 Byte 17 value after an element value after a frame Block n The amount of data block size to transfer is programmed in bytes This size can be odd or even The start address for a transfer is a byte address and can be odd in other words non word aligned this is true only if bursting is not enabled because any DMA channel that has bursting enabled must use a start address that is...

Page 248: ...ssing mode Destination addressing mode These modes work independently For example to transfer data from a TIPB serial port to internal memory the source addressing mode is constant for ex ample when the read operation must be done at a unique register address and the destination addressing mode is post incremented The number of frames the number of elements and the element size are the same for so...

Page 249: ...a i 1 1 if i mod ES 0 1 i BS 1 a i a i 1 EI if i mod ES 0 1 i BS 1 where a i is the address of the byte number i within the transfer SA is the start address of the transfer BS is the block size in bytes ES is the element size in bytes 1 ES 2 EI is the element index in bytes specified in a configuration register 32768 EI 32767 5 3 2 4 Double Indexed Addressing Mode Address is incremented by a frame...

Page 250: ... burst of four 32 bit words or burst8 burst of eight words access only the LCD channel can perform burst8 ac cesses This increases the transfer rate For a channel the decision to pack or burst accesses to its source port is made by the source address unit and depends on source port access capability The decision to pack and or burst accesses to its destination port is made by the destination addre...

Page 251: ...s J Is packing allowed DST_PACK or SRC_PACK set J Is bursting allowed DST_BURST_EN or SRC_BURST_EN set The last bits of the address J Is the address even or odd J Is the address word16 word32 burst4 burst8 aligned The number of elements remaining in the frame When the type of access is determined the current byte address can be in cremented by 1 2 or 4 to reach the next memory space location to ac...

Page 252: ... 16 bit word If frame index is used it must always produce addresses aligned on a 16 bit word If element index is used it must always produce addresses aligned on a 16 bit word Example 5 1 provides an example of packing and splitting Example 5 1 Packing 2 x s16 32 A channel is set up for a transfer with the following parameters for its source J Number of frames in the block FN 2 J Number of elemen...

Page 253: ...16 20 24 Element 2 1 Element 2 2 28 Element 2 3 Element 2 4 32 Element 2 5 36 40 The computed addresses and access types are as identified in Table 5 6 Table 5 6 Address and Access Types Clock Cycle Frame Number j Element Number i Address Access 0 1 1 2 16 bits 1 1 2 4 32 bits 2 1 4 8 32 bits 3 2 1 24 32 bits 4 2 3 28 32 bits 5 2 5 32 16 bits 6 End of transfer ...

Page 254: ...ddress are always 0000 When using the indexed addressing modes element index and or frame index all the addresses computed must be aligned on the data type Failure to adhere to these address alignment requirements could yield unexpected results In the case of the four word bursting alignment failure to properly align the addresses could result in a lockup condition on the DMA channel To accomplish...

Page 255: ...MA con tains adaptation logic to convert incoming data to big endian and outgoing data back to little endian This adaptation logic is static can not be configured and is transparent to system DMA operation Additional logic unrelated to the system DMA is available to perform endian ism conversion between the DSP and the MPU at the DSP MMU and the MPUI interfaces These are described in section 2 11 ...

Page 256: ...e Time out An access has been timed out To prevent a definitive lock by a channel on a memory location or peripher al all the DMA ports to memory peripheral requests are monitored by a time out counter in the following sequence 1 When the request is sent by the DMA to transfer data in a channel a time out counter is triggered 2 The request is acknowledged and the time out counter is stopped 3 If t...

Page 257: ...MPU level2 IRQ22 is dedicated to channel 3 Interrupt line 4 MPU level2 IRQ23 is dedicated to channel 4 Interrupt line 5 MPU level2 IRQ24 is dedicated to channel 5 Interrupt line 6 MPU level2 IRQ25 is dedicated to the LCD channel If simultaneous events occur in two physical channels that share the same interrupt line only one interrupt is generated and all the relevant status bits are set Each phys...

Page 258: ...port with an address that must hit in the destination port memory space If the software specifies a port with an address that does not hit this port memory space example source port EMIFF with an EMIFS start address specified the transfer continues and memory can be corrupted No address space check is performed by the DMA or outside the DMA It is the programmer s responsibility to ensure coherency...

Page 259: ...7 bits Read control logic LCD address unit read dma_lcd_ram 15 0 dma_lcd_enable dma_lcd_ready dma_lcd_un_flow dma_lcd_add 5 0 Interrupt generator LCD registers IMIF port EMIFF port Priority always high From to generic channels LCD controller EMIFF scheduler IMIF EMIFF TIPB system DMA LCD channel Read address Data 16 bits Asyncronous RAM memory Switching from one frame to another is achieved by loa...

Page 260: ... addressing modes used in the LCD channel are not compliant with the generic modes The generic channels receive two instances of the address unit The LCD channel does not have the write address unit instantiated because there is no write address to compute that is the read FIFO address is given by the OMAP LCD controller so there is no write address 5 4 2 1 LCD Addressing At the beginning of LCD o...

Page 261: ...le Source In case of dual frame operation it is not possible to have one frame read from one source and one frame read from second source For changing from one source to another the LCDEN bit of the LCD control register see Section 11 8 LCD Controller Registers must be cleared to 0 and all pending LCD interrupts processed The LCDEN bit level is connected to the dma_lcd_en input of the DMA LCD chan...

Page 262: ...frame located in EMIFF to the LCD controller The size for the LCD display is 6x16 pixels with 16 bits per pixel So the length of the video frame is 6 x16 x 2 in bytes 32 bytes for the palette 224 bytes If the video frame starts at address 0x0B0000 the bottom address of the video frame is 0x0B00DE Registers settings are shown in Table 5 8 Table 5 7 EMIF to LCD Register Settings One Frame DMA_LCD_CT...

Page 263: ... 5 4 4 2 IMIF to LCD Two Frames Figure 5 12 shows a transfer from two video frames located in IMIF to the LCD controller The size for the LCD display is 6 x 16 pixels with 16 bits per pixel So the length of one video frame is 6 x 16 x 2 in bytes 32 bytes for the palette 224 bytes If the video frame 1 starts at address 0x0B0000 the bottom address of the video frame is 0x0B00DE If the video frame 2 ...

Page 264: ... The transfer runs and the interrupts are generated at the ends of frames 1 and 2 Figure 5 12 LCD Dual Frame Mode Transfer Scheme IMIF Video frame 1 LCD controller DMA Video frame 2 0x0B 0000 0x0C 0000 0x0B 00DE 0x0C 00DE When an interrupt occurs read the DMA_LCD_CTRL register to find the source of the interrupt If DMA_LCD_CTRL 3 1 end frame 1 interrupt If DMA_LCD_CTRL 4 1 end frame 2 interrupt Wh...

Page 265: ...A_REQ_04 EXT_DMA_REQ0 MPUIO2 DMA_REQ_05 EXT_DMA_REQ1 MPUIO4 DMA_REQ_06 MicroWire TX DMA_REQ_07 McBSP1 TX DMA_REQ_08 McBSP1 RX DMA_REQ_09 McBSP3 TX DMA_REQ_10 McBSP3 RX DMA_REQ_011 UART1 TX DMA_REQ_012 UART1 RX DMA_REQ_013 UART2 TX DMA_REQ_014 UART2 RX DMA_REQ_015 McBSP2 TX DMA_REQ_016 McBSP2 RX DMA_REQ_017 UART3 TX DMA_REQ_018 UART3 RX DMA_REQ_019 Camera RX DMA_REQ_020 MMC TX DMA_REQ_021 MMC RX DM...

Page 266: ...A Request Mapping Continued MPU System DMA Requests MPU System DMA Reserved DMA_REQ_025 USB function RX0 DMA_REQ_026 USB function RX1 DMA_REQ_027 USB function RX2 DMA_REQ_028 USB function TX0 DMA_REQ_029 USB function TX1 DMA_REQ_030 USB function TX2 DMA_REQ_031 ...

Page 267: ...ED800 0x0000 DMA_CCR_CH0 Channel 0 control R W 16 0xFFFED802 0x0000 DMA_CICR_CH0 Channel 0 interrupt control R W 16 0xFFFED804 0x0003 DMA_CSR_CH0 Channel 0 status R 16 0xFFFED806 0x0000 DMA_CSSA_L_CH0 Channel 0 source start address lower bits R W 16 0xFFFED808 U DMA_CSSA_U_CH0 Channel 0 source start address upper bits R W 16 0xFFFED80A U DMA_CDSA_L_CH0 Channel 0 destination start address lower bit...

Page 268: ...0xFFFED850 U DMA_CFN_CH1 Channel 1 frame number R W 16 0xFFFED852 U DMA_CFI_CH1 Channel 1 frame index R W 16 0xFFFED854 U DMA_CEI_CH1 Channel 1 element index R W 16 0xFFFED856 U DMA_CPC_CH1 Channel 1 channel progress counter R W 16 0xFFFED858 U DMA_CSDP_CH2 Channel 2 source destination parameters R W 16 0xFFFED880 0x0000 DMA_CCR_CH2 Channel 2 control R W 16 0xFFFED882 0x0000 DMA_CICR_CH2 Channel 2...

Page 269: ...ED8C8 U DMA_CSSA_U_CH3 Channel 3 source start address upper bits R W 16 0xFFFED8CA U DMA_CDSA_L_CH3 Channel 3 destination start address lower bits R W 16 0xFFFED8CC U DMA_CDSA_U_CH3 Channel 3 destination start address upper bits R W 16 0xFFFED8CE U DMA_CEN_CH3 Channel 3 element number R W 16 0xFFFED8D0 U DMA_CFN_CH3 Channel 3 frame number R W 16 0xFFFED8D2 U DMA_CFI_CH3 Channel 3 frame index R W 1...

Page 270: ...8 U DMA_CSDP_CH5 Channel 5 source destination parameters R W 16 0xFFFED940 0x0000 DMA_CCR_CH5 Channel 5 control R W 16 0xFFFED942 0x0000 DMA_CICR_CH5 Channel 5 interrupt control R W 16 0xFFFED944 0x0003 DMA_CSR_CH5 Channel 5 status R 16 0xFFFED946 0x0000 DMA_CSSA_L_CH5 Channel 5 source start address lower bits R W 16 0xFFFED948 U DMA_CSSA_U_CH5 Channel 5 source start address upper bits R W 16 0xFF...

Page 271: ...0xFFFED990 U DMA_CFN_CH6 Channel 6 frame number R W 16 0xFFFED992 U DMA_CFI_CH6 Channel 6 frame index R W 16 0xFFFED994 U DMA_CEI_CH6 Channel 6 element index R W 16 0xFFFED996 U DMA_CPC_CH6 Channel 6 channel progress counter R W 16 0xFFFED998 U DMA_CSDP_CH7 Channel 7 source destination parameters R W 16 0xFFFED9C0 0x0000 DMA_CCR_CH7 Channel 7 control R W 16 0xFFFED9C2 0x0000 DMA_CICR_CH7 Channel 7...

Page 272: ...dress upper bits R W 16 0xFFFEDA0A U DMA_CDSA_L_CH8 Channel 8 destination start address lower bits R W 16 0xFFFEDA0C U DMA_CDSA_U_CH8 Channel 8 destination start address upper bits R W 16 0xFFFEDA0E U DMA_CEN_CH8 Channel 8 element number R W 16 0xFFFEDA10 U DMA_CFN_CH8 Channel 8 frame number R W 16 0xFFFEDA12 U DMA_CFI_CH8 Channel 8 frame index R W 16 0xFFFEDA14 U DMA_CEI_CH8 Channel 8 element ind...

Page 273: ...al Control register DMA_GCR Bit Name Value Description Type Reset Value 15 4 RESERVED 3 AUTOGATING_ON DMA clock autogating is as follows RW 1 0 Reserved Do not use this setting 1 Allows the DMA to dynamically cut off its clocks according to its activity This bit should always be set to 1 2 FREE DMA reaction to the suspend signal is as follows RW 0 0 The DMA suspends all the current transfers when ...

Page 274: ... 4 x dst_width When bursting is disabled the destination port performs single accesses of dst_width bits RW 00 00 Single access no burst 01 Single access no burst 10 Burst 4 11 Reserved do not use this setting If the destination port of the channel has no burst access capability this field is ignored 13 DST_PACK Destination packing The DMA ports can have a data bus width different from that of the...

Page 275: ... IMIF 0011 TIPB 0100 Local 0101 TIPB_MPUI Others Illegal do not use this setting 8 7 SRC_BURST_EN Source burst enable Enable disable bursting on the source port When bursting is enabled the source port performs bursts 4 x src_width When bursting is disabled the source port performs single accesses of src_width bits RW 00 00 Single access no burst 01 Single access no burst 10 Burst 4 11 Reserved do...

Page 276: ...s8 data can be read on a 32 bit DMA port The DMA channel has the capacity to pack four consecutive s8 data reads in a single 32 bit read access to increase bandwidth RW 0 0 The source port never makes packed accesses 1 The source port makes packed accesses 5 2 SRC Transfer source A unique identifier is given to each port This field indicates which port is the originator of the transfer RW 0000 000...

Page 277: ... 00 s8 8 bits scalar 01 s16 16 bits scalar 10 s32 32 bits scalar 11 Illegal value Start address must be aligned on the boundary of the type of data moved For example if type is s32 the source and destination start address must be aligned on a 32 bit word If type is s8 source and destination start address can have any value The DMA forces by hardware the start address value on the type of data tran...

Page 278: ...dressing mode on the source port of a channel RW 00 00 Constant address 01 Post incremented address 10 Single index element index 11 Double index element index and frame index 11 END_PROG End of programming RW RST 0 0 Delays the channel autoinitialization if AUTO_INIT 1 and REPEAT 0 1 Allows the channel to reinitialize itself if AUTO_INIT 1 10 RESERVED RW RST 0 9 REPEAT Repetitive operations RW 0 ...

Page 279: ...e Write a 0 to the DMA_CCR EN bit the channel immediately stops Write a 0 to the DMA_CCR AUTO_INIT bit the channel completes the current transfer and stops 7 EN Enable This bit is used to enable disable the transfer in the DMA channel RW RST 0 0 The transfer stops and it is reset 1 The transfer starts This bit is automatically cleared by the DMA once the transfer is accomplished Clearing of this b...

Page 280: ...nterleaved on the DMA port with other channel requests 1 An entire frame is transferred each time a DMA request is made This frame can be interleaved on the DMA ports with other channel requests 4 0 SYNC Synchronization control This field is used to specify the external DMA request which can trigger the transfer in this channel One DMA request among 15 possible can be chosen The values for this fi...

Page 281: ...el does not interrupt the processor when the transfer of the current frame completes 1 The channel sends an interrupt to the processor when the transfer of the current frame completes 2 HALF_IE Half frame interrupt enable RW 0 0 The channel does not interrupt the processor when the transfer of the first half of the current frame completes 1 The channel sends an interrupt to the processor when the ...

Page 282: ...terrupt enable bit is set the channel sends an interrupt to the processor At the same time the correspond ing status bit is set in DMA_CSR DMA channel status register or in DMA_TSR DMA time out error status register A status bit is not set if the corresponding interrupt enable bit in DMA_CICR equals 0 Table 5 15 DMA Channel Status Register DMA_CSR Bit Name Value Description Type Reset Value 15 14 ...

Page 283: ... not finished yet 1 The current transfer in the channel is finished another one may have start if DMA_CCR2 AUTOINIT 1 4 LAST Last frame R 0 0 Last frame did not start yet 1 The transfer of the last frame has started 3 FRAME Frame R 0 0 Transfer of the current frame still in progress 1 A complete frame was transferred 2 HALF Half frame R 0 0 First half of the current frame not transferred yet 1 Fir...

Page 284: ...CSSA_L Bit Name Description Type Reset Value 15 0 Source start address lower bits Lower bits of the source start address expressed in bytes The source start address output by the DMA is an up to 32 bit byte address made of the concatenation of DMA_CSSA_U and DMA_CSSA_L RW Undefined Table 5 17 DMA Channel Source Start Address Upper Bits Register DMA_CSSA_U Bit Name Description Type Reset Value 15 0...

Page 285: ...number is 65535 RW Undefined Table 5 21 DMA Channel Frame Number Register DMA_CFN Bit Name Description Type Reset Value 15 0 Channel frame number Number of frames within the block to transfer The maximum frame number is 65535 The size in bytes of the data block to transfer is DMA_CFN x DMA_CEN x DMA_CES This size is programmed in bytes to Allow transfer of an odd byte number Accommodate the requir...

Page 286: ... the last request for an element If the channel transfer is synchronized on frames DMA_CCR SYNC 0 and DMA_CCR FS 1 or not synchronized DMA_CCR SYNC 0 the register is updated with 16 LSB of the address each time the destination port issues the last request for a frame R Undefined The DMA LCD control register contains seven bits that control the LCD chan nel operation There are two cases of interrup...

Page 287: ...ad R R 0 0 No bus error interrupt detected 1 Bus error interrupt detected 4 FRAME_2_ IT_COND Status LCD channel register must be reset after read R R 0 0 No end of frame 2 interrupt detected 1 End of frame 2 interrupt detected 3 FRAME_1_ IT_COND Status LCD channel register must be reset after read R R 0 0 No end of frame 1 interrupt detected 1 End of frame 1 interrupt detected 2 BUS_ERROR_ IT_IE B...

Page 288: ...uffer 1 The 32 bit address is obtained by the concatenation of the two 16 bit words as described here LCD_TOP_F1 DMA_LCD_TOP_F1_U DMA_LCD_TOP_F1_L Note LSB of the 32 bit word is equal to zero Address of video buffer must always be even Table 5 26 LCD Top Address for Frame Buffer 1 Lower Bits Register DMA_LCD_TOP_F1_L Bit Name Description Type Reset Value 15 1 LCD_TOP_F1_ L 15 1 LCD top address for...

Page 289: ...it word is equal to zero Address of video buffer must always be even Table 5 28 LCD Bottom Address for Frame Buffer 1 Register Lower Bits Register DMA_LCD_BOT_F1_L Bit Name Description Type Reset Value 15 1 LCD_BOT_F1_ L 15 1 LCD bottom address for frame buffer 1 lower bits 15 1 RW Undefined 0 LCD_BOT_F1_ L 0 Address bit 0 Fixed at 0 since address must be even R 0 Table 5 29 LCD Bottom Address for...

Page 290: ...Note LSB of the 32 bit word is equal to zero Address of video buffer must always be even Table 5 30 LCD Top Address for Frame Buffer 2 Lower Bits Register DMA_LCD_TOP_F2_L Bit Name Description Type Reset Value 15 1 LCD_TOP_F2_ L 15 1 LCD top address for frame buffer 2 lower bits 15 1 RW Undefined 0 LCD_TOP_F2_ L 0 Address bit 0 Fixed at 0 since address must be even R 0 Table 5 31 LCD Top Address f...

Page 291: ...f the 32 bit word is equal to zero Address of video buffer must always be even Table 5 32 LCD Bottom Address for Frame Buffer 2 Lower Bits Register DMA_LCD_BOT_F2_L Bit Name Description Type Reset Value 15 1 LCD_BOT_F2_ L 15 1 LCD bottom address for frame buffer 2 lower bits 15 1 RW Undefined 0 LCD_BOT_F2_ L 0 Address bit 0 Fixed at 0 since address must be even R 0 Table 5 33 LCD Bottom Address fo...

Page 292: ...age 6 1 Overview 6 2 6 2 Timer Description 6 3 6 3 Watchdog Timer 6 8 6 4 MPU Interrupt Handlers 6 14 6 5 Level 1 and Level 2 Interrupt Mapping 6 17 6 6 Interrupt Handler Level 1 and Level 2 Registers 6 20 6 7 Configuration Module 6 24 6 8 OMAP5910 Configuration Registers 6 27 6 9 Device Identification 6 70 Chapter 6 ...

Page 293: ...dge LCD I F MPU interface SRAM SDRAM memories Flash and SRAM memories DSP MMU 16 16 32 16 32 32 32 32 32 32 16 MPU private peripheral bus DSP public shared peripheral bus 32 MPU public 16 DSP DSP public peripherals McBSP1 McBSP3 MPU public peripherals USB host I F JTAG emulation I F OSC 12 MHz Clock OSC OMAP5910 ETM9 Timers 3 MPU DSP shared peripherals Mailbox MPU private peripherals Timers 3 16 M...

Page 294: ...TIM CLK CLK 2 PTV 1 If autoreload then load when timer underflows IRQ when timer underflows 32 bit timer Timer 1 IRQ_26 Timer 2 IRQ_30 Timer 3 IRQ_16 MPUTIM_CK 12 MHz Load when timer starts Table 6 1 identifies the level 1 interrupts for the three 32 bit timers Table 6 1 Timer Level 1 Interrupt Timer Corresponding Level 1 Interrupt 1 IRQ_26 2 IRQ_30 3 IRQ_16 The timers are 32 bit counters that rec...

Page 295: ...r when it starts and PTV is the prescaler field located in the control timer register CNTL_TIMER tint tclk X LOAD_TIM 1 x 2 PTV 1 Table 6 3 shows the timer characteristics for the three timers for different input frequencies Table 6 3 Timer Characteristics Input Clock tclk Clock Period LOAD_TIM tint Timer Interrupt Period for PTV 0 tint Timer Interrupt Period for PTV 7 100 MHz 10 ns 0000 0001 40 n...

Page 296: ...resetting this bit to 0 When the timer is stopped the content of the decrementer is frozen If the autoreload bit is disabled AR field of control timer register CNTL_TIM ER is 0 the timer decrements from the loaded value down to zero and then stops If the autoreload bit is enabled AR 1 the timer continues A new value from the load register is loaded into the timer when it passes though zero or when...

Page 297: ...ions R W Size Offset Reset Value CNTL_TIMER Control timer R W 32 bits x00 0x0000 0000 LOAD_TIM Load timer W 32 bits x04 U READ_TIM Read timer R 32 bits x08 U Table 6 5 Control Timer Register CNTL_TIMER Bits Name Value Description Reset Value 31 7 RESERVED 6 FREE FREE bit 0 0 Timer stops counting in suspend mode 1 Timer continues counting in suspend mode 5 CLOCK_ENABLE External timer clock enable 0...

Page 298: ...ter LOAD_TIMER Bit Name Description Reset Value 31 0 LOAD_TIM The value is loaded into the VALUE_TIM when the timer passes through 0 or when it starts Undefined Table 6 7 Read Timer Register READ_TIMER Bit Name Description Reset Value 31 0 VALUE_TIM Value of timer Undefined ...

Page 299: ...cts user programs stuck in an infinite loop loss of program control or a runaway condition When used as a general purpose timer the watchdog timer is a 16 bit timer configurable either in autoreload or one shot mode with on the fly read capability The timer generates an interrupt to the TI925T RISC processor when the count passes through zero see Figure 6 5 Figure 6 4 Watchdog Timer Divide clock d...

Page 300: ...y 19 seconds The watchdog timer uses a special clock from the MPU clock frequency gener ation module CLKM1 This clock is CLKIN 14 When configured as a watch dog timer the prescaler field PTV of CNTL_TIMER reference is fixed at 7 When configured as a general purpose timer the prescaler field can range from 0 to 7 The time from writing a new value to counter underflow is between 256 Tclk to 16 777 2...

Page 301: ...user a time of 16 777 216 tclk 19 57 seconds to change the timer mode or write a new value different from 0xFFFF into the LOAD_TIM register The user program or the OS must write periodically to the count register LOAD_TIM before the counter underflows The new loaded value must be different from the previous value because the write is taken into account only if the newly loaded value is different f...

Page 302: ... started by setting the ST field of the control timer register CNTL_TIMER to 1 It is stopped by resetting this bit to 0 When the timer is stopped the content of the decrementer is frozen If the autoreload bit is disabled the AR field of control timer register CNTL_TIMER is 0 the timer decrements from the loaded value down to zero and then stops If the autoreload bit is enabled AR 1 the timer conti...

Page 303: ...IMER Control timer R W 16 bits x00 0x0002 LOAD_TIM Load timer W 16 bits X04 0xFFFF READ_TIM Read timer R 16 bits X04 0xFFFF TIMER_MODE Timer mode R W 16 bits X08 0x8000 Table 6 12 Control Timer Register CNTL_TIMER Bits Name Value Description Reset Value 15 12 RESERVED 11 9 PTV Prescale clock timer value 0 8 AR 0 One shot timer 0 1 Autoreload timer 7 ST 0 Stop timer 0 1 Start timer 6 2 RESERVED 1 F...

Page 304: ...D_TIM Bit Name Description Reset Value 15 0 VALUE_TIM Read timer value FFFF Table 6 15 Timer Mode Register TIMER_MODE Bit Name Value Description Reset Value 15 WATCHDOG Write access 1 1 Switchback timer mode to watchdog Writing a 0 in this bit has no effect 14 8 RESERVED 7 0 WATCHDOG_DIS Write access only Writing a predefined sequence 0xF5 followed by 0xA0 in this field disables the watchdog Funct...

Page 305: ... not support nested interrupts 6 4 1 MPU Level 1 Interrupt Handler The MPU level 1 interrupt handler has 32 interrupt request lines IRQ_ 31 0 These interrupts are generated by peripherals such as the timers camera LCD the system DMA controller and the DSP The interrupt handler handles edge triggered or level sensitive interrupts individually programmable via the ILRn registers see Table 6 23 All i...

Page 306: ... alarm IRQ 26 Reserved IRQ 27 USB function ISO on IRQ 29 DSP MMU IRQ 28 USB funciton non ISO on IRQ 30 McBSP2 receive overflow IRQ 31 IRQ from Level2 Camera interrupt Level 1 Interrupt Handler IRQ 1 IRQ 0 IRQ 2 IRQ 3 IRQ 5 IRQ 4 IRQ 6 IRQ 7 IRQ 9 IRQ 8 IRQ 10 IRQ 11 IRQ 13 IRQ 12 IRQ 14 IRQ 15 IRQ 17 IRQ 16 IRQ 18 IRQ 19 IRQ 21 IRQ 20 IRQ 22 IRQ 23 IRQ 25 IRQ 24 IRQ 26 IRQ 27 IRQ 29 IRQ 28 IRQ 30 ...

Page 307: ...y the level 2 interrupt handler as indicated by an IRQ of 0 read the SIR_IRQ_CODE register of the level 2 interrupt handler Step 3 If the interrupt is a level interrupt the corresponding interrupt routine must first clear the interrupt source usually by writing to a register in the module generating the interrupt or at least mask the interrupt Then it must write 1 into the NEW_IRQ_AGR field of the...

Page 308: ...nterrupt Line on Level 2 Level 2 interrupt handler IRQ Level IRQ_0 Camera interrupt Level IRQ_1 Reserved IRQ_2 External FIQ Edge IRQ_3 McBSP2 TX interrupt Edge IRQ_4 McBSP2 RX interrupt Edge IRQ_5 IRQ_RTDX Level IRQ_6 IRQ_DSP_MMU_ABORT Level IRQ_7 IRQ_HOST_INT Level IRQ_8 IRQ_ABORT Level IRQ_9 IRQ_DSP_MAILBOX1 Level IRQ_10 IRQ_DSP_MAILBOX2 Level IRQ_11 Reserved IRQ_TIPB_BRIDGE_PRIVATE Level IRQ_13...

Page 309: ...F Level IRQ_29 IRQ_TIMER2 Edge IRQ_30 IRQ_LCD_CTRL Level IRQ_31 FAC Level IRQ0 IRQ_00 Keyboard Edge IRQ0 IRQ_01 MicroWire TX Edge IRQ0 IRQ_02 MicroWire RX Edge IRQ0 IRQ_03 I2C Edge IRQ0 IRQ_04 MPUIO Level IRQ0 IRQ_05 USB HHC 1 Level IRQ0 IRQ_06 Reserved IRQ0 IRQ_07 Reserved IRQ0 IRQ_08 Reserved IRQ0 IRQ_09 McBSP3 TX interrupt Edge IRQ0 IRQ_10 McBSP3 RX interrupt Edge IRQ0 IRQ_11 McBSP1 TX interrup...

Page 310: ...Q0 IRQ_22 MMC interrupt Level IRQ0 IRQ_23 ULPD interrupt Level IRQ0 IRQ_24 RTC periodical timer Edge IRQ0 IRQ_25 RTC alarm Level IRQ0 IRQ_26 Reserved IRQ0 IRQ_27 DSPMMU IRQ IRQ0 IRQ_28 USB function IRQ ISO On Level IRQ0 IRQ_29 USB function IRQ Non ISO On Level IRQ0 IRQ_30 McBSP2 RX OVERFLOW It Edge IRQ0 IRQ_31 IRQ_RTDX is used in emulation for the Code Composer Studio RTDX real time data exchange ...

Page 311: ...R W 2 bits 0X18 0x0 ILR0 Interrupt priority level for IRQ 0 R W 7 bits 0X1C 0x00 ILR1 Interrupt priority level for IRQ 1 R W 7 bits 0X20 0x00 ILR2 Interrupt priority level for IRQ 2 R W 7 bits 0X24 0x00 ILR3 Interrupt priority level for IRQ 3 R W 7 bits 0X28 0x00 ILR4 Interrupt priority level for IRQ 4 R W 7 bits 0X2C 0x00 ILR5 Interrupt priority level for IRQ 5 R W 7 bits 0X30 0x00 ILR6 Interrupt...

Page 312: ...21 Interrupt priority level for IRQ 21 R W 7 bits 0X70 0x00 ILR22 Interrupt priority level for IRQ 22 R W 7 bits 0X74 0x00 ILR23 Interrupt priority level for IRQ 23 R W 7 bits 0X78 0x00 ILR24 Interrupt priority level for IRQ 24 R W 7 bits 0X7C 0x00 ILR25 Interrupt priority level for IRQ 25 R W 7 bits 0X80 0x00 ILR26 Interrupt priority level for IRQ 26 R W 7 bits 0X84 0x00 ILR27 Interrupt priority ...

Page 313: ...masks some interrupts to ignore specific interrupts 0 30 0 IRQ_30 IRQ_0 Same as bit 31 0 Table 6 19 Mask Interrupt Register MIR Bit Name Description Reset Value 31 IRQ_31_MSK Interrupt mask bit 1 prevents IRQ_31 from interrupting MPU program flow If the peripheral on IRQ_31 has been configured to request an interrupt but masked out in this register the IRQ_31 bit in the IRQ register is still set o...

Page 314: ... NEW_IRQ_REG New IRQ agreement Writing a 1 resets IRQ output clears source IRQ register and enables new IRQ generation 0 Table 6 23 Interrupt Level Registers ILR0 ILR31 Bit Name Value Description Reset Value 6 2 PRIORITY Defines the priority level when the corresponding interrupt is routed to IRQ or FIQ 31 down to 0 0 1 SENS_EDGE 0 Interrupt is falling edge triggered 0 1 Interrupt is low level tri...

Page 315: ...e module is a bank of 32 bit registers that can be read and written by firmware This bank of registers can be broken down into eight primary sections These are OMAP5910 generic multiplexing registers 0x0010h to 0x0038h address range OMAP5910 pullup pulldown control registers 0x0040h to 0x004Ch address range OMAP5910 gating and inhibiting registers 0x0050h address range OMAP5910 voltage control reg...

Page 316: ... writes then to enable all of the modes simultaneously 6 7 3 OMAP5910 Generic Pin Multiplexing and Pullup Pulldown Control The OMAP5910 configuration module was developed with future versions of OMAP5910 in mind To enable software compatibility between OMAP5910 and future versions this module allows for up to eight multiplexing options on all device pins and independent pin by pin pulldown control...

Page 317: ...l case on the OMAP5910 device The MMC SD pin interface uses the state of a device pin STAT_VAL WKUP at release of power on reset to determine if the MMC SD function is enabled at the device s pins The power on reset sam pling of a high level on this pin forces the device s I O into a state that is consis tent with MMC SD This means that several pullups are enabled when in MMC SD mode Users must pr...

Page 318: ..._CTRL_3 Functional multiplexing control 3 0x10 FUNC_MUX_CTRL_4 Functional multiplexing control 4 0x14 FUNC_MUX_CTRL_5 Functional multiplexing control 5 0x18 FUNC_MUX_CTRL_6 Functional multiplexing control 6 0x1C FUNC_MUX_CTRL_7 Functional multiplexing control 7 0x20 FUNC_MUX_CTRL_8 Functional multiplexing control 8 0x24 FUNC_MUX_CTRL_9 Functional multiplexing control 9 0x28 FUNC_MUX_CTRL_A Functio...

Page 319: ... native modes 30 23 RESERVED Reserved These bits must always be written as 0 R W 0x0 22 LB_RESET_DISABLE This bit holds the OMAP local bus reset input active Set this to 1 when using OMAP5910 USB_HHC module R W 0x0 0 Local bus RESET 0 1 Local bus RESET USB_HHC LB reset This bit is valid in compatibility and native modes 21 RESERVED Reserved This bit must always be written as 0 R W 0x0 20 LRU_SEL T...

Page 320: ...rl input source used for USB insertion disconnection detection R W 0x0 0 USB input vbus_ctrl Hardware detection see bit i7 of the MOD_CONF_CTRL_0 register 1 USB input vbus_ctrl OMAP5910 configuration VBUS_CTRL bit 17 15 RESERVED Reserved These bits must always be written as 0 R W 0x0 14 NRESET_ENABLE Allows AND gating of OMAP5910 outputs with the OMAP CHIP_NRESET_OUT R W 0x0 0 Disabled 1 Allowed T...

Page 321: ... AND gating of OMAP5910 inputs with BFAIL EXT_FIQ OMAP5910 input pin R W 0x0 1 Allows AND gating of OMAP5910 inputs with BFAIL EXT_FIQ OMAP5910 input pin This bit is valid in compatibility and native modes 10 BVLZ_MASK_OUT 0 Does not allow AND gating of outputs with BFAIL EXT_FIQ OMAP5910 input pin R W 0x0 1 Allows AND gating of outputs with BFAIL EXT_FIQ OMAP5910 input pin This bit is valid in co...

Page 322: ...it field can be used to control the interrupt observability mux When a 7 bit value is written in this field the corre sponding interrupt signal is output on the UART3 TX pin for visibility Legal values are from 0 to 101 0 is the functional mode values between 1 and 101 are for observability mode 0 Default for i in 1 to 16 observability UART3 TX pin DSP level2 interrupt i 1 for i in 17 to 37 observ...

Page 323: ...xing Control 3 Register FUNC_MUX_CTRL_3 Bits Name Description R W Reset Value 31 0 RESERVED Reserved for future expansion These bits must always be written as 0 R W 0x0 Table 6 32 Functional Multiplexing Control 4 Register FUNC_MUX_CTRL_4 Bits Name Description R W Reset Value 31 30 RESERVED Reserved for future expansion These bits must always be written as 0 R W 0x0 29 27 CONF_CAM_D_7_R These bits...

Page 324: ...set The control for this I O is forced to 000 at reset and while in compatibility mode R W 0x0 14 12 CONF_MCBSP1_SYNC_R These bits control the multiplexing on the OMAP5910 I O which defaults to MCBSP1 FSX at reset The control for this I O is forced to 000 at reset and while in compatibility mode R W 0x0 11 0 RESERVED Reserved for future expansion These bits must always be written as 0 R W 0x0 Tabl...

Page 325: ...ontrol for this I O is forced to 000 at reset and in compatibility mode R W 0x0 17 15 CONF_CAM_D_1_R These bits control the multiplexing on the OMAP5910 I O which defaults to CAM D 1 at reset The control for this I O is forced to 000 at reset and in compatibility mode R W 0x0 14 12 CONF_CAM_D_2_R These bits control the multiplexing on the OMAP5910 I O which defaults to CAM D 2 at reset The control...

Page 326: ...ESERVED Reserved for future expansion These bits must always be written as 0 R W 0x0 29 27 CONF_GPIO_4_R These bits control the multiplexing on the OMAP5910 I O which defaults to GPIO4 at reset The control for this I O is forced to 000 at reset and while in compatibility mode R W 0x0 26 24 CONF_GPIO_6_R These bits control the multiplexing on the OMAP5910 I O which defaults to GPIO6 at reset The co...

Page 327: ...PIO_14_R These bits control the multiplexing on the OMAP5910 I O which defaults to GPIO14 at reset The control for this I O is forced to 000 at reset and while in compatibility mode R W 0x0 8 6 CONF_GPIO_15_R These bits control the multiplexing on the OMAP5910 I O which defaults to GPIO15 at reset The control for this I O is forced to 000 at reset and while in compatibility mode R W 0x0 5 3 CONF_R...

Page 328: ... OMAP5910 I O which defaults to MPUIO5 at reset The control for this I O is forced to 000 at reset and while in compatibility mode R W 0x0 11 9 CONF_GPIO_0_R These bits control the multiplexing on the OMAP5910 I O which defaults to GPIO0 at reset The control for this I O is forced to 000 at reset and while in compatibility mode R W 0x0 8 6 CONF_GPIO_1_R These bits control the multiplexing on the O...

Page 329: ...r this I O is forced to 000 at reset and in compatibility mode R W 0x0 11 9 CONF_WIRE_NSCS0_R These bits control the multiplexing on the OMAP5910 I O which defaults to UWIRE CS0 at reset The control for this I O is forced to 000 at reset and in compatibility mode R W 0x0 8 6 CONF_WIRE_SCLK_R These bits control the multiplexing on the OMAP5910 I O which defaults to UWIRE SCLK at reset The control f...

Page 330: ...on the OMAP5910 I O which defaults to UART1 TX at reset The control for this I O is forced to 000 at reset and in compatibility mode R W 0x0 20 15 RESERVED Reserved for future expansion These bits must always be written as 0 R W 0x0 14 12 CONF_RTS1_R These bits control the multiplexing on the OMAP5910 I O which defaults to UART1 RTS at reset The control for this I O is forced to 000 at reset and i...

Page 331: ... to MMC DAT2 at reset As long as the STATIC_VALID pin is sampled high upon reset the control for this I O is force to 000 at reset and while in compatibility mode STATIC_VALID must sample high at reset for the associated OMAP5910 pin to function properly R W 0x0 17 15 RESERVED Reserved for future expansion These bits must always be written as 0 R W 0x0 14 12 CONF_CLK32K_OUT_R These bits control th...

Page 332: ...RL_B Bits Name Description R W Reset Value 31 21 RESERVED Reserved for future expansion These bits must always be written as 0 R W 0x0 20 18 CONF_COM_MCLK_REQ_R These bits control the multiplexing on the OMAP5910 I O which defaults to UART2 CLKREQ at reset The control for this I O is forced to 000 at reset and while in compatibility mode R W 0x0 17 15 RESERVED Reserved for future expansion These b...

Page 333: ...ys be written as 0 R W 0x0 Table 6 40 Functional Multiplexing Control C Register FUNC_MUX_CTRL_C Bits Name Description R W Reset Value 31 30 RESERVED Reserved for future expansion These bits must always be written as 0 R W 0x0 29 27 CONF_TX2_R These bits control the multiplexing on the OMAP5910 I O which defaults to UART2 TX at reset The control for this I O is forced to 000 at reset and in compat...

Page 334: ...ONF_MCBSP2_RSYNC_R These bits control the multiplexing on the OMAP5910 I O which defaults to MCBSP2 FSR at reset The control for this I O is forced to 000 at reset and while in compatibility mode R W 0x0 11 9 RESERVED Reserved for future expansion These bits must always be written as 0 R W 0x0 8 6 CONF_MCBSP2_CLKR_R These bits control the multiplexing on the OMAP5910 I O which defaults to MCBSP2 C...

Page 335: ...l the multiplexing on the OMAP5910 I O which defaults to MMC DAT3 at reset The control for this I O is forced to 000 at reset R W 0x0 11 9 RESERVED Reserved for future expansion These bits must always be written as 0 R W 0x0 8 6 CONF_NFCS2_R These bits control the multiplexing on the OMAP5910 I O which defaults to FLASH CS2 at reset The control for this I O is forced to 000 at reset R W 0x0 5 0 RE...

Page 336: ... disabled 23 CONF_PDEN_CAM_D_3_R These bits control the pulldown en able on the OMAP5910 I O which defaults to CAM D 3 at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled 22 RESERVED Reserved for future expansion These bits must always be written as 0 R W 0x0 21 CONF_PDEN_CAM_D_5_R These bits control the pulldown en able on the OMAP5910 I O which defaults to CAM D 5 at reset R W 0x0 0 Pulldown...

Page 337: ...x A of this document or the OMAP5910 data manual literature number SPRS197 to determine whether a pulldown exists for each I O Table 6 43 Pulldown Control 1 Register PULL_DWN_CTRL_1 Bit Name Value Description See Note R W Reset Value 31 30 RESERVED Reserved for future expansion These bits must always be written as 0 R W 0x0 29 CONF_PDEN_MCBSP3_CLK_R This bit controls the pulldown enable on the OMA...

Page 338: ...efaults to EMU0 at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled 24 19 RESERVED Reserved for future expansion These bits must always be written as 0 R W 0x0 18 CONF_PDEN_WIRE_SDI_R This bit controls the pulldown enable on the OMAP5910 I O which defaults to UWIRE SDI at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled 17 15 PULLDOWN Reserved for future expansion These bits must always be...

Page 339: ...control for this pulldown is forced on at reset and while in compatibility mode 12 CONF_PDEN_ARMIO_5_R This bit controls the pulldown enable on the OMAP5910 I O which defaults to MPUIO5 at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled The control for this pulldown is forced on at reset and while in compatibility mode Note Unless otherwise indicated pulldown control for each I O is forced of...

Page 340: ...sabled The control for this pulldown is forced on at reset and while in compatibility mode 9 CONF_PDEN_GPIO_2_R This bit controls the pulldown enable on the OMAP5910 I O which defaults to GPIO2 at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled The control for this pulldown is forced on at reset and while in compatibility mode Note Unless otherwise indicated pulldown control for each I O is f...

Page 341: ...ntrol for this pulldown is forced on at reset and while in compatibility mode 6 CONF_PDEN_GPIO_6_R This bit controls the pulldown enable on the OMAP5910 I O which defaults to GPIO6 at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled The control for this pulldown is forced on at reset and while in compatibility mode Note Unless otherwise indicated pulldown control for each I O is forced off at ...

Page 342: ...abled The control for this pulldown is forced on at reset and while in compatibility mode 3 CONF_PDEN_GPIO_12_R This bit controls the pulldown enable on the OMAP5910 I O which defaults to GPIO12 at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled The control for this pulldown is forced on at reset and while in compatibility mode Note Unless otherwise indicated pulldown control for each I O is ...

Page 343: ...ontrol for this pulldown is forced on at reset and while in compatibility mode 0 CONF_PDEN_GPIO_15_R This bit controls the pulldown enable on the OMAP5910 I O which defaults to GPIO15 at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled The control for this pulldown is forced on at reset and while in compatibility mode Note Unless otherwise indicated pulldown control for each I O is forced off ...

Page 344: ...10 I O which defaults to MCBSP2 CLKX at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled The control for this pulldown is forced on at reset and while in compatibility mode 28 CONF_PDEN_MCBSP2_ CLKR_R This bit controls the pulldown enable on the OMAP5910 I O which defaults to MCBSP2 CLKR at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled Note Unless otherwise indicated pulldown control fo...

Page 345: ... I O which defaults to MPUIO3 at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled The control for this pulldown is forced on at reset and while in compatibility mode 24 CONF_PDEN_GPIO_8_R This bit controls the pulldown enable on the OMAP5910 I O which defaults to GPIO 8 at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled The control for this pulldown is forced on at reset and while in comp...

Page 346: ...ion These bits must always be written as 0 R W 0x0 20 CONF_PDEN_MCSI2_ SYNC_R This bit controls the pulldown enable on the OMAP5910 I O which defaults to MCSI2 SYNC at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled 19 RESERVED Reserved for future expansion These bits must always be written as 0 R W 0x0 18 CONF_PDEN_MCSI2_ DIN_R This bit controls the pulldown enable on the OMAP5910 I O which ...

Page 347: ... CONF_PDEN_MMC_ DAT1_R This bit controls the pullup enable on the OMAP5910 I O which defaults to MMC DAT1 at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled 13 RESERVED Reserved for future expansion These bits must always be written as 0 R W 0x0 12 CONF_PDEN_MMC_ DAT2_R This bit controls the pulldown enable on the OMAP5910 I O which defaults to MMC DAT2 at reset R W 0x0 0 Pulldown enabled 1 P...

Page 348: ...d on at reset and while in compatibility mode 7 CONF_PDEN_MCSI1_ SYNC_R This bit controls the pulldown enable on the OMAP5910 I O which defaults to MCSI1 SYNC at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled The control for this pulldown is forced on at reset and while in compatibility mode 6 CONF_PDEN_UARTS_ CLKIO_R Reserved for future expansion These bits must always be written as 0 R W 0...

Page 349: ...I O which defaults to UART1 RX at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled 1 CONF_PDEN_R_R This bit controls the pulldown enable on the OMAP5910 I O which defaults to UART1 CTS at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled 0 RESERVED Reserved for future expansion These bits must always be written as 0 R W 0x0 Note Unless otherwise indicated pulldown control for each I O is fo...

Page 350: ... CONF_PDEN_TCK_R This bit controls the pulldown enable on the OMAP5910 I O which defaults to TCK at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled 11 CONF_PDEN_TMS_R This bit controls the pulldown enable on the OMAP5910 I O which defaults to TMS at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled 10 CONF_PDEN_TDI_R This bit controls the pulldown enable on the OMAP5910 I O which defaults ...

Page 351: ... This bit controls the pulldown enable on the OMAP5910 I O which defaults to UART2 CTS at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled 0 CONF_PDEN_RX2_R This bit controls the pulldown enable on the OMAP5910 I O which defaults to UART2 RX at reset R W 0x0 0 Pulldown enabled 1 Pulldown disabled Table 6 46 Gate and Inhibit Control 0 Register GATE_INH_CTRL_0 Bit Name Value Description R W Rese...

Page 352: ...mpatibility mode R W 0x0 1 CONF_ SOFTWARE_BVLZ_R This bit controls software gating and inhibiting of the OMAP5910 I O which are gated or inhibited by BFAIL EXT_FIQ If the gating and inhibiting logic are enabled by FUNC_MUX_CTRL_0 10 13 bits and conf_software_gate_ena_r is set to 1 this bit controls the BFAIL EXT_FIQ gating and inhibiting instead of device pins This bit has no effect in compatibili...

Page 353: ... at 1 8 V nom or 2 75 V nom R W 0x0 0 Drive strength is 1 80 V 1 Drive strength is 2 75 V At reset and in compatibility mode the interface is set for 2 75 V operation This register only controls the interface in OMAP5910 mode 1 CONF_VOLTAGE_SDRAM_R This bit controls the drive strength of the OMAP5910 SDRAM interface I O This allows the interface to be run at 1 8 V nom or 2 75 V nom R W 0x0 0 Drive...

Page 354: ... interface to be run at 1 8 V nom or 2 75 V nom R W 0x0 0 Drive strength is 1 80 V 1 Drive strength is 2 75 V At reset and in compatibility mode the interface is set for 2 75 V operation This register only controls the interface in OMAP5910 mode Table 6 48 Test Debug Control 0 Register TEST_DBG_CTRL_0 Bit Name Description R W Reset Value 31 0 RESERVED These register is reserved for factory testing...

Page 355: ...ART1 on the OMAP5910 device R W 0x0 0 12 MHz 1 48 MHz 28 MOD_MCBSP3_MODE_R This bit determines the method of frame synchronization wrap around used on MCBSP3 R W 0x0 0 Wrap around done in hardware external to the McBSP 1 Wrap around disabled Wrap around can be performed within the McBSP module Modes documented in Chapter 9 DSP Public Peripherals 27 24 MOD_32KOSC_SW_R These bits determine the confi...

Page 356: ...terfaced to the flash interface of OMAP5910 21 CONF_MOD_MSMMC_ VSS_HIZ_OVERRIDE This bit disables the forced HI Z on the the MMC DAT2 pin of the device In order to use this pin in a functional mode the user must set this bit to a 1 R W 0x0 20 CONF_MOD_MCBSP3_ AUXON This bit enables the McBSP3 AUXON functionality which gates the functional clock to the corresponding McBSP module R W 0x0 0 The inter...

Page 357: ...f the GPIO0 input 1 The VBUS detection is under control of the VBUS detection I O cell This bit resets to 0 during reset and compatibility mode 16 CONF_MOD_I2C_ SELECT_R This bit selects the I2C module compatibility mode This bit resets to standard mode R W 0x0 0 The I2C module is in standard mode 1 The I2C module is in compatibility mode 15 14 RESERVED Reserved for future expansion These bits mus...

Page 358: ...Hz DPLL R W 0x0 11 CONF_MOD_USB_HOST_ UART_SELECT_R This bit enables the multiplexing of UART1 CTS UART1 RX and UART1 TX signals to the USB_HMC host mux module R W 0x0 0 UART1 uses the standard source location as defined by the OMAP5910 functional multiplexing 1 UART1 TX UART1 RX and UART1 CTS1 are sourced from the USB_HMC module For details on this multiplexing please see the USB_HMC spec 10 RESE...

Page 359: ... or internal D signal The pullup is only modeled when HMC_TLL_ATTACH_I is active This signal is ignored when either device drives USB data and whenever HMC_MODE or HMC_JTAG_EN_I specify that the TLL is not being used R W 0x0 0 When HMC_TLL_ATTACH_I is high the TLL is enabled and neither the USB host nor the external USB device attempts to drive the pullup is modeled on the D signal to indicate a l...

Page 360: ... USB data R W 0x0 0 When neither the USB host nor the external USB device attempts to drive no pullup is modeled The associated USB host port interprets this as no attached device 1 When neither the USB host nor the external USB device attempts to drive a pullup is modeled on either the internal representation of D or D The associated USB host port interprets this as attached device with the bus i...

Page 361: ... 16 bits 27 to 12 Manufacturer Identity 11 bits 11 to 1 Fixed LSB 1 bit LSB 0 Table 6 50 ID Code Register IDCODE Register Name Size Access Capture Value Address IDCODE 32 R See below FFFE D404 The TI manufacturer identity is IEEE WW defined as 000 0001 0111 For OMAP5910 design ID code xxxx 1011 0100 0111 0000 0000 0010 1111 xb47002f The IDCODE register bits are described in Table 6 51 Table 6 51 I...

Page 362: ...ID is a 64 bit code Of these 56 bits bits 0 55 are data bits that con tain x and y coordinates of the die wafer number lot number and manufactur ing number Eight bits bits 56 63 are check bits computed using a Hamming code The die ID can be read by software via the private TIPB see Table 6 52 Table 6 52 Die ID Address Space Private TIPB Bridge Device Name Start Address Size in Bytes Data Access OM...

Page 363: ...kHz Timer 7 46 7 6 Pseudonoise Pulse Width Light Modulator 7 50 7 7 Pulse Width Tone 7 52 7 8 Inter Integrated Circuit Controller 7 57 7 9 LED Pulse Generator 7 100 7 10 McBSP2 7 104 7 11 USB Function Overview 7 117 7 12 MMC SD Host Controller 7 120 7 13 Real Time Clock 7 169 7 14 USB Host Controller Overview 7 185 7 15 HDQ and 1 Wire Protocols 7 185 7 16 Frame Adjustment Counter 7 198 Chapter 7 ...

Page 364: ...ls McBSP1 McBSP3 MPU public peripherals USB host I F JTAG emulation I F OSC 12 MHz Clock OSC OMAP5910 ETM9 Timers 3 MPU DSP shared peripherals Mailbox MPU private peripherals Timers 3 16 Memory interface Reset External clock MPU bus 32 kHz 1 5M bits Traffic controller TC Watchdog timer Level 1 2 interrupt handlers Configuration registers Clock and reset management Watchdog timer Level 1 2 Private ...

Page 365: ...nsfer it to the MPU peripheral bridge using the DMA mode or the CPU mode It contains a 128 word FIFO The 8 bit data received from the camera module is latched and mixed to be compliant with the 32 bit data format of the MPU TIPB A 128 bit deep FIFO is implemented to provide local buffering of data and to control the DMA request when the camera interface is enabled in DMA mode The main goals of thi...

Page 366: ...igure 7 2 Camera Interface Block Diagram CAM_LCLK CAM_D CAM_VS CAM_HS Interrupt generator Interrupt CAM_NIRQ Clock divider 12 MHz CAM_EXCLK Camera I F AND ENABLE 32 8 TIPB register FIFO TIPB DPLL_REQ DPLL_CLK DMA_REQ status ...

Page 367: ... CAM LCLK configure the interface to catch the data on the falling edge of CAM LCLK The high level of the vertical synchronous and horizontal synchronous signals indicates that the data is valid on CAM_D This level is registered in VSTATUS and HSTATUS which are updated on edge detection of vertical and horizontal synchronous signals It is possible to gate the clock during the VSYNC and or HSYNC bl...

Page 368: ...beginning of the image Note If a reset FIFO occurs see Section 7 2 1 3 while the interface is latching data the capture is automatically disabled and the autostart function is enabled 7 2 1 3 Reset FIFO An active high reset FIFO is implemented at bit 18 RAZ FIFO of the camera mode register This feature clears any remaining data in the FIFO before start ing a new transfer It also resets all status ...

Page 369: ...ch four bytes received from the camera must be packed and can be swapped to follow the order YUV specified in the camera mode register by ORDERCAMD Figure 7 5 Order of Camera Data on TIPB Not Swapped ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Y6 V3 Y5 U3 Y4 V2 Y3 U2 Y2 V1 Y1 U1 U2 Y3 V2 Y4 U1 Y1 V1 Y2 Not swapped TIPB 32 bits CAM D 8 8 bits U1 Bits 31 24 Y1 Bits 23 16 V1 Bits 15 8 Y2 Bits 7 0 Figure 7 6 Order of Camera ...

Page 370: ...A pulse on the DMA request see Figure 7 7 and Figure 7 8 occurs when the number of words in the FIFO is above the threshold The DMA request occurs if the number of remaining words is above the threshold and the system DMA has completed the transfer number of words read by the DMA threshold The camera FIFO continues to fill up to its maximum 128 values when an interrupt or DMA request has been gene...

Page 371: ...ock Divider The clock divider takes the internal 12 MHz clock source or the 48 MHz source from DPLL to generate the external clock CAM EXCLK The division factor is programmable in the clock control register through FOSCMOD see Table 7 1 Table 7 1 Clock Ratios Ratio CAM EXCLK From 12 MHz From 48 MHz 1 12 MHz 1 2 6 MHz 24 MHz 1 5 9 6 MHz 1 6 8 MHz A request is automatically generated to wake up the ...

Page 372: ...sk for a read of the interrupt register When the read occurs the register is automatically reset and the interrupt signal is released Figure 7 9 IRQ Generated on VSYNC Falling Edge ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ VSYNC MCLK RNW CS CAM_NIRQ 7 2 1 8 DMA Procedure A typical procedure to perform the data transfer by DMA is as follows 1 Rising edge of VSYNC sends an interrupt to TI925T to ale...

Page 373: ...ers for communication between the TIPB and camera module They mainly control clock generation interrupt request and status register see Section 7 2 1 10 The address of each register is the start address FFFB 6800 plus the offset indicated in Table 7 3 Table 7 2 shows the default configuration of several critical register fields at reset See Table 7 4 through Table 7 10 for full descriptions of the...

Page 374: ...STATUS Status R 32 bits 0x0C CAMDATA Image data R 32 bits 0x10 GPIO Camera interface GPIO general purpose input output R W 32 bits 0x14 PEAK_COUNTER FIFO peak counter R W 32 bits 0x18 The MCLK_EN bit gates the 12 MHz master clock of the camera interface to disable the clock when switching between two clock domains or to save power consumption when the camera module is not used To clear PEAK_COUNTE...

Page 375: ...served bits R 0xX 5 DATA_TRANSFER Data transfer status Set to 1 when trigger is reached Reset by reading IT_STATUS if no event in the meantime R 0x0 4 FIFO_FULL Detect rising edge on FIFO full flag Reset by reading IT_STATUS if no event in the meantime R 0x0 3 H_DOWN Flag for horizontal synchronous falling edge occurred Reset by reading IT_STATUS if no event in the meantime R 0x0 2 H_UP Flag for h...

Page 376: ...rrupt bypass DMA mode 15 9 THRESHOLD Programmable DMA request trigger value DMA request is made when FIFO counter is equal to the threshold value Currently set this field to 1 in DMA mode R W 0x0000001 8 DMA Enables DMA mode when 1 R W 0x0 7 EN_H_DOWN Enables interrupt on HSYNC falling edge Active when 1 R W 0x0 6 EN_H_UP Enables interrupt on HSYNC rising edge Active when 1 R W 0x0 5 EN_V_DOWN Ena...

Page 377: ... camera interface 0 CAMOSC 0 Set synchronous mode R W 0x0 1 Set asynchronous mode Currently this has no effect on the camera interface Table 7 7 Status Register STATUS Bit Name Function R W Reset Value 31 2 RESERVED Reserved bits R 0xX 1 HSTATUS CAM_HS status edge detection R 0x0 0 VSTATUS CAM_VS status edge detection R 0x0 Table 7 8 Camera Interface GPIO Register GPIO Bit Name Function R W Reset ...

Page 378: ...tocol The CAM EXCLK switch protocol is required for any change of the CAM EXCLK frequency value to first disable both 12 MHz clock source and the DPLL clock source in clock control registers 1 Disable MCLK and DPLL_CLK MCLK_EN 0 DPLL_EN 0 FOSCMOD FOSCMOD 2 Change CAM EXCLK value FOSCMOD new FOSCMOD 3 Enable MCLK and DPLL_CLK MCLK_EN 1 DPLL_EN 1 FOSCMOD FOSCMOD 7 2 2 2 CAM LCLK Switch Protocol Bit ...

Page 379: ...Interrupts The MPU I O module generates two interrupts The keyboard interrupt KEYBOARD_INT used to detect a key press connected to the MPU interrupt handler level2 line1 edge sensitive The GPIO interrupt GPIOS_INT used to detect an edge on one MPUIO input connected to the MPU interrupt handler level2 line5 level sensitive 7 3 2 MPU I O Clocks and Reset The MPU I O module has two clocks The 32 kHz ...

Page 380: ...DDSHV kbr 6 VSS kbr 5 VSS kbr 4 0 VSS Functional Multiplexing mpuio_cntl 5 4 3 2 1 mpuio_out 5 4 3 2 1 mpuio_in 5 4 3 2 1 VSS mpuio_cntl 12 11 7 6 0 mpuio_out 12 11 7 6 0 mpuio_in 12 11 7 6 0 1 2 NOTES 1 These brackets mean that these MPU IOs are not present by default on OMAP5910 pads 2 These Pull downs have dotted line because they don t exist for all these MPU IOs KEYBOARD GPIO WIRE_nSCS3 KBC 6...

Page 381: ...on the corresponding row line generating a keyboard interrupt see Figure 7 11 Once the keyboard interrupt is received the MPU scans the column lines in the sequence described in the Table 7 11 in order to detect the key that has been pressed Table 7 11 Keyboard Scanning Sequence Idle Keyboard Scanning Idle KB C 0 0 1 0 1 1 1 1 1 1 1 0 KB C 2 0 1 1 1 0 1 1 1 1 1 0 KB C 3 0 1 1 1 1 0 1 1 1 1 0 KB C ...

Page 382: ...t mask register KB C 7 0 KB R 7 0 7 3 4 MPUIO General Purpose I O Interface This interface has the following characteristics see Figure 7 12 Every MPUIO can be configured individually either in input or in output mode Interrupt generation GPIOS_INT on edge detection rising or falling after debouncing preprocessing Edge detection can be used to latch all the GPIOs event capture mode GPIO interface ...

Page 383: ...ronously with the 32 kHz system clock clk_32khz These events and consequently the GPIO_INT interrupt are reset on one GPIO interrupt register GPIO_INT read Only the bits that are active after masking are reset The GPIO_INT reset is synchronously asserted and synchronously released with the 32 kHz system clock The GPIO_INT register read and the 32 kHz system clock are resynchronized with the MPU TI...

Page 384: ..._MASKIT can mask the edge detection on the MPU I O inputs This mask is applied asynchronously on each detected edge after debounc ing If all the edges detected are masked then the gpios_int interrupt is masked Masking one MPU I O input forces its corresponding debouncing value to 0 which ensures that gpios_int is generated three cycles after the corresponding detected edge To ensure that this forc...

Page 385: ... 14 MPU I O Input Masking Timing The mask is present two cycles before the active edge on the MPUIO input consequently the debouncing is forced to 0 from the start and the IT must be generated three cycles after the detected edge CLK_32 KHz MPUIO_IN I GPIO_MASKIT I GPIO_MASKIT_SS I after 32 KHz resync GPIOS_INT The IT is masked during this period The GPIO_INT read asynchronously resets the gpios_i...

Page 386: ...BOUNCING_REG in steps of 31 µs The GPIO event mode register GPIO_EVENT_MODE_REG enables or disables the GPIO event mode It also selects the external pin used as the GPIO_CLK The GPIO interrupt edge register GPIO_INT_EDGE selects the GPIO_CLK falling or rising edge to generate the GPIO_INT interrupt When the gpios_int interrupt active low is generated the GPIO_INT register must be read by the MPU t...

Page 387: ...art address in the MPU I O range hex FFFB 5000 Table 7 12 lists the MPU I O registers Table 7 13 through Table 7 25 describe the individual registers Table 7 12 MPU Input Output Registers Register Description R W Size Address Offset INPUT_LATCH General purpose input R 16 bits FFFB 5000 0x00 OUTPUT_REG Output R W 16 bits FFFB 5000 0x04 IO_CNTL Input Output control R W 16 bits FFFB 5000 0x08 KBR_LAT...

Page 388: ...000 0x30 GPIO_LATCH_REG GPIO latch R 16 bits FFFB 5000 0x34 Table 7 13 General Purpose Input Register INPUT_LATCH Bit Name Function Reset Value 15 0 INPUT_LATCH General purpose inputs Reflects input pins Table 7 14 Output Register OUTPUT_REG Bit Name Function Reset Value 15 0 OUTPUT_REG General purpose outputs Undefined Table 7 15 Input Output Control Register IO_CNTL Bit Name Value Function Reset...

Page 389: ...REG Keyboard columns outputs 0 Table 7 18 GPIO Event Mode Register GPIO_EVENT_MODE_REG Bit Name Value Function Reset Value 15 5 Reserved 4 1 PIN_SELECT Select MPUI O_IN 15 0 pin to be the GPIO_CLK event 0000 0000 Pin 0 1111 Pin 15 0 SET_GPIO_EVENT_ MODE 0 GPIO event mode disable 0 1 GPIO event mode enable Table 7 19 GPIO Interrupt Edge Register GPIO_INT_EDGE_REG Bit Name Value Function Reset Value...

Page 390: ...s active high 0 Note GPIO_INT is reset on read access to the GPIO_INT register The value read is the value after mask application Even in emulation mode the GPIO interrupts are reset by a read in the GPIO interrupt register GPIO_INT Table 7 22 Keyboard Mask Interrupt Register KBD_ MASKIT Bit Name Function Reset Value 15 1 Reserved 0 KBD_MASKIT Mask is active at level 1 inactive at level 0 00 Table...

Page 391: ...ogramming step is 31 µs 0000 Note Because GPIO_CLK is an asynchronous signal loading GPIO_DEBOUNCING_REG with 01 hex minimum value is rec ommended to ensure that you have a 31 µs minimum debouncing time If the value is 00 hex the interrupt may be gener ated immediately when an edge is met Table 7 25 GPIO Latch Register GPIO_LATCH_REG Bit Name Function Reset Value 15 0 GPIO_LATCH_REG After debounci...

Page 392: ...d status Setup registers UWIRE CS 3 0 Clock register Clock enable MPUXOR_CK register DMA_REQ to system DMA_REQ 6 0 Inth lvl2 2 3 edge 2 16 bits 16 bits 7 4 1 MicroWire Registers Start address in the peripheral range hex FFFB 3000 Table 7 26 lists the MicroWire registers Table 7 27 through Table 7 34 describe the individual registers Table 7 26 MicroWire Registers Register Description R W Size Addr...

Page 393: ... 27 Transmit Data Register TDR Bit Name Function Reset Value 15 0 TD Data to transmit Undefined Note MSB bit 15 is the first transmitted bit Whatever its size the word must be aligned on the most significant bit MSB side Table 7 28 Receive Data Register RDR Offset address hex 0x00 Bit Name Function Reset Value 15 0 TD Received data Undefined Note LSB bit 0 is the last received bit Whatever its siz...

Page 394: ...ce compared to the internal clock the CSRB status bit may still be low for the first read access The CSRB latency is 0 if the transfer was initiated by modifying the CS_CMD bit but it can be 0 3 cycles if initiated by the START bit Suggested workarounds are a to have a few NOPs between initiating a µWire transfer and checking CSRB status or b to check that CSRB first has a high value on an initial...

Page 395: ...s register sets up the serial interface for the first and the second external components Table 7 30 Setup Register 1 SR1 Bit Name Value Function Reset Value 11 6 Reserved 5 CS0_CHK Before activating a write process checks if external device is ready Undefined 0 No check is done and the write process is immediately executed 1 If DI signal is low the interface considers the external component busy i...

Page 396: ...e of the serial clock SCLK used to write data to the serial input D0 Output data is generated on this edge Undefined 0 Falling serial clock not inverted 0 Rising when serial clock inverted 1 Rising serial clock not inverted 1 Falling when serial clock inverted 0 CS0_EDGE_RD When CS0 is selected defines the active edge of the serial clock SCLK used to read data from the serial input DI Input data i...

Page 397: ...selected Undefined 10 9 CS3_FRQ Defines the frequency of the serial clock SCLK when CS3 is selected Undefined 00 F_INT 2 01 F_INT 4 10 F_INT 8 11 Undefined 8 CS3CS_LVL Defines the active level of the CS3 chip select 0 7 CS3_EDGE_WR Same as CS0_EDGE_WR when CS3 is selected Undefined 6 CS3_EDGE_RD Same as CS0_EDGE_RD when CS3 is selected Undefined 5 0 Reserved Notes 1 Content of this register must n...

Page 398: ...input clock 00 00 ARMOXR_CK 2 01 ARMOXR_CK 4 10 ARMOXR_CK 7 11 ARMOXR_CK 10 0 CLK_EN 0 Switch off the clock if 0 0 1 Switch on the clock if 1 Note Content of this register must not be changed when a read or write process is running This register sets up the serial clock polarity Table 7 33 Setup Register 4 SR4 Read Write Bit Name Function Reset Value 0 CLK_IN Serial clock is not inverted if 0 Seri...

Page 399: ...sed A hardware state machine detects a TXD write and automatically sets the programmed CS to its active value then starts the transmission The CS CMD and the START bits in the control and status register CSR are not updated during autotransmit 0 0 Autotransmit mode is disabled if 0 1 Autotransmit mode is enabled if 1 1 IT_EN In IT mode an interrupt is generated each time a word has been transferre...

Page 400: ...f the transmit data register TDR a write process is activated by setting the START bit to 1 and by writing a value different from zero to the NB_BITS_WR field A read process is always simultaneous with a write process which means that at every serial clock SCLK cycle data is read After having finished a write process if necessary a number defined by NB_BITS_RD of SCLK cycles is generated to allow ...

Page 401: ...edge Figure 7 19 Behavior of a XL93LC66 EEPROM Read Cycle 1 1 0 D15 UWIRE_SDI UWIRESDO UWIRE_SCLK WIRE_NCS A7 A6 A5 A4 A3 A2 A1 A0 D14 D13 D1 D0 On the DO line data is generated from the µWire interface on SLCK falling edge and read by the EEPROM interface on SCLK rising edge On the DI line data is generated from the EEPROM interface on SCLK rising edge and read by the µWire interface on SCLK risi...

Page 402: ...the following fields of the control and status register CSR J NB_BITS_RD 16 decimal J NB_BITS_WR 11 decimal J INDEX 00 J CS_CMD 1 J START 1 5 Wait until CSRB 0 and RDRB 1 status bits of CSR 6 Read the content of receive data register RDR 7 To continue reading data external component the EEPROM go to 8 Else go to 9 8 Set the following fields of the control and status register CSR J NB_BITS_RD 16 de...

Page 403: ...atus register CSR to be reset 4 Set the following fields of the control and status register CSR J NB_BITS_RD 0 J NB_BITS_WR 11 decimal J INDEX 00 J CS_CMD 1 J START 1 5 Wait for the CSRB bit of the control and status register CSR to be reset 6 Load the transmit data register TDR with J D15 D14 D0 J D15 D0 Data 7 Set the following fields of the control and status register CSR J NB_BITS_RD 0 J NB_BI...

Page 404: ...ait for the CSRB bit of the control and status register CSR to be reset 3 Load the transmit data register TDR with J D7d1 D0d1 D7d2 D0d2 D7d1 D0d1 Data for digit 1 J D7d2 D0d2 Data for digit 2 4 Set the following fields of the control and status register CSR J NB_BITS_RD 0 J NB_BITS_WR 16 decimal J INDEX 01 J CS_CMD 1 J START 1 5 Wait for the CSRB bit of the control and status register CSR to be r...

Page 405: ...vised that you read the bit before and after every write access to CSR to check the status 12 Set the following fields of the control and status register CSR J INDEX 01 J CS_CMD 0 J START 0 7 4 5 Example of Protocol Using Autotransmit Mode The autotransmit mode is controlled by the setup 5 register SR5 The follow ing example configures µWire for a read access on CS0 with serial clock out inverted ...

Page 406: ...r TDR with J A6 A5 A4 A3 A2 A1 A0 x x x x x x x x x x Don t care J A6 A0 Address of the selected memory register Transfer is automatically started 8 Wait until CSRB 0 and RDRB 1 status bits of CSR 9 Read the content of receive data register RDR 10 To continue reading data external component go to 5 else go to 11 11 Release auto transmit mode SR5 AUTO_TX_EN 0 12 END The corresponding behavior of th...

Page 407: ... register CSR as follows J NB_BITS_RD 0 J NB_BITS_WR 16 J INDEX 00 J CS_CMD 1 J START 0 5 Write to the setup register SR5 to configure and initiate the transfer J DMA_TX_EN 1 J IT_EN 0 J AUTO_TX_EN 1 J CS_TOGGLE_TX_EN 1 In AUTO TX mode setting the DMA_TX_EN bit to 1 starts the transfer 6 When the DMA transfer is complete check the status of CSRB to find whether µWire has finished the serial data t...

Page 408: ...oft Windows CE OS scheduling requires the following The periodic interrupt occurs every 1 25 ms The timer is expected to run in all modes except when suspended 32 kHz timer is a 24 bit down counter that generates CPU interrupts for the TI925T processor The following capabilities are available Timer reset Timer current value reading Timer start and stop Interrupt generation as timer down counts to ...

Page 409: ...2 Loading Autorestart of the Timer Loading the counter in the timer can be done in two fashions Write a 1 to the TRB bit in the timer control register TCR Wait until the counter reaches zero and is reloaded from its register if the autorestart bit ARL in the timer control register TCR is set to 1 If not then the timer is stopped 7 5 1 3 Timer Interrupt Period The timer interrupt period is defined ...

Page 410: ... see Table 7 37 Table 7 37 Read Write Synchronization Register Name Read Write CR Can be read anytime The value read is the last value written Two consecutive writes must be separated by at least 1 CLK32 period 31 µs If this is not the case the value written is not guaranteed TCR Reads are resynchronized on MPUXOR_CK clock to prevent peripheral bus from timing out Can be read anytime providing MPU...

Page 411: ...TRB Timer reload bit TRB 1 reloads the counter Once the counter is reloaded TRB is set to 0 0 0 TSS Timer start stop 0 0 Stop timer 1 Start timer If one shot mode is selected ARL 0 this bit is automatically reset by internal logic when timer is equal to 0 Table 7 39 Tick Value Register TVR Bit Name Function Reset Value 31 24 Reserved 23 0 TICK_VALUE_REG This value is loaded when timer passes throu...

Page 412: ...grammable threshold comparator see Figure 7 21 The pseudorandom 8 bit data generator is built using an LFSR It generates a white normal law random value between 1 and 255 The LFSR polynomial generator is P x x 7 x 3 x 2 x 1 The comparator generates 0 if the random value is greater or equal than the programmable threshold 1 if the random value is less than the programmable threshold Assuming the ra...

Page 413: ... address hex FFFB 5800 Table 7 41 PWL Registers Name Description R W Size Address Offset PWL_LEVEL PWL level R W 8 bits FFFB 5800 0x00 PWL_CTRL PWL control R W 8 bits FFFB 5800 0x04 Table 7 42 PWL Level Register PWL_LEVEL Offset address hex 0x00 Bit Name Function Reset Value 7 0 PWL_LEVEL Defines the mean value of the PWL output signal 0 leads to a continuous 0 output 255 to an almost continuous 1...

Page 414: ...put tone signal for a buzzer The frequency and the volume of this signal are programmable 7 7 2 PWT Features The PWT module has the following features see Figure 7 22 Divider generating a 1500 kHz frequency clock TIPB control interface Four dividers with 101 107 49 55 50 63 and 80 127 to generate each note particularity Four dividers 1 2 and a mux to select the octave 6 bit register to control ton...

Page 415: ... bit counter t128 t64 t32 t16 and comparator 7 7 3 PWT Registers Start address hex FFFB6000 Table 7 44 lists the PWT registers Table 7 45 through Table 7 47 describe the individual registers Table 7 44 PWT Registers Register Description R W Size Address Offset FRC PWT frequency control R W 8 bits FFFB 6000 0x00 VRC PWT volume control R W 8 bits FFFB 6000 0x04 GCR PWT general control R W 8 bits FFF...

Page 416: ...Name Function R W Reset Value 1 TESTIN Divider 1 154 switched ON OFF on 0 off 1 Asynchronous writing and reading R W 0 0 CLK_EN PWT clock enable clock disabled 0 clock enabled 1 Asynchronous writing and reading R W 0 7 7 4 PWT Programming 7 7 4 1 Buzzer Frequency To obtain the required frequencies the PWT clock is divided in a special way Four frequency dividers with the coefficients 101 107 49 55...

Page 417: ...different periods which differ by one period of the original signal Because of this difference the resulting signal has jitter To minimize this jitter the divider works with high frequencies resulting in short periods producing low jitter see Table 7 48 Table 7 48 Buzzer Frequencies FRC Bits 5 2 1 0 Buzzer Frequency FRC Bits 5 2 1 0 Buzzer Frequency 0000 00 4868 Hz 0000 10 1217 Hz 0001 00 4595 Hz ...

Page 418: ...xact tones 7 7 4 2 Buzzer Volume The buzzer volume can be programmed see Table 7 49 with bits 6 to 1 in the volume control register VRC The higher the 6 bit value is the louder is the buzzer loudspeaker To perform this programming a 6 bit binary counter is clocked with the PWT clock and rolls over to 0h after reaching its terminal value 3 Fh The counter value is compared with the 6 bit value progr...

Page 419: ... compatible device VDD I2C I F pads 7 8 1 1 Functional Overview The I2C bus is a multimaster bus The I2C controller function does support the multimaster mode to which more than one device capable of controlling the bus can be connected Including the OMAP5910 each I2C device is recog nized by a unique address and can operate as either transmitter or receiver depending on the function of the device...

Page 420: ...al pads Table 7 51 lists the reset state of the I2C signals Table 7 50 Signal Pads Name Type Description Reset Value I2C SCL In Out OD I2C serial CLK line Open drain output buffer requires external pullup resistor Rp Input I2C SDA In Out OD I2C serial data line Open drain output buffer requires external pullup resistor Rp Input Table 7 51 Reset State of I2C Signals Pin Pads System Reset I2C Reset ...

Page 421: ...dity on the I2C Bus SDA SCL Data line stable data valid Change of data allowed The I2C module generates start and stop conditions when it is configured as a master see Figure 7 25 Start condition is a high to low transition on the SDA line while SCL is high Stop condition is a low to high transition on the SDA line while SCL is high The bus is considered busy after the start condition BB 1 and fre...

Page 422: ...bit addressing format 7 bit 10 bit addressing format with repeated start condition The first byte after a start condition S always consists of 8 bits In the acknowl edge mode an extra bit dedicated for acknowledgement bit is inserted after each byte In the addressing formats with 7 bit addresses the first byte is composed by seven MSB slave address bits and one LSB R W bit While in the addressing ...

Page 423: ...nd SCL held low when the intervention of the processor is required after a byte has been transmitted Master Receiver This mode can only be entered from the master transmitter mode With either of the address formats Figure 7 27 a b and c the master receiver is entered after the slave address byte and bit R W has been transmitted if R W is high Serial data bits received on bus line SDA are shifted i...

Page 424: ...itters start a transmission on the same bus almost simultaneously arbitration procedure is invoked The arbitration procedure uses the data presented on the serial bus by the competing transmitters When a transmitter senses that a high signal it has presented on the bus has been overruled by a low signal it switches to the slave receiver mode Figure 7 28 shows the arbitration procedure between two ...

Page 425: ...line then is held low by the device with the longest low period while the other devices that finish their low periods must wait for the clock line to be released before starting their high periods A synchronized signal on the clock line is thus obtained where the slowest device determines the length of the low period and the fastest the length of the high period If a device pulls down the clock li...

Page 426: ...ts are all connected together for a two way transfer from one device to other devices 7 8 2 1 I2C Controller Features The main features of the I2C controller are as follows Compliant with Philips I2C specification version 2 1 1 Support standard mode up to 100 kbit s and Fast mode up to 400 kbit s 7 bit and 10 bit device addressing modes General call Start Restart Stop Multimaster transmitter slave...

Page 427: ... system peripheral clock MPUXOR_CK to obtain a 12 MHz clock for the I2C module see Figure 7 30 Figure 7 30 Prescale Sampling Clock Divider Value 1 PSC 1 MPUXOR_CK ICLK 0x0 0x1 0xFF Divide by 1 Divide by 2 Divide by 256 Values after reset are low All 8 bits Noise Filter The noise filter suppresses any noise that is 50 ns or less It is designed to suppress noise with one ICLK assuming the lower and ...

Page 428: ...tted data into the I2C_DATA register The interrupt vector register I2C_IVR contains one of the binary coded inter rupt vector to indicate which interrupt has occurred Reading the I2C_IVR clears the interrupt flag if other interrupts are pending a new interrupt is gen erated If there are more than one interrupt flag reading the I2C_IVR clears the highest priority interrupt flag The I2C interrupt si...

Page 429: ...x18 I2C_DATA I2C data access R W 0x1C Reserved 0x20 I2C_CON I2C configuration R W 0x24 I2C_OA I2C own address R W 0x28 I2C_SA I2C slave address R W 0x2C I2C_PSC I2C clock prescaler R W Ox30 I2C_SCLL I2C SCL low time control R W 0x34 I2C_SCLH I2C SCL high time control R W 0x38 I2C_SYSTEST I2C system test R W 0x3C The read only I2C module version register I2C_REV contains the hard coded revision num...

Page 430: ... Name Description 15 5 Reserved 4 XRDY_IE Transmit data ready interrupt enable 3 RRDY_IE Receive data ready interrupt enable 2 ARDY_IE Register access ready interrupt enable 1 NACK_IE No acknowledgment interrupt enable 0 AL_IE Arbitration lost interrupt enable Common to all bits When a bit location is set to 1 by the local host an interrupt is signaled to the local host if the corresponding bit lo...

Page 431: ...dy 3 RRDY Receive data ready 2 ARDY Register access ready 1 NACK No acknowledgment interrupt enable 0 AL Arbitration lost interrupt enable Single Byte Data SBD This read only bit 15 is set to 1 in slave receive or master receive modes when the last byte that was read from I2C_DATA register contains a single valid byte This bit is cleared to 0 by the core when the local host reads the I2C_IV regist...

Page 432: ...hen the receive shift register ICRSR is full and the receive FIFO is full An overrun condition does not result in a data loss the peripheral is just holding the bus low on SCL and prevent others bytes from being received ROVR is set to 1 when the I2C has recognized an overrun ROVR is clear when reading the I2C_DATA register or resetting the I2C I2C_EN 0 J 0 Normal operation J 1 Receiver overrun Va...

Page 433: ...recognized its own slave address or an address of all 8 zeros The AAS bit is reset to 0 by restart or stop 0 No action 1 Address as slave Value after reset is low Address Zero Status AD0 General Call This read only bit 8 is set to 1 by the device if it detects the address of all eight zeros that is general call The AD0 bit is reset to 0 default value when a start or stop condition is detected This...

Page 434: ...s written and the transmit FIFO buffer is full The local host can also poll this bit to write newly transmitted data into I2C_DATA register 0 Transmit buffer full or receiver mode 1 Transmit data ready for write and byte is needed Value after reset is low Receive Data Ready RRDY RRDY bit 3 is set to 1 when the local host is able to read new data from the I2C_DATA register RRDY is automatically cle...

Page 435: ...mit or receive STP 0 RM 0 DCOUNT passed 0 Master transmit or receive RM 1 Never Slave transmit Stop condition received from master Slave receive Stop condition and receiver FIFO empty This bit is cleared to 0 by the core with a read of the matching interrupt vector in I2C_IV register 0 No action 1 Access ready Value after reset is low No Acknowledgment NACK The no acknowledge flag bit 1 is set whe...

Page 436: ... to start a trans fer while BB bus busy is 1 When this is set to 1 due to arbitration lost the MST STP bits are automatically cleared by the core and the I2C becomes a slave receiver This bit is cleared to 0 by the core with a read of the matching interrupt vector in I2C_IV register 0 Normal no action required 1 Arbitration lost Value after reset is low Table 7 57 I2C Interrupt Vector Register I2C...

Page 437: ...EN Receive DMA channel enable 14 8 Reserved 7 XDMA_EN Transmit DMA channel enable 6 0 Reserved Receive DMA Channel Enable RDMA_EN When this bit 15 is set to 1 the receive DMA channel is enabled and the receive data ready interrupt is automatically disabled RRDY_IE bit cleared 0 Receive DMA channel disabled 1 Receive DMA channel enabled Value after reset is low Transmit DMA Channel Enable XDMA_EN W...

Page 438: ...ches 0 the core generates a stop condition if a stop condi tion was specified STP 1 and the ARDY status flag is set to 1 If STP 0 then the I2C asserts SCL 0 when DCOUNT reaches 0 The local host can then reprogram DCOUNT to a new value and resume sending or receiving data with a new start condition restart This process repeats until the STP is set to 1 by the LH The ARDY flag is set each time DCOUN...

Page 439: ...must be accessed in 16 bit mode except for the last byte in case of an odd number of bytes to transmit The last byte of the data packet may be written using a byte write access or a 16 bit write access When transmit FIFO the last data transfer must be a 16 bit transfer when it is written by the DMA and it can either be an 8 bit or 16 bit transfer when it is written by the MPU When an odd number of...

Page 440: ...o 1 for normal operation 0 I2C controller in reset 1 I2C module enabled Value after reset is low I2C Big Endian BE When this bit 14 is 0 default the FIFO is accessed in little endian format In transmit mode the LS byte I2C_DATA 7 0 is transmitted first and the MS byte I2C_DATA 15 8 is transmitted in 2nd position over the I2C line Con versely in receive mode the 1st or odd byte received 1 3 5 is st...

Page 441: ...d from the master device When this bit is set the I2C controller is in the master mode and it generates the serial clock Once set this bit is automatically cleared by a stop condition 0 Slave mode 1 Master mode Value after reset is low Transmitter Receiver Mode TRX Master mode only When this bit 9 is cleared the I2C controller is in the receiver mode and data on data line SDA is shifted into the r...

Page 442: ...cal host to put the I2C in the repeat mode In this mode data is continuously transmitted out of the I2C_DATA transmit reg ister until the STP bit is set to 1 regardless of DCOUNT value This bit is don t care if the I2C is configured in slave mode 0 Normal mode 1 Repeat mode Value after reset is low Table 7 64 Repeat Mode Conditions RM STT STP Conditions Bus Activities Mode 0 0 0 Idle None NA 0 0 1...

Page 443: ...set is low Start Condition STT Master mode only This bit 0 can be set to a 1 by the local host to generate a start condition It is reset to 0 by the hardware after the start condition has been generated The start stop bits can be configured to generate different transfer formats The STT and STP can be used to terminate the repeat mode 0 No action or start condition generated 1 Start Value after re...

Page 444: ...to 0 In this case OA 9 7 bits must be set to 000 by application software Values after reset are low all 10 bits The I2C slave address register I2C_SA specifies the addressed I2C module 7 bit or 10 bit address slave address Table 7 67 I2C Slave Address Register I2C_SA Bit Name Description 15 10 Reserved 9 0 SA Slave address This field bits 9 0 specifies either A 10 bit address coded on SA 9 0 when ...

Page 445: ...e divided by PSC 1 0x0 Divide by 1 0x1 Divide by 2 All other settings are Reserved Values after reset are low all 8 bits This I2C SCL low time control register I2C_SCLL is used to determine the SCL low time value when master Table 7 69 I2C SCL Low Time Control Register I2C_SCLL Bit Name Description 15 8 Reserved 7 0 SCLL SCL low0x0 6 ICLK time period time Master mode only This 8 bit value bits 7 0...

Page 446: ...low all 10 bits The I2C system test register I2C_SYSTEST is used to facilitate system level test by overriding some of the standard functional features of the peripheral It can permit the test of SCL counters control the signals that connect to I O pins or create digital loop back for self test when the module is configured in system test SYSTEST mode It also provides stop no stop function in debu...

Page 447: ...SCL low whether I2C is master transmitter receiver If SCL is high I2C waits until SCL becomes low and then stops If the I2C is a slave it stops when the transmission receiving completes FREE 1 The I2C runs free 0 Stop mode on breakpoint condition 1 Free running mode Value after reset is low Test Mode Select TMODE In normal functional mode ST_EN 0 these bits 13 12 are don t care They read always as...

Page 448: ... functional mode ST_EN 0 this read only bit 3 always reads as 0 In system test mode ST_EN 1 and TMODE 11 this read only bit returns the logical state taken by the SCL line either 1 or 0 Value after reset is low SCL Line Drive Output Value SCL_O In normal functional mode ST_EN 0 this bit 2 is don t care and always reads as 0 Writes are ignored In system test mode ST_EN 1 and TMODE 11 a 0 forces a l...

Page 449: ... transmit receive data enable interrupt masks J If using DMA for transmit receive data enable the DMA and program the DMA controller 2 Take the I2C module out of reset I2C_EN 1 Initialization procedure Configure the I2C mode register I2C_CON bits Program clock control registers I2C_SCLL and I2C_SCLH Program the I2C clock to obtain 100K bps or 400K bps I2C_SCLL x and I2C_SCLH x these values are to ...

Page 450: ...r use the DMA to write data into the data transmit register I2C_DATA Interrupt subroutines 1 Test for arbitration lost and resolve accordingly 2 Test for no acknowledge and resolve accordingly 3 Test for register access ready and resolve accordingly 4 Test for receive data and resolve accordingly 5 Test for transmit data and resolve accordingly 7 8 4 Flowcharts Figure 7 31 through Figure 7 42 show...

Page 451: ...T Write I2C_DATA n n 2 Are m bytes transferred n m Is send data being requested XUDF 1 Yes No Yes No Start is generated Start address is sent New START is generated STOP is generated DATA is sent Set appropriate values to every bit of I2C_CON I2C_EN bit must be set to 1 to take I2C out of reset condition Setting I2C_EN and setting other mode bits can be done simultaneously Because RM 1 hardware co...

Page 452: ...1 No 3 Read I2C_DATA n n 2 Are m bytes transferred n m Is send data being requested XUDF 1 Yes No Yes No Set appropriate values to every bit of I2C_CON I2C_EN bit must be set to 1 to take I2C out of reset condition Setting I2C_EN and setting other mode bits can be done simultaneously Because RM 1 hardware counter does not run Thus software counter counts the number of the required transfer The I2C...

Page 453: ...ers STT 1 new start Yes No STP 1 No 3 End code Is received data in I2C_DATA RRDY 1 No Yes Set appropriate values to every bit of I2C_CON I2C_EN bit must be set to 1 to take I2C out of reset condition Setting I2C_EN and setting other mode bits can be done simultaneously Dummy read The contents of this read data has no meaning The I2C goes into slave receiver mode EXPECTED COMMAND At the beginning S...

Page 454: ... start Yes No STP 1 No Can update the registers ARDY 1 Set appropriate values to every bit of I2C_CON I2C_EN bit must be set to 1 to take I2C out of reset condition Setting I2C_EN and setting other mode bits can be done simultaneously Yes EXPECTED COMMAND At the beginning STT STP 1 0 1 1 1 0 1 1 in the middle STT STP 0 0 0 1 At the end STT STP 0 1 EXPECTED I2C_IE I2C_IE 00000b Yes Is send data bei...

Page 455: ...s STT 1 new start Yes No STP 1 No Can update the registers ARDY 1 Set appropriate values to every bit of I2C_CON I2C_EN bit must be set to 1 to take I2C out of reset condition Setting I2C_EN and setting other mode bits can be done simultaneously Yes EXPECTED COMMAND At the beginning STT STP 1 0 1 1 1 0 1 1 in the middle STT STP 0 0 0 1 At the end STT STP 0 1 EXPECTED I2C_IE I2C_IE 00000b Yes Is re...

Page 456: ...e n bytes transferred ARDY 1 Set appropriate values to every bit of I2C_CON I2C_EN bit must be set to 1 to take I2C out of reset condition Setting I2C_EN and setting other mode bits can be done simultaneously Yes EXPECTED COMMAND At the beginning STT STP 1 0 1 1 1 0 1 1 in the middle STT STP 0 0 0 1 At the end STT STP 0 1 EXPECTED I2C_IE I2C_IE 11111b Yes Is send data being requested XRDY 1 No No ...

Page 457: ...STP 1 No Are n bytes transferred ARDY 1 Set appropriate values to every bit of I2C_CON I2C_EN bit must be set to 1 to take I2C out of reset condition Setting I2C_EN and setting other mode bits can be done simultaneously Yes EXPECTED COMMAND At the beginning STT STP 1 0 1 1 1 0 1 1 in the middle STT STP 0 0 0 1 At the end STT STP 0 1 EXPECTED I2C_IE I2C_IE 11111b Yes Is received data in I2C_DATA RR...

Page 458: ...bytes transferred ARDY 1 Set appropriate values to every bit of I2C_CON I2C_EN bit must be set to 1 to take I2C out of reset condition Setting I2C_EN and setting other mode bits can be done simultaneously Yes EXPECTED COMMAND At the beginning STT STP 1 0 1 1 1 0 1 1 in the middle STT STP 0 0 0 1 At the end STT STP 0 1 EXPECTED I2C_IE I2C_IE 00111b Yes Is DMA interrupt received No No Yes The I2C go...

Page 459: ... No Are n bytes transferred ARDY 1 Set appropriate values to every bit of I2C_CON I2C_EN bit must be set to 1 to take I2C out of reset condition Setting I2C_EN and setting other mode bits can be done simultaneously Yes EXPECTED COMMAND At the beginning STT STP 1 0 1 1 1 0 1 1 in the middle STT STP 0 0 0 1 At the end STT STP 0 1 EXPECTED I2C_IE I2C_IE 00111b Yes Is DMA interrupt received No No Yes ...

Page 460: ...Inter Integrated Circuit Controller 7 98 Figure 7 41 Slave Transmitter Receiver Mode Polling Write data XRDY 1 Read I2C_STAT Start Read I2C_DATA Write I2C_DATA No Yes No Yes Read data RRDY 1 ...

Page 461: ...it Controller 7 99 MPU Public Peripherals Figure 7 42 Slave Transmitter Receiver Mode Interrupt Read I2C_IV Start Write I2C_DATA Read I2C_DATA No Yes No Yes Transmit I2C_IV 5 Is interrupt received Receive I2C_IV 4 Yes No Yes ...

Page 462: ...o 5 Programmable Divider Synchronous or nstrobe CLK32K Reset lpgres perm_on lpg_led clk_256 perctrl onctrl perlpg onlpg TIPB interface control logic for output and counter counter and comparator pulse generator Two 1 7 9 1 Features The LPG has the following features Divider generating a 256 Hz frequency clock TIPB control interface Two 8 bit registers to control the whole LPG block Decoder for thr...

Page 463: ...e additional blink period 7 9 3 LPG Power Management The LPG input clock comes from the 32 kHz ULPD clock because it must work even when the OMAP5910 system is in deep sleep mode The internal clock of the LPG runs with 256 Hz For this reason the power consumption of this block can be neglected Nevertheless switch the LPG_CLK off if LPG is not used 7 9 4 LPG Registers Both receive and transmit regi...

Page 464: ...ading R W 0 5 3 ONCTRL Time LED is on parameter Asynchronous writing and reading R W 000 2 0 PERCTRL LED blink frequency Asynchronous writing and reading R W 000 With the LCR bits 2 0 the blinking period of the LED is determined Table 7 75 LED Blinking Period LCR Bit 2 LCR Bit 1 LCR Bit 0 Period of LED Number of Clock Cycles 0 0 0 125 ms 32 0 0 1 250 ms 64 0 1 0 500 ms 128 0 1 1 1 s 256 1 0 0 1 5 ...

Page 465: ... Time LED On Number of Clock Cycles 0 0 0 3 889 ms 1 0 0 1 7 789 ms 2 0 1 0 15 59 ms 4 0 1 1 31 39 ms 8 1 0 0 46 59 ms 12 1 0 1 62 59 ms 16 1 1 0 78 39 ms 20 1 1 1 93 59 ms 24 Table 7 77 Power Management Register PMR Bit Name Value Function R W Reset Value 0 CLK_EN Functional clock enable R W 0 0 Clock disabled 1 Clock enabled Asynchronous writing and reading ...

Page 466: ...king for receives and transmits External shift clock generation or an internal programmable frequency shift clock Multichannel transmits and receives of up to 128 channels A wide selection of data sizes including 8 12 16 20 24 or 32 bits µ Law and A Law companding Data transfers with LSB or MSB first Programmable polarity for both frame synchronization and data clocks Highly programmable internal ...

Page 467: ...0 MPU memory map Table 7 79 McBSP2 Registers Name Description Offset DRR2 15 0 Data receive register 2 0x00 DRR1 15 0 Data receive register 1 0x02 DXR2 15 0 Data transmit register 2 0x04 DXR1 15 0 Data transmit register 1 0x06 SPCR2 15 0 Serial port control register 2 0x08 SPCR1 15 0 Serial port control register 1 0x0A RCR2 15 0 Receive control register 2 0x0C RCR1 15 0 Receive control register 1 ...

Page 468: ...l enable register partition D 0x28 XCERC 15 0 Transmit channel enable register partition C 0x2A XCERD 15 0 Transmit channel enable register partition D 0x2C RCERE 15 0 Receive channel enable register partition E 0x2E RCERF 15 0 Receive channel enable register partition F 0x30 XCERE 15 0 Transmit channel enable register partition E 0x32 XCERF 15 0 Transmit channel enable register partition F 0x34 R...

Page 469: ... requests Reset MPU I F Interrupts TX DMA_REQ_16 MPUPER_CK MPUPER_nRST MPU public peripheral bus RX overflow level 2 IRQ_31 TX interrupt level 1 IRQ_4 RX interrupt level 1 IRQ_5 RX DMA_REQ_17 Clock generation and management MPU peripheral bridge MPU interrupt handler 32 MCBSP2 CLKX MCBSP2 DX MCBSP2 FSR MCBSP2 CLKR MCBSP2 DR Note You can use the AUXON feature to gate the functional clock to the McB...

Page 470: ...P module The CLKS signal is the active input clock for the McBSP modem block The active input clock can be changed in a McBSP register but register activity on CLKS is required to perform the set up and write to the McBSP Figure 7 45 Communication Processor Data Interface OMAP5910 MPU peripheral programmable clock Configreg McBSP2 CLKS FSX_OUT FSX_OE FSX_IN CLKX_OUT CLKX_OE CLKX_IN DX_OUT DX_OE FS...

Page 471: ...in Control Register Configuration Bit Configuration Value Description 15 14 00b Reserved 13 0b Set serial port mode for DX FSX and CLKX pins 12 0b Set serial port mode for DR FSR and CLKR pins 11 1b TX frame synchronization signal driven by internal generator 10 0b RX frame synchronization signal derived by external source 9 1b CLKX set output pin and driven by internal generator 8 0b CLKR set inp...

Page 472: ...ion Value Description 15 0b Set single phase frame 14 8 000 0000b Don t care for single phase frame 7 5 000b Don t care for single phase frame 4 3 00b Set no companding data and transfer start with MSB first 2 0b Set FSR not ignore after the first resets the transfer 1 0 01b Set data delay as 1 bit 7 10 1 4 Transmit Control Register Configuration ARM_Write 0x0040 XCR1 set up XCR1 per below configu...

Page 473: ...nfigure the sample rate generator appropriately for CLKX and FSX For details see TMS320C54x DSP Enhanced Peripherals Reference Set vol 5 SPRA302 2 Wait for two CLKSRG clocks 3 ARM_Write SPCR2 or 0x0000 0040 SPCR2 CLKG enable 4 Wait two CLKG clocks 7 10 1 6 Interrupt Flag Configuration and Clear ILR ITR MIR 1 ARM_Write ILR set ILR appropriately for the interrupt handling priority 2 ARM_Write ITR an...

Page 474: ...rrupts flag on ITR when taken the interrupt handle 7 10 1 9 Received Data Loading RX_INT Handling in Interrupt Survive Routine ARM_Read DRR Note Clear interrupts flag on ITR when taken the interrupt handle Waveform Example Figure 7 46 Waveform Example CLK R X FS R X D R X A15 A14 A13 A3 A2 A1 A0 B13 B14 B15 B3 B2 B1 B0 ...

Page 475: ...85 Pin Control Register Configuration Bit Configuration Value Description 15 14 00b Reserved 13 0b Set serial port mode for DX FSX and CLKX pins 12 0b Set serial port mode for DR FSR and CLKR pins 11 1b TX frame synchronization signal driven by internal generator 10 0b RX frame synchronization signal derived by external source 9 1b CLKX set output pin and driven by internal generator 8 0b CLKR set...

Page 476: ...guration Bit Configuration Value Description 15 0b Set single phase frame 14 8 000 0000b Set receive frame length as one word per frame 7 5 000b Don t care for single phase frame 4 3 00b Don t care for single phase frame 2 0b Set FSR not ignore after the first resets the transfer 1 0 01b Set data delay as 1 bit 7 10 1 13 Transmit Control Register Configuration ARM_Write 0x0040 XCR1 set up XCR1 per...

Page 477: ...appropriately for CLKX and FSX For details see TMS320C54x DSP Enhanced Peripherals Reference Set vol 5 SPRA302 2 Wait two CLKSRG clocks 3 ARM_Write SPCR2 or 0x0000 0040 SPCR2 CLKG enable 4 Wait two CLKG clocks 7 10 1 15 DMA Configuration Configure the REVT and XEVT bit for the DMA receive and transmit synchronized invent 7 10 1 16 Interrupt Flag Configuration and Clear ILR MIR 1 ARM_Write ILR set ...

Page 478: ...ta buffer and transfer the new transmit data to appropriate TX buffer Clear interrupts flag on ITR when taking the interrupt handle Note Clear interrupts flag on ITR when taken the interrupt handle Waveform Example Figure 7 47 Waveform Example CLK R X FS R X D R X A15 A14 A13 A3 A2 A1 A0 B13 B14 B15 B3 B2 B1 B0 ...

Page 479: ...il see Chapter 13 USB Function Module The MPU base address is FFFB 4000 Table 7 90 USB Function Registers Name Description Offset Address REV Revision number read 0x00 Endpoint EP_NUM Selects and enables the endpoint that can be accessed by the TI925T 0x04 DATA The entry point to write into a selected TX endpoint to read data from a selected RX endpoint or to read data from setup FIFO 0x08 CTRL Co...

Page 480: ...e possible DMA transmit channels and selects the endpoint number that is assigned to each of these DMA channels 0x44 DMA DATA_DMA Entry point to write or to read data into from an endpoint used in a DMA transfer through DMA channel 0 1 or 2 0x48 Reserved 0x4C TXDMA0 Controls the operation of the transmit DMA channel 0 0x50 TXDMA1 Controls the operation of the transmit DMA channel 1 0x54 TXDMA2 Con...

Page 481: ...or non control receive endpoint 1 0x84 EP2_RX Gives the device configuration for non control receive endpoint 2 0x88 EP15_RX Gives the device configuration for non control receive endpoint 15 0xBC Reserved 0xC0 EP1_TX Gives the device configuration for non control transmit endpoint 1 0xC4 EP2_TX Gives the device configuration for non control transmit endpoint 2 0xC8 EP15_TX Gives the device config...

Page 482: ...I proto col interface Other combinations like two SD cards one MMC card one SD card are not supported The application interface is responsible for managing transaction semantics The MMC SD host controller handles MMC SD protocol at transmission level packing data adding cyclic redundancy check CRC start end bit and check ing for syntactical correctness SD mode wide bus width is also supported The ...

Page 483: ...D_MMC_SD_ adp_clk_o CONF_MMC LATCH static_valid Nrespwron adp_clock_i Functional MMC_CLK 0 MMC_CMD adp_rcmd_o adp_cmd_dir_oq adp_cmd_oq adp_cmd_i MMC_DATA 3 0 adp_rdat_o adp_dat_dir_oq adp_dat_oq 3 0 adp_dat_i 3 0 GPIO 2 SPI_CLK adp_spi_clk_o VDDSHV6 VDDSHV6 VSS GPIO 3 4 6 SPI_C Sn 3 1 adp_spi_cs_oqn 3 1 GPIO 0 SPI_RDY adp_spi_fl_rdy_i VSS System DMA MPU Interrupt Handler Lev2 ULPD MMC card MMC ca...

Page 484: ... built in support for card detection No full compliance to SDIO specification 7 12 2 MMC SD Host Controller Signals Pads The signal pads listed in Table 7 91 describe the physical interface between OMAP5910 the transceiver and the target MMC SD memory card s or serial flash memories The transceiver provides dc level adaptation functions between OMAP5910 and the target devices The state of the OMAP...

Page 485: ...PI C Sn 3 2 In Out Out Pulldown disabled Input 1 By default pad used by the GPIO3 The SPI CSn 3 output signal can be multiplexed SPI CSn 3 is active low only active in SPI mode during SPI transfers Reserved in MMC SD mode GPIO4 SPI C Sn 2 2 In Out Out Pulldown disabled Input 1 By default pad used by the GPIO4 The SPI CSn 2 output signal can be multiplexed SPI CSn 2 is active low only active in SPI...

Page 486: ...ock ADP_CLK_I which is generated by the ULPD DPLL This clock is requested by setting to 1 the CONF_MOD_MMC_SD_CLK_REQ bit 23 of the MOD_CONF_CTRL_0 register The MPU TIPB reset MPU_PER_RST resets the MMC SD host controller 7 12 4 MMC SD Host Controller DMA Request The MMC SD host controller can use Receive DMA channel DMA_RD_REQ_OQN which is connected to the SYSTEM DMA request 21 Transmit DMA chann...

Page 487: ...rectly controlled by the MMC SD host controller adp_rcmd_o and adp_rdat_o and are only active when required which saves power Table 7 92 and Table 7 93 show activation conditions for the MMC CMD and MMC DAT pullups Table 7 92 MMC_CMD Pullups MMC_SD Host Controller Status MMC CARD Status MMC_CMD Pullup Open Drain Mode MMC_CMD Pullup Push Pull Mode Input Input Active Active Input Output Active Disab...

Page 488: ... FFFB 781C MMC_DATA MMC TX RX FIFO data R W FFFB 7820 MMC_BLEN MMC block length R W FFFB 7824 MMC_NBLK MMC number of blocks R W FFFB 7828 MMC_BUF MMC buffer configuration R W FFFB 782C MMC_SPI MMC serial port interface R W FFFB 7830 MMC_SDIO MMC SDIO mode configuration R W FFFB 7834 MMC_SYST MMC system test R W FFFB 7838 MMC_REV MMC module version R FFFB 783C MMC_RSP0 MMC command response 0 R FFFB...

Page 489: ...a write access to the least significant LSB bits 7 0 Hence the MSB must always be written first in a byte accessed situation A read has no effect except to return the last command that was previously sent Note A write into this register with Type adtc resets the FIFO pointers and pre fetch register Writes with other type values bc bcr ac do not affect the FIFO contents Hence data must be written i...

Page 490: ... command It can be used to terminate the interrupt mode by generating a CMD40 response by the core see Interrupt Mode section 4 3 in MMC 1 specification This bit is only valid if the command type is adtc or bc 0 Normal mode 1 Stream mode type adtc host response type bc Value after reset is low Command Type Type Encoded bits 13 12 that define the type of the command that is passed by the core to th...

Page 491: ...R1 R1b normal response command 010 R2 CID CSD registers 011 R3 OCR register 100 R4 Fast I O MMC card only 101 R5 Interrupt request MMC card only 110 R6 Published RCA response SD card only 111 Reserved Values after reset are low three bits Send Initialization Stream Init When this bit 7 is set an initialization sequence is sent prior to the command This option can simplify acquisition of new cards ...

Page 492: ...cifying the command number sent to the card 000000 CMD0 000001 CMD1 111111 CMD63 Values after reset are low all 6 bits The MMC argument low and high registers specify the 32 bit argument value that is passed with the command These registers must be initialized prior to sending the command itself to the card write action into the MMC_CMD regis ter The only exception is for a command index specifyin...

Page 493: ... DAT 0 used 1 4 bit data width DAT 3 0 used SD card only Value after reset is low This bit must always be set to 0 for MMC cards or during SPI transfer Not set ting this bit correctly can result in an unpredictable behavior Mode Select Mode These bits 13 12 select between MMC SD mode SPI mode 1 SYSTEST mode and SPI mode 2 In MMC SD mode transfers to the MMC SD card follow the MMC protocol MMC cloc...

Page 494: ...MMC SD cards using SPI protocol Values after reset are low 2 bits Power Up Control Power_Up This bit 11 must be set to 1 prior to any valid transaction to either MMC SD or SPI memory cards When 1 the card is considered powered up and the controller core is enabled When 0 the card is considered powered down system dependant and the controller core logic in pseudoreset state That is the MMC_STAT reg...

Page 495: ...ard when MMC_CON Mode 01 POL MMC_SPI 0 MMC card w SPI protocol select MMC_CON Mode 11 0 1 S Notes 1 Duringtheidentificationphase themaximalfrequencyontheMMCCLKlineis400kHz reference bustimingspeci fications Chapter 6 of the MultiMediaCard System Specification Version 3 1 June 2001 MMCA Technical Com mittee or the SD Memory Card Specifications Part 1 Physical Layer Specification Version 1 0 March 2...

Page 496: ...Clk_div 2 1 ref_clk_per TRUNC Clk_div 2 Odd 3 POL PHA ref_clk_per TRUNC Clk_div 2 ref_clk_per TRUNC Clk_div 2 1 ref_clk_per is reference clock period in ns to the module end system dependant TRUNC is the truncate to an integer number function round down Example 1 Module reference clock 48 MHz 20 83 ns target is MMC card clk_div 3 MMC card is 20 MHz max MMC_CLK period 62 5 ns 50 ns OK Ideal MMC_CLK...

Page 497: ...ut Data response time out no response 4 EOF_Busy Card exit busy state 3 Block_RS Block received sent 2 Card_Busy Card enter busy state 1 Reserved 0 End_of_Cmd End of command phase Common to all bits The local host can only clear a set bit location by writing a 1 into the bit location A write 0 has no effect When a bit location is set to 1 by the core an interrupt is signaled to the local host if t...

Page 498: ...status error In SPI or SYSTEST modes this bit has no meaning and always reads as 0 0 No action or no error 1 Error occurred Value after reset is low Card IRQ Card_IRQ MMC mode only The core automatically sets this bit 13 when a card is in interrupt mode and exits Wait_IRQ state irq by asserting a 0 on the CMD line cards are in open drain mode Only Class 9 MMC cards can be put into interrupt mode w...

Page 499: ...ion or card powered up 1 OCR busy Value after reset is low Buffer Almost Empty A_Empty The core automatically sets this bit 11 during a write operation to the card when the level is below the threshold value set in MMC_BUFF AE_Level regis ter bits It indicates that the memory card has emptied the buffer to the speci fied level and that the local host is able to write more data into the buffer If t...

Page 500: ...e decimal equivalent set binary value 0 31 0 No action or buffer is below or equal almost full level 1 Buffer almost full Value after reset is low Command CRC Error Cmd_CRC MMC SD mode only The core automatically sets this bit 8 if there is a CRC7 error in the command response bits 7 1 of all response types except type R3 A CMD1 MMC or ACDM41 SD cannot trigger a CRC 7 error In SPI or SYSTEST modes...

Page 501: ...ery block In SPI or SYSTEST modes this bit has no meaning and always reads as 0 0 No action or no CRC error 1 CRC16 error read 3 bit CRC token error write Value after reset is low Data Time out Error Dat_timeout The core automatically sets this bit 5 if the card does not respond within the specified number of data time out clock cycles DTO that is set in MMC_DTO register In SPI mode this bit also ...

Page 502: ...his bit is not set instead a data CRC error is set to 1 For either multiple block or stream transfer this bit is set only once after last successful block transfer when MMC_NBLK NBLK decrements down to 0 or until interrupted by a stop command In SPI mode this bit is set when either the read or write command completes MMC_BLEN BLEN decrements down to 0 There is a distinction to be made between DMA ...

Page 503: ...essful command response sequence or at the end of a command without response This bit is not set in case of a card status error In SPI or SYSTEST modes this bit has no meaning and always reads as 0 0 No action 1 End of command response sequence Value after reset is low When a CMD12 command is transferred after a multiple block read the End_of_Cmd bit 0 is not set Alternatively the Card_Busy bit 2 ...

Page 504: ...Data_CRC_IE Data CRC error interrupt enable 5 Data_timeout_IE Data response time out interrupt enable 4 EOF_Busy_IE Card exit busy state interrupt enable 3 Block_RS_IE Block received sent interrupt enable 2 Card_Busy_IE Card enter busy state interrupt enable 1 Reserved 0 End_of_Cmd_IE End of command interrupt enable Common to all bits When a bit location is set to 1 by the local host an interrupt ...

Page 505: ... MMC SD mode only The local host sets this field bits 7 0 based on NCR clock cycles MMC and SD card specifies NCR to be between 2 and 64 clock cycles If the card does not respond within the specified number of cycles command time out gets set to 1 in MMC_STAT 7 register bit For MMC card interrupt mode support this time out is disabled when the command passes with an R5 response CMD40 0x00 Command ...

Page 506: ... response register after a successful execution of a SEND_CSD command CMD9 If the card does not respond within the specified number of cycles data time out gets set to 1 in MMC_STAT 5 register bit The effective number of clock cycles for time out value are to be multiplied by 1024 if MMC_SDIO DTO_PS_En 1 and by 1 if DTO_PS_En 0 In SPI mode a data time out condition is also generated if the RDY BUS...

Page 507: ... is legal for the local host to perform only 16 bit accesses read or write to the buffer even if the block length is not an even number In case of an odd number of bytes to read the upper byte of the last access always reads as 0x00 Conversely for an odd number of bytes to write the upper byte must be filled with 0x00 for the last data value In SPI mode the register contains both the command op co...

Page 508: ... are CSD register settings of the card returned in a response R2 following a SEND_CSD command CMD9 In SPI modes and for a read transaction BLEN must be initialized with the exact byte count to read negative 1 excluding the op code and address arguments Op code and address arguments that are passed to the SPI device must be written into the FIFO buffer prior to starting the SPI transfer BLEN starts...

Page 509: ...r A write into this register initializes an 11 bit counter that decrements by one after each block transfer A read into this register returns the number of blocks remaining to be transferred to the card When the counter reaches 0 the transfer stops after the last transfer completes For stream or multiple block transfer a Block_RS interrupt is generated only once after the last successful transfer ...

Page 510: ...et to 1 the receive DMA channel is enabled and the A_Full status bit is forced to 0 by the core irrespectively of AF_level setting see Table 7 109 0 Receive DMA channel disabled 1 Receive DMA channel enabled Value after reset is low Buffer Almost Full Level AF_Level This register bits 12 8 holds the programmable almost full level value used to determine almost full buffer condition If you want an ...

Page 511: ...em DMA Controller 0 Receive DMA channel disabled 1 Receive DMA channel enabled Value after reset is low Buffer Almost Empty Level AE_Level This register bits 4 0 holds the programmable almost empty level value used to determine almost empty buffer condition If you want an interrupt or a DMA write request to be issued during a write operation when the data buffer holds n words of 16 bits then AE_Le...

Page 512: ...6 Reserved 5 4 CS Chip select control 3 CSM Chip select mode 2 CSD Chip select disable 1 PHA Phase control 0 POL Polarity control Start SPI Transfer Start This set only bit 15 always reads as 0 A write to 0 has no effect When set to 1 by the local host a SPI transfer is automatically started Note The user must take care to initialize MMC_BLEN BLEN before starting an SPI transfer SPI transfer autom...

Page 513: ...ts after last SPI_CLK clock edge before asserting the chip select signals to their inactive high level 00 Minimum 0 5 clock cycle 01 Minimum 1 5 clock cycles 10 Minimum 2 5 clock cycles 11 Minimum 3 5 clock cycles Values after reset are low 2 bits Chip Select Setup Time Control TCSS This field bits 9 8 defines the number of interface clock cycles that the core waits after asserting the chip select...

Page 514: ...d Internal clock Figure 7 51 SPI Mode C S Timings Controls POL 1 TCSH 3 5 TCSH 2 5 TCSH 1 5 TCSH 0 5 TCSS 3 TCSS 4 TCSS 2 TCSS 1 SPI_CLK POL 1 SPI_CSn 3 0 SPI shift clock module generated Internal clock Chip Select Control CS Encoded value bits 5 4 that selects the device being targeted for SPI transfer 00 Reserved no device is selected 01 C S 1 10 C S 2 11 C S 3 Values after reset are low 2 bits ...

Page 515: ...e with busy condition 0 Automatic mode 1 Manual mode controlled by CSD Value after reset is low Chip Select Disable CSD When this bit 2 is set to 0 the selected CS signal is asserted to its active low state either automatically when CSM 0 or manually when CSM 1 When set to 1 the selected CS signal is forced to its inactive high state It can be used to send dummy clocks with CS inactive to a MMC or...

Page 516: ...n on the second edge transition of SPICLK When clock phase 1 Data is shifted out in transmission on the first edge transition of SPICLK Data is shifted in in reception on the second edge transition of SPICLK J 0 Phase 0 J 1 Phase 1 Value after reset is low Clock Polarity POL The clock polarity bit 0 selects the active edge of the clock either rising or falling When 0 the idle value of the SPI cloc...

Page 517: ...uration Register MMC_SDIO Bit Name Description 15 14 Reserved 13 CER1_3_En Card status error on bit 3 of response 1 enable 12 6 Reserved 5 DTO_PS_En Data time out prescaler enable 4 0 Reserved Card Status Error on Bit 3 of Response R1 Enable CER1_3_En This bit 13 must be set to 1 for SD cards only or application specific com mands that generates an error If set to 1 a card status error is generate...

Page 518: ...m Test Register MMC_SYST Bit Name Description 15 14 Reserved 13 RDY_dat Ready busy input signal data value 12 DAT dir DAT 3 0 signals direction 11 DAT3_dat DAT3 input output signal data value 10 DAT2_dat DAT2 input output signal data value 9 DAT1_dat DAT1 input output signal data value 8 DAT0_dat DAT0 SI input output signal data value 7 CMD dir CMD SO signal direction 6 CMD_dat CMD SO input output...

Page 519: ...e corresponding DAT pins high or low A write into these bits has no effect If DAT_dir 1 output mode direction the DAT pins is driven high or low according to the value written into these register bits Values after reset are low all 4 bits CMD Direction CMD_dir When set this bit 7 places the in out CMD pin in output mode 0 Input 1 Output Value after reset is low CMD Data CMD_dat If CMD_dir 0 input ...

Page 520: ...to these register bits 3 1 Values after reset are low all 3 bits The read only MMC module version register MMC_REV contains the revision number of the module A write to this register has no effect Table 7 114 MMC Module Version Register MMC_REV Bit Name Description 15 8 Reserved 7 0 REV Module version number Module Version Number REV This 8 bit field bits 7 0 indicates the revision number of the R...

Page 521: ...ponse Register 1 MMC_RSP1 Bit Name Description 15 0 RESP0 CMD response R2 31 16 Table 7 117 MMC SD Command Response Register 2 MMC_RSP2 Bit Name Description 15 0 RESP0 CMD response R2 47 32 Table 7 118 MMC SD Command Response Register 3 MMC_RSP3 Bit Name Description 15 0 RESP0 CMD response R2 63 48 Table 7 119 MMC SD Command Response Register 4 MMC_RSP4 Bit Name Description 15 0 RESP0 CMD response...

Page 522: ...or a 32 bit response of type R1 R1b R3 R4 R5 R6 Table 7 121 MMC SD Command Response Register 6 MMC_RSP6 Bit Name Description 15 0 RESP6 CMD response R2 111 96 R1 R1b R3 R4 R5 R6 23 8 Table 7 122 MMC SD Command Response Register 7 MMC_RSP7 Bit Name Description 15 0 RESP6 CMD response R2 111 96 R1 R1b R3 R4 R5 R6 39 24 ...

Page 523: ...re 7 54 Figure 7 53 Command Flow Operation without data Initialization set system configuration Send command with type response direction Write data buffer Read data buffer Set transfer parameters Response from card Blocks sent to card Blocks received from card End of the operation Write Read Operation with data Send command with type response direction Send command with type response direction ...

Page 524: ... is necessary at the begin ning After the MMCSD adapter woks differently depending if the host sends a command without data with data and depending the type the index of the response and the direction Figure 7 55 Detail of Basic Operation Initialization set system configuration Next operation Write MMC_CON Choose the mode and frequency Write MMC_IE Enable interrupts Write MMC_CTO Command time out ...

Page 525: ...ut End of command Next operation No No Yes Yes Send command with type response direction When a command that has no response is used that is CMD0 CMD4 CMD15 the command timeout condition can never occur since there is no response expected In this case the NO path from the command timeout clock is taken and the timeout interrupt is not valid ...

Page 526: ...l and Rx Tx DMA if needed Write or read MMC_DATA Write MMC_BLEN If the value does not change it is not useful to set it again Write MMC_NBLK In single mode NBLK must be 0 In multiblock or stream NBLK must be 0 Next operation Write or read data buffer For the example shown in Figure 7 58 the mode selected is MMC SD MMC_CON 13 12 00 ...

Page 527: ...ocks sent to card Blocks received from card Write operation Set transfer parameters Calculation of CRC Almost full Almost Block R S Stop transmission send command Error Write data buffer In multi block the MMC_NBLK 0 must be set for every new operation No No Yes Stream Single block Stream and multiple Yes No Others cases Stream Send command with type response direction Send command with type respo...

Page 528: ...level is equal to or greater than the programmed threshold Since each DMA transfer has equal size it is necessary to have the total data size of the transfer be a multiple of the DMA read access size max 32 words Summary DMA transfer size n FIFO size max 32 16 bit words AF_level n 1 FIFO threshold level n submultiple of total transfer size Example Multiple block read of 10 blocks of 512 bytes each...

Page 529: ... of two DMA transfers of n words minus one Hence the maximum permitted DMA transfer size is half the FIFO size The MMC SD host controller does not generate a new DMA request until the system DMA has written the N words corresponding to the previous DMA request even if the FIFO level is equal to or greater than the programmed threshold Because each DMA transfer has equal size it is necessary to hav...

Page 530: ...nlike DMA mode it is not needed to have the total data size of the transfer be a multiple of the LH read access size maximum 32 words The last LH read access can be down to the LH transfer size when ending any total data size transfer as follows LH transfer size n FIFO size max 32 16 bit words AF_level n 1 FIFO threshold level An example is a multiple block read of 10 blocks of 512 bytes each The ...

Page 531: ... Calendar information day month year day of the week directly in BCD code up to year 2099 Interrupt generation periodically 1s 1m 1h 1d period or at a precise time of the day alarm function 30 s time correction Oscillator drift compensation Figure 7 59 RTC Clock Diagram 32 kHz IRQ_ALARM Compensation NIRQ_ALARM NIRQ_TIMER 32 kHz counter Seconds Minutes Hours Days Months Years Alarm Interrupt Week d...

Page 532: ...to 12 Day 01 to 31 01 to 31 for months 1 3 5 7 8 10 12 01 to 30 for months 4 6 9 11 01 to 29 for month 2 leap year 01 to 28 for month 2 common year Week 00 to 06 Weekday Hour 00 to 23 00 to 23 in 24 hour mode 01 to 12 in AM PM mode Minutes 00 to 59 Seconds 00 to 59 7 13 2 Register Access There are three types of registers Time and calendar registers alarm General Compensation These three types hav...

Page 533: ... accesses the time and calendar registers outside of the access period the access is not ensured see Figure 7 60 Figure 7 60 Time and Calendar Registers and Alarm Register Access Read BUSY bit CLK_32 KHz BUSY TIPB NSTROBE Timer counter Available TC registers access 15 µs 15 µs Available TC registers access 15 µs Available TC registers access RTC update 32766 32767 0 1 Any read write TC registers a...

Page 534: ... the time and calendar information The MPU can write into time and calendar registers without stopping the RTC but in this case the MPU must read the status register to ensure that the RTC updating takes place in more than 15 µs bit BUSY should be 0 Then the MPU must perform all changes in less than 15 µs to prevent partial updating between the beginning and the end of the writing sequence into ti...

Page 535: ...7 61 Compensation Scheduling Hours Busy Seconds COMP_EN Hours Seconds Compensation event Load Comp registers 58 59 0 1 2 Compensation event Load Comp registers 58 59 0 1 2 3 4 5 3 4 59 0 1 Compensation event Load comps Hour event Compensation scheduling ...

Page 536: ...s a negative edge sensitive interrupt low level pulse duration 15 µs RTC_STATUS_REG 5 2 are only updated at each new interrupt and show what events have happened as shown in Table 7 124 Table 7 124 Timer Interrupts RTC_INTERRUPTS_REG 1 0 11 10 01 00 RTC_STATUS_REG 5 day 1 0 1 0 1 0 1 RTC_STATUS_REG 4 hour 1 1 0 1 0 1 RTC_STATUS_REG 3 min 1 1 1 0 1 RTC_STATUS_REG 2 sec 1 1 1 1 1 when this event is ...

Page 537: ...ARM Busy Timer counter 3 1 0 32767 2 Write 1 into STATUS 6 7 13 2 9 Oscillator Drift Compensation To compensate for any inaccuracy of the 32 kHz oscillator the MPU can per form a calibration of the oscillator frequency calculate the drift compensation versus one hour period and load the compensation registers with the drift compensation value see Figure 7 64 Autocompensation is enabled by the AUTO...

Page 538: ...nter 32 kHz clock Second update Timer counter 32 kHz clock Second update Timer counter 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 0000 0001 0000 No compensation 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 0002 0003 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 7FFE 7FFF Negative compensation comp_reg 2 Positive compensation comp_reg 2 0xFFFE Two cycles are removed from next second Two cycles are added to current second ...

Page 539: ...bits R W FFFB 4800 0x18 Reserved 8 bits FFFB 4800 0x1C ALARM_SECOND_REG Alarm seconds 8 bits R W FFFB 4800 0x20 ALARM_MINUTES_REG Alarm minutes 8 bits R W FFFB 4800 0x24 ALARM_HOURS_REG Alarm hours 8 bits R W FFFB 4800 0x28 ALARM_DAYS_REG Alarm days 8 bits R W FFFB 4800 0x2C ALARM_MONTHS_REG Alarm months 8 bits R W FFFB 4800 0x30 ALARM_YEARS_REG Alarm years 8 bits R W FFFB 4800 0x34 Reserved 8 bit...

Page 540: ...tes Register MINUTES_REG Bit Name Function R W Reset Value 7 Reserved R 0 6 4 MIN1 2nd digit of minutes Range is 0 to 5 R W 000 3 0 MIN0 1st digit of minutes Range is 0 to 9 R W 0000 Table 7 128 Hours Register HOURS_REG Bit Name Value Function R W Reset Value 7 PM_nAM Only used in PM_AM mode otherwise 0 R 0 0 AM 1 PM 6 Reserved R 0 5 4 HOUR1 2nd digit of hours Range is 0 to 2 R W 00 3 0 HOUR0 1st ...

Page 541: ...R 000 4 MONTH1 2nd digit of months Range from 0 to 1 R W 0 3 0 MONTH0 1st digit of months Range from 0 to 9 R W 0001 Note Usual notation for month value 01 January 02 February 12 December Table 7 131 Years Register YEARS_REG Bit Name Function R W Reset Value 7 4 YEAR1 2nd digit of years Range from 0 to 9 R W 0000 3 0 YEAR0 1st digit of years Range from 0 to 9 R W 0000 Table 7 132 Weeks Register WE...

Page 542: ...r ALARM_MINUTES_REG Bit Name Function R W Reset Value 7 Reserved R 0 6 4 ALARM_MIN1 2nd digit of minutes Range from 0 to 5 R W 000 3 0 ALARM_MIN0 1st digit of minutes Range from 0 to 9 R W 0000 Table 7 135 Alarm Hours Register ALARM_HOURS_REG Bit Name Value Function R W Reset Value 7 ALARM_PM_nAM Only used in PM_AM mode otherwise 0 R 0 0 AM 1 PM 6 Reserved R 0 5 4 ALARM_HOUR1 2nd digit of hours Ra...

Page 543: ...0 to 9 R W 0001 Table 7 137 Alarm Months Register ALARM_MONTHS_REG Bit Name Function R W Reset Value 7 5 Reserved R 000 4 ALARM_MONTH1 2nd digit of months Range from 0 to 1 R W 0 3 0 ALARM_MONTH0 1st digit of months Range from 0 to 9 R W 0001 Table 7 138 Alarm Years Register ALARM_YEARS_REG Bit Name Function R W Reset Value 7 4 ALARM_YEAR1 2nd digit of years Range from 0 to 9 R W 0000 3 0 ALARM_YE...

Page 544: ...running RTC_DISABLE can be written to 1 to disable RTC clock Behavior is unpredictable if this bit is reset to 0 after having been set to 1 SET_32_COUNTER must only be used when the RTC is frozen The set operation is asynchronous which means the RTC counter is frozen to the compensation value as long as this bit is set The correct sequence reset STOP_RTC freezes RTC set SET_32_COUNTER bit set STOP...

Page 545: ... to this bit The alarm interrupt keeps its low level until the MPU writes 1 in the ALARM bit of this register The timer interrupt is a low level pulse 15 µs duration The STOP_RTC signal is synchronized on the 32 kHz clock so only 1 clock period can elapse between the write to STOP_RTC and the RTC actually being stopped The RUN bit shows the actual state of the RTC Table 7 141 RTC Interrupts Regist...

Page 546: ...one 32 kHz oscillator period every hour MPU must write FFFF into RTC_COMP_MSB_REG and RTC_COMP_LSB_REG To remove one 32 kHz oscillator period every hour MPU must write 0001 into RTC_COMP_MSB_REG and RTC_COMP_LSB_REG The 7FFF value is forbid den Table 7 143 RTC Compensation MSB Register RTC_COMP_MSB_REG Bit Name Function R W Reset Value 7 0 RTC_COMP_MSB Indicates number of 32 kHz periods to be adde...

Page 547: ...n software and this must be done before any transmit and receive from the module is performed The mode is assumed static during operation of the device From a timing perspective both the 1 Wire and the HDQ protocols use HDQ timing 7 15 1 Functional Description The module is intended to work with both the HDQ and the 1 Wire protocols The protocols use a single wire to communicate between the master...

Page 548: ...and address and data is the responsibility of the firmware The master engine provides for only one data TX register HDQ is a return to 1 protocol This means that after a data byte either command address write data for writes or just command address for reads is sent to the slave the host pulls the line high This is accomplished in the OMAP5910 device by setting the line to high with an external pu...

Page 549: ...the TX write register 2 Write 0 to R W bit 1 to the go bit and wait for TX complete interrupt 3 Write 1 to the R W bit of the control and status register to indicate a read 4 Write 1 to the go bit of the control and status register to start the actual read This step and the above step can be done at the same time a The hardware detects a low going edge of the line created by the slave and receives...

Page 550: ...ulse is sent by setting the INIT bit and the GO bit in the con trol and status register A presence detect is indicated in the appropriate bit of the register If no presence is received then a time out bit is set in the status register The initialization bit is cleared at the end of the initialization pulse Also the presence detect and the time out bits are cleared at the end of the initialization ...

Page 551: ...e c The completion of the operation sets the TX complete flag in the inter rupt status register If interrupts are masked no interrupt is generated The interrupt status register is always cleared at the beginning of any read or write operation d At the end of the write the go bit is cleared 4 If interrupt is enabled software must read the interrupt status register to clear the interrupt 5 Repeat fo...

Page 552: ...ftware must read the interrupt status register to determine if RX was completed or whether there was a time out 8 Software does a read of the RX buffer register to retrieve the read data from slave 9 Repeat for each successive byte 1 Wire Bit Mode Operation A single bit mode can be entered by writing to the appropriate bit in the control and status register In this mode only one bit of data is rec...

Page 553: ...in the BQ2023 The master works at the timing of the HDQ interface which encompasses the HDQ and the 1 Wire timing Therefore in 1 Wire mode the master runs slower than the full performance capability of the protocol Figure 7 65 Read Timing Diagram Must be driven low by host for DS driven low by slave on HDQ tCYC tODHO tODD Read 0 Read 1 tREC tRSTRB Figure 7 66 Reset Timing Diagram Sent by host tRST...

Page 554: ...te Machine 1 Reset Time out 0 Go 0 IDLE TX Write data TX complete Bits sent 8 Rnw 0 Go 1 TX complete 1 Time out 0 TX complete 0 Time out 0 7 15 1 4 Read State Diagram Figure 7 69 Read State Machine 1 Reset Time out 1 Go 1 IDLE Time out Receiving 8 bits Rnw 0 Go 1 Go 0 Time out HDQ 1 ...

Page 555: ...etion of a byte read in both modes Cleared at beginning of read command Presence detect time out J In 1 Wire mode it indicates that it is now valid to check the presence detect received bit Cleared at beginning of initialization sequence J In HDQ mode it indicates that after a read command was issued by the host the slave did not pull the line low within specified time In HDQ mode bit is cleared a...

Page 556: ...al Interface The HDQ and 1 Wire battery monitoring serial interface module implements the hardware protocol of the master function of the TI Benchmarq HDQ and the Dallas Semiconductor 1 Wire protocol The module works off a command structure that is programmed into transmit command registers The received data is in the received data register The firmware is responsible for doing the correct sequenc...

Page 557: ...A read is not performed from the interrupt status register or receive buffer register unless the processor has been interrupted by the peripheral After the release of the go bit in the control and status register no access to the TX write data buffer or the control and status registers is performed until the processor has been interrupted by the peripheral Polling of the interrupt status register ...

Page 558: ...nown read only when data is ready 23 16 Reserved read aliased to bits 7 0 writes ignored ready 15 8 Reserved read aliased to bits 7 0 writes ignored 7 0 Next received character 31 24 Interrupt status register Bit is set to 1 if cause of interrupt Read of the clears all interrupts that have been set Reserved read aliased to bits 7 0 writes ignored Read only read to clear at 8h0C 23 16 Reserved read...

Page 559: ...ites ignored 7 Single bit mode for 1 Wire R W 0 6 Interrupt mask R W 0 0 Disable interrupts 1 Enable interrupts 5 Power down mode R W 0 0 Disable clocks 1 Enable clocks 4 Go bit Write 1 to send the appropriate commands Bit returns to 0 after the command is complete R W 0 3 Presence detect received 1 Wire mode only R 0 0 Not detected 1 Detected 2 Write 1 to this bit and set the GO bit to send Initi...

Page 560: ...with the number of frame start rising edges that occur during the programmable FARC period A control and configuration register CTRL allows you to put the module into either continuous or halt mode In continuous mode the FSC register is periodically updated with a new value each time the FARC register value is met and a new count is automatically initiated In halt mode the FSC register is updated ...

Page 561: ... 7 16 2 Synchronization and Counter Control Because frame start and frame synchronization signals are from different time domains the FAC module synchronizes these two signals to the system clock domain and uses the synchronized signals as the count enables The actual counters for frame synchronization and frame start are clocked by the system clock The synchronization mechanism is based on the as...

Page 562: ...djustment Counter 7 200 Figure 7 72 FAC Module Counters and Clock Synchronization FARC REG FSC Frame start Sync circuit EN Sync circuit FSM EN Frame sync Frame start System clock REG counter Frame sync counter ...

Page 563: ... Frame Start Signals DFF3 Frame sync DFF2 DFF1 TFF frame start System clock XOR Synced signal Figure 7 74 shows the actual waveforms of at the output of each flip flop and the XOR output Figure 7 74 Synchronization Circuit Waveforms DFF1 output TFF output Frame start sync DFF2 output DFF3 output XOR output System clock ...

Page 564: ...the system is awakened 12 MHz provided to the MPU the MPU programmable peripheral clock PERCLK is used as the source clock for the FAC clock for more detail see Chapter 15 Clock Generation and System Reset Management The MPU TIPB reset MPU_PER_RST resets the FAC 7 16 5 Software Interface Table 7 146 lists the FAC registers Table 7 147 through Table 7 150 describe the register bits Table 7 146 FAC ...

Page 565: ...ount is met with the new count value If CNT is zero the counting is in halt mode The frame start count register is updated when the frame adjustment reference count is met and the counting halts until the software reads the FSC register A level sensitive interrupt can be generated to indicate that the frame start counting is finished and the FSC register is loaded with a new count value The interr...

Page 566: ...gister CTRL Bit Name Function Reset Value 15 3 Reserved 0 2 INT_ENABLE When this bit is set to a 1 an interrupt is generated when FSC is updated If this bit is set to a 0 no interrupt is generated The INT_ENABLE bit is independent of the CNT bit The interrupt can be enabled or disabled in either continuous mode or halt mode 0 1 RUN Enables operation of the counter When this bit is set to zero the ...

Page 567: ...wing DSP private peripherals and their associated memory and mapping Timers Watchdog timer Interrupt handlers Topic Page 8 1 DSP Private Peripherals 8 2 8 2 Timers 8 3 8 3 Watchdog Timer 8 10 8 4 Interrupt Handlers 8 15 8 5 DSP Interrupt Interface 8 26 Chapter 8 ...

Page 568: ...erals McBSP1 McBSP3 MPU public peripherals USB Host I F JTAG emulation I F OSC 12 MHz Clock OSC OMAP5910 ETM9 Timers 3 MPU DSP shared peripherals Mailbox MPU private peripherals Timers 3 16 Memory interface Reset External clock MPU Bus 32 kHz 1 5M bits traffic controller TC Watchdog timer Level 1 2 interrupt handlers Configuration registers Clock and reset management Watchdog timer Level 1 2 Priva...

Page 569: ... 8 1 Timer Interrupt Levels Figure 8 2 DSP Timers Divide clock down by 2 PTV 1 READ_TIM_HI READ_TIM_LO LOAD_TIM_HI LOAD_TIM_LO CLK CLK 2 PTV 1 If autoreload then load when timer underflows Interrupt when timer underflows 32 bit timer Timer 1 INT23 Timer 2 INT22 Timer 3 INT8 DSPTIM_CK 12 MHz Load when timer starts Divide clock down by 2 PTV 1 READ_TIM LOAD_TIM CLK CLK 2 PTV 1 If autoreload then loa...

Page 570: ...ck timer value PTV field of the control timer register shown in Table 8 2 PTV Divisors 32 Bit Timers Table 8 2 PTV Divisors 32 Bit Timers PTV Divisor 0 2 1 4 2 8 3 16 4 32 5 64 6 128 7 256 The timer interrupt period is calculated as follows tint tclk x LOAD_TIM 1 x 2 PTV 1 where tclk is the clock period of the input clock The load timer register LOAD_TIM holds the value loaded when the timer passe...

Page 571: ...t to 0 to stop the timer When the timer stops the decrementer content is frozen Set the autoreload bit AR of the control timer to 0 to have the timer decrement from the loaded value down to zero and then stop Set the AR to 1 to have the timer continue A new value from the load register is loaded into the timer when it passes though zero or when it starts An interrupt is produced when the correspon...

Page 572: ...IMER Bit Name Value Descriptions Reset Value 15 8 Unused 7 SOFT This bit is used with the FREE bit to determine peripheral state when a breakpoint is encountered Used in emulation mode 0 0 Peripheral halts immediately either retaining or discarding current state 1 Peripheral stops after completion of current task 6 FREE This bit is used with the SOFT bit to determine peripheral state when a breakp...

Page 573: ...IPB writes on the DSP TIPB Table 8 6 Load Timer High Register LOAD_TIM_HI Bit Name Description Reset Value 15 0 LOAD_TIM_HI This value is loaded when the timer passes through 0 or when it starts LOAD_TIM_HI is the same as LOAD_TIM 31 16 Undefined Table 8 7 Load Timer Low Register LOAD_TIM_LO Bit Name Description Reset Value 15 0 LOAD_TIM_LO This value is loaded when the timer passes through 0 or w...

Page 574: ...ts of the read timer register READ_TIM are stored in a temporary register 2 Perform a TIPB read transaction to read the lower 16 bits of the read timer register READ_TIM offset 10 During this read the value of the tem porary register is forwarded onto the TIPB bus instead of reading the read timer register READ_TIM again This is done because the TIMER can change value between the two TIPB read tra...

Page 575: ... Registers Register Name Description R W Size Bits Word Address Reset Value CNTL_TIMER2 Timer control register R W 16 0x02C00 0x0000 LOAD_TIM2 Value that must be loaded into timer when it passes through 0 W 32 0x02C02 U READ_TIM2 Timer counter R 32 0x02C04 U Table 8 12 DSP Timer 3 Registers Register Name Description R W Size Bits Word Address Reset Value CNTL_TIMER3 Timer control register R W 16 0...

Page 576: ...probably the reason Be certain to disable the watchdog timer before placing the DSP processor in deep sleep mode It must not be left configured as a watchdog timer The watchdog timer underflow resets the DSP If the input clock is 12 MHz and the watchdog timer values are left at their power up state the value loaded into the load timer register LOAD_TIM is set to the maximum value of 0xFFFF reset o...

Page 577: ...aracteristics of the watchdog timer for different input frequencies Table 8 15 Watchdog Timer Characteristics Input Clock tclk Clock Period LOAD_TIM tint Timer Interrupt Period PTV 7 12 MHz 1167 ns 0001 597 34 µs 12 MHz 1167 ns FFFF max interrupt period 19 57 s The 12 MHz clock is divided by 14 If LOAD_TIM 0 and AR auto reload mode 1 the timer is always 0 and can never decrement Here the timer int...

Page 578: ...n this case the value loaded into the load timer register LOAD_TIM is set to the maximum value 0xFFFF as on power up In watchdog mode the control timer register CNTL_TIMER must not be used The watchdog timer can not be stopped by clearing bit 7 ST and the prescale value is 7 regardless of the PTV field Autoreload and one shot do not apply because if the counter underflows the processor is reset an...

Page 579: ... Read timer R 16 x003402 0xFFFF TIMER_MODE Timer mode R W 16 x003404 0x8000 Table 8 17 Control Timer Register CNTL_TIMER Bit Name Value Description Reset Value 15 12 Reserved 11 9 PTV Prescale clock timer value 0 8 AR 0 One shot timer 0 1 Autoreload timer If one shot mode is selected AR 0 this bit is automatically reset by internal logic when timer is equal to 0 7 ST 0 Stop timer 0 1 Start timer 6...

Page 580: ...r FFFF Table 8 20 Timer Mode TIMER_MODE Bit Name Value Description Reset Value 15 WATCHDOG Write access 1 Switch back from timer mode to watchdog Writing a 0 in this bit has no effect 1 Read access Status of timer mode 0 Timer is used as a general purpose counter 1 Timer is used as a watchdog timer 14 8 Reserved 7 0 WATCHDOG_DIS Write access only Writing a predefined sequence 0xF5 followed by 0xA0...

Page 581: ...tions All of these interrupts are routed to the DSP core interrupt inputs Interrupts are handled through two cascaded interrupt controllers One is the level 1 handler and is inside the DSP core The second is the level 2 handler and is external to the DSP and functions similarly to the MPU interrupt handler The 22 level 1 interrupts are handled by the DSP internal interrupt controller provided by t...

Page 582: ...or the DSP to recognize it To ensure that this requirement is met the DSP is pro vided with and internal hardware module called the DSP interrupt interface described in Section 8 5 Table 8 21 Level 1 Interrupt Mapping Level 1 Interrupt Priority DSP Interrupt Vector Location DSP IFR_bit IMT_bit 26 0 RESET 0 FFFF00 NMI 1 FFFF08 Emulator Test 3 INT2 FFFF10 2 Level 2 INTH FIQ 5 INT3 FFFF18 3 TC_ABORT ...

Page 583: ...ines whether it is to be level or edge sensitive and determines to which DSP interrupt fast inter rupt request FIQ or low priority interrupt request IRQ the incoming interrupt goes If several interrupts have the same priority level assigned they are serviced in a predefined order All level 2 interrupts are routed to FIQ IRQ output is unconnected The interrupt controller also provides a 16 bit soft...

Page 584: ...ction flip_flops Edge or level direction Process next pending IRQ Process next pending FIQ Generate IRQ Generate FIQ FIQ To DSP level 1 16 incoming interrupts Interrupt level register 0 ILR0 Interrupt level register 1 ILR1 Interrupt level register 16 ILR16 SIR_IRQ Binary coded source IRQ reigster SIR_FIQ Binary coded source RIQ register Interrupt handler T I P B ...

Page 585: ...s reset and restarted if necessary 4 To determine which incoming interrupt has requested a DSP action the source interrupt encoded register SIR_FIQ must be read The register contains an encoded number that tells which interrupt lines are being serviced After that it runs the corresponding subroutine 5 To finish the interrupt sequence DSP software must first clear the interrupt bit in the interrupt...

Page 586: ...bit 2 00 R W 6 bits 0x004810 ILR3 Interrupt priority level bit 3 00 R W 6 bits 0x004812 ILR4 Interrupt priority level bit 4 00 R W 6 bits 0x004814 ILR5 Interrupt priority level bit 5 00 R W 6 bits 0x004816 ILR6 Interrupt priority level bit 6 00 R W 6 bits 0x004818 ILR7 Interrupt priority level bit 7 00 R W 6 bits 0x00481A ILR8 Interrupt priority level bit 8 00 R W 6 bits 0x00481C ILR9 Interrupt pr...

Page 587: ...n the storage element IRQ FIQ output and SIR_IRQ SIR_FIQ registers are reset only if the bit of ITR register corresponding to the interrupt that requested DSP action is already cleared or masked The time when this ITR bit is reset depends on the sensitivity of the incoming interrupt In case of an edge sensitive interrupt the IT register bit is cleared when reading SIR_IRQ SIR_FIQ register Otherwis...

Page 588: ...ng this register clears the corresponding bit in the interrupt input register ITR if the interrupt is set as edge sensitive This register will not normally be used since all level 2 DSP interrupts must be configured as FIQ to generate DSP interrupts because IRQ is not connected Table 8 26 FIQ Binary Coded Source Register SIR_FIQ Bit Name Type Reset Value 3 0 FIQ_NUM R 0 In order to save software p...

Page 589: ...st Note All level 2 DSP interrupts must be configured as FIQ to generate DSP interrupts because IRQ is not connected R W 0 The software interrupt set register is a 16 bit read write register Writing a 1 to any bit generates an interrupt to the DSP if the corresponding ILR register is set as edge triggered otherwise no interrupt is generated A 0 is always returned from a read to this register Exter...

Page 590: ...is falling edge sensitive R W 0 1 The corresponding interrupt is low level sensitive 0 FIQ 0 0 The corresponding interrupt is routed to IRQ R W 0 1 The corresponding interrupt is routed to FIQ Note Since IRQ is not connected only the FIQ setting is useful This bit must be set to 1 for the corresponding level 2 interrupt to cause a DSP interrupt Note Assuming that all interrupts have the same prior...

Page 591: ... TX Level IRQ_06 MCSI1 RX Level IRQ_07 MSCI2 TX Level IRQ_08 MCSI2 RX Level IRQ_09 MCSI1 frame error Level IRQ_10 MCSI2 frame error Level IRQ_11 Reserved IRQ_12 Reserved IRQ_13 Reserved IRQ_14 Reserved IRQ_15 Level sensitive interrupts are level active the interrupt line must remain asserted until it has been acknowledged Edge triggered interrupts are edge triggered just an edge is required for ge...

Page 592: ... process consists of an edge registration flip flop and a chain of four positive edge triggered timing flip flops A negative transi tion falling edge on the incoming nXIRQ N interrupt line sets the edge regis tration flip flop to 1 and the output of this flip flop is the edge triggered inter rupt In addition to activating the output interrupt line nIRQ N this output also propagates through the fou...

Page 593: ...s two separate incidents This minimal time does not take into account the processing time of the interrupts once recognized by the DSP processor and this time must be taken into account to derive the minimum time between interrupts from a system perspective Figure 8 5 Interrupt Channel Implementation Interrupt channel XIRQ N SCL D Q SCL D Q SCL D Q SCL D Q Q ACL D Q D Q D Q D Q D Q XIRQOUT N CLKOU...

Page 594: ...es this as only one interrupt because there was only one falling edge of nIRQ N 8 5 4 Internal Registers DSP word start address 0x003800 Bit width 16 bits DSP word address of a register start word address offset address The DSP_INT_IF has two control registers one 16 bit and one 7 bit and two clear command registers one 16 bit and one 7 bit The control registers are used exclusively for assigning ...

Page 595: ...Bit Name Value Description Type Reset Value 15 8 Reserved 0 7 Host Interrupt Trig Level This bit defines whether the host interrupt is edge or level sensitive R W 0 NHOSTINT is level sensitive 1 NHOSTINT is edge sensitive 6 NMI Trig Level This bit defines whether the nonmaskable interrupt is edge or level sensitive The NMI channel corresponds to the DSP NMI interrupt R W 0 0 NMI is level sensitive...

Page 596: ...t Value 15 0 Reset_CHx Reset CHx if a 1 is written into RST_LVL_LO x and CHx is configured as level sensitive interrupt where CHx corresponds to interrupt channels nXIRQ 15 0 0 0 0 Do not reset CHx 1 Reset interrupt channel CHx if level is configured as level sensitive A write to the level sensitive clear high register RST_LVL_HI whose offset address is 03 clears interrupts from interrupt channels...

Page 597: ...upt channel CHx if level is configured as level sensitive Figure 8 6 Level Sensitive Interrupt Clear Commands Clear assignments 15 11 14 10 9 8 7 6 5 4 3 2 1 0 Clear interrupt channel 0 Clear interrupt channel 1 Clear interrupt channel 2 Clear interrupt channel 3 Clear interrupt channel 4 Clear interrupt channel 5 Clear interrupt channel 6 Clear interrupt channel 7 Clear interrupt channel 8 Clear ...

Page 598: ...ic peripherals for the OMAP5910 multimedia processor Topic Page 9 1 Introduction 9 2 9 2 McBSPs 9 3 9 3 McBSP1 9 4 9 4 McBSP3 9 11 9 5 Multichannel Serial Interfaces 9 27 9 6 MCSI1 9 52 9 7 MCSI2 9 54 9 8 McBSP and MCSI Memory and Peripheral Mapping 9 56 Chapter 9 ...

Page 599: ...ipherals bus DSP public shared pheripheral bus 32 MPU public 16 DSP DSP public peripherals McBSP1 McBSP3 MPU public peripherals USB Host I F JTAG emulation I F OSC 12 MHz Clock OSC OMAP5910 ETM9 Timers 3 MPU DSP shared peripherals Mailbox MPU private peripherals Timers 3 16 Memory interface Reset External clock MPU Bus 32 kHz 1 5M bits traffic controller TC Watchdog timer Level 1 2 interrupt handl...

Page 600: ...ce Guide literature number SPRU317 Key features of the McBSPs include Full duplex communication DMA support for both RX and TX transfers Double buffered data registers which allow a continuous data stream Independent framing and clocking for receives and transmits External shift clock generation or an internal programmable frequency shift clock Multichannel transmits and receives of up to 128 chan...

Page 601: ...ver can only operate in slave mode on McBSP1 and McBSP3 9 3 McBSP1 This section provides information specific to McBSP1 of the OMAP5910 device For a full description of McBSP functionality and register descriptions see the TMS320C55x DSP Peripherals Reference Guide literature number SPRU317 9 3 1 McBSP1 Pin Descriptions Table 9 1 identifies the McBSP1 I O pins Table 9 1 McBSP1 Pin Descriptions Pin...

Page 602: ...U Interrupts DMA requests I F 16 RX DMA_REQ_9 TX DMA_REQ_8 RX interrupt IRQ_3 TX interrupt IRQ_2 DSP public peripheral bus DSPPER_nRST DSPXOR_CK RX interrupt IRQ_13 TX interrupt IRQ_12 RX DMA_REQ_9 TX DMA_REQ_8 12 MHz DSP DMA DSP level 2 interrupt handler System DMA MPU level 2 interrupt handler DSP peripheral bridge Clock generation and management Note You can use the AUXON feature to gate the fu...

Page 603: ...e internal feedback from CLXX DR Receive data McBSP1 DR CLKS Clock input McBSP1 CLKS 9 3 2 McBSP1 Interrupt Mapping Table 9 3 identifies the McBSP1 interrupts McBSP1 generates level 2 interrupts for both the DSP and the MPU Table 9 3 McBSP1 Interrupt Mapping Incoming Interrupts Level 2 DSP Interrupt Level 2 MPU Interrupt McBSP1 TX interrupt IRQ_02 IRQ_12 McBSP1 RX interrupt IRQ_03 IRQ_13 9 3 3 McB...

Page 604: ...e frame synchronization and bit clock Section 9 3 4 1 through Section 9 3 4 9 explain how to set up the McBSP registers for I2S slave mode with 16 bit transfers using DMA support Figure 9 3 I2S Audio Codec Interface mcbsp1_sync OMAP5910 McBSP1 CLKS FSX_OUT FSX_OE FSX_IN CLKX_OUT CLKX_OE CLKX_IN DX_OUT DX_OE FSR_OUT FSR_OE FSR_IN CLKR_OUT CLKR_OE CLKR_IN DR_IN 0 mcbsp1_bclk mcbsp1_dout mcbsp1_din m...

Page 605: ...ed 13 0b Set serial port mode for DX FSX and CLKX pins 12 0b Set serial port mode for DR FSR and CLKR pins 11 0b TX frame synchronization signal derived by external source 10 0b RX frame synchronization signal derived by external source 9 0b CLKX set input pin and derived by external source 8 0b CLKR set input pin and derived by external source 7 0b Sample rate generator input clock mode bit 6 0b ...

Page 606: ...ation DSP_Write 0x80a1 RCR2 Bit Config Value Description 15 1b Set dual phase frame 14 8 000 0000b Set receive frame length as one word per frame 7 5 101b Set receive word length as 32 bits per frame 4 3 00b Don t care for single phase frame 2 0b Set FSR not ignore after the first resets the transfer 1 0 01b Set data delay as 1 bit 9 3 4 4 Transmit Control Register Configuration DSP_Write 0x00a0 X...

Page 607: ...RGR 1 2 It is not necessary to configure the sample rate generator because external clocks and frames are provided appropriately for CLKX and FSX 9 3 4 6 DMA Configuration It is necessary to configure the REVT and XEVT bit for the DMA receive and transmit synchronized invent 9 3 4 7 Interrupt Flag Configuration and Clear ILR MIR 1 DSP_Write ILR set ILR appropriately for the interrupt handling prio...

Page 608: ...A3 A2 A1 A0 B29 B30 B31 B1 B0 9 4 McBSP3 This section provides information specific to McBSP3 on the OMAP5910 device For a full description of McBSP functionality and register definitions see the TMS320C55x DSP Peripherals Reference Guide literature number SPRU317 9 4 1 McBSP3 Pin Descriptions Table 9 10 identifies the McBSP3 I O pins Table 9 10 McBSP3 Pin Descriptions Pin I O Direction Descriptio...

Page 609: ...X Interrupt IRQ_1 TX Interrupt IRQ_0 DSP public peripheral bus DSPPER_nRST DSPXOR_CK RX Interrupt IRQ_11 TX Interrupt IRQ_10 RX DMA_REQ_11 TX DMA_REQ_10 12 MHz DSP DMA DSP level 2 interrupt handler System DMA MPU level 2 interrupt handler DSP peripheral bridge Clock generation and management DSP peripheral fixed clock 12 MHz 0 0 0 Configuration register Configuration register Note You can use the ...

Page 610: ...DX FSR Receive frame input only Not available internal feedback from FSX CLKR Receive clock input only Not available internal feedback from FSX DR Receive data McBSP3 DR MOD_MCBSP3_MODE_R 1 In this case the McBSP3 is half duplex master slave for transmission slave for reception This mode utilizes the paths shown as dashed lines in Figure 9 5 Table 9 12 lists the McBSP3 signals available in this mo...

Page 611: ... Line DSP DMA Request Line MPU McBSP3 TX DMA_REQ_10 DMA_REQ_10 McBSP3 RX DMA_REQ_11 DMA_REQ_11 9 4 4 McBSP3 Application Example Optical Interface With the assistance of two GPIOs McBSP3 is configured to connect to an external optical audio interface see Figure 9 6 device such as the Sanyo LC89051V The CLKS signal is the active input clock for the McBSP modem block The active input clock can be cha...

Page 612: ...KX_OUT CLKX_OE CLKX_IN DX_OUT DX_OE FSR_OUT FSR_OE FSR_IN CLKR_OUT CLKR_OE CLKR_IN DR_IN 0 mcbsp3_clk mcbsp3_dout mcbsp3_din Optical audio Interface device DAU_CLK DAU_SCLK DAU_DOUT DAU_SWDT DAU_DIN DAU_SRDT DAU_DQSY output DAU_XLAT input DSP peripheral programmable clock DSPXOR_CK Tie off Config reg OMAP5910 GPIOs Config reg ...

Page 613: ...oopback mode 14 13 00b Right justify and zero fill MSBs in DRR 12 11 10b Enabled clock stop mode 10 8 000b Reserved 7 0b Turn off the DX enabler 6 0b Reserved 5 4 00b Set RINT driven by RRDY mode 3 0b No synchronization error 2 0b RBR is not in overrun condition 1 0b Receiver is not ready 0 0b Disabled the serial port receiver and in reset state DSP_Write 0x0000 SPCR2 set up SPCR2 as initial confi...

Page 614: ...1b TX frame synchronization signal driven by internal generator 10 0b RX frame synchronization signal derived by external source 9 1b McBSP is set master and generate clock by internal source 8 0b CLKR set input pin and derived by external source 7 0b Sample rate generator input clock mode bit 6 0b CLKS pin status no meaning in OMAP5910 5 0b DX pin status 4 0b DR pin status 3 1b Set FSX polarity a...

Page 615: ...ame length as one word per frame 7 5 000b Set receive word length as 8 bits per frame 4 0 0 0000b Reserved DSP_Write 0x0000 RCR2 set up RCR2 per below configuration Table 9 18 Receive Control Register 2 Configuration DSP_Write 0x0000 RCR2 Bit Config Value Description 15 0b Set single phase frame 14 8 000 0000b Don t care for single phase frame 7 5 000b Don t care for single phase frame 4 3 00b Set...

Page 616: ... transmit frame length as one word per frame 7 5 000b Set transmit word length as 8 bits per frame 4 0 0 0000b Reserved DSP_Write 0x0000 XCR2 set up XCR2 per below configuration Table 9 20 Transmit Control Register 2 Configuration DSP_Write 0x0000 XCR2 Bit Config Value Description 15 0b Set single phase frame 14 8 000 0000b Don t care for single phase frame 7 5 000b Don t care for single phase fra...

Page 617: ...set up SRGR2 per below configuration Table 9 22 Sample Rate Generator 2 Configuration SRGR 1 2 DSP_Write 0x2000 SRGR2 Bit Config Value Description 15 0b Set sample rate generator clock synchronization 14 0b Set clock polarity 13 1b Sample rate generator clock derived from DSP clock 12 0b Set frame synchronization 11 0 0000 0000 0000b These bit ignored by the FSGM 0 SRGR2 12 12 Wait two CLKSRG cloc...

Page 618: ...g SPCR 1 2 1 DSP_write SPCR1 or 0x0001 SPCR1 enabled receive port 2 DSP_write SPCR2 or 0x0001 SPCR2 enabled transmit port Note Wait two sample rate clock cycles for McBSP stability 9 4 4 10 Transmit and Received Data Loading TX_INT Handling in Interrupt Survive Routine For data transmit 1 DSP_Write DXR transmit data loading to DXR 2 DSP_Read DRR wait for data read after the RINT For two data recei...

Page 619: ... Register Configuration DSP_Write 0x1000 SPCR1 set up SPCR1 per below configuration Table 9 23 Serial Port Control Register Configuration DSP_Write 0x1000 SPCR1 Bit Config Value Description 15 0b Disables digital loopback mode 14 13 00b Right justify and zero fill MSBs in DRR 12 11 10b Enables clock stop mode 10 8 000b Reserved 7 0b Turns off the DX enabler 6 0b Reserved 5 4 00b Set RINT driven by...

Page 620: ...0b Set serial port mode for DR FSR and CLKR pins 11 1b TX frame synchronization signal driven by internal generator 10 0b RX frame synchronization signal derived by external source 9 1b McBSP is set master and generate clock by internal source 8 0b CLKR set input pin and derived by external source 7 0b Sample rate generator input clock mode bit 6 0b CLKS pin status no meaning in OMAP5910 5 0b DX p...

Page 621: ...as one word per frame 7 5 000b Set receive word length as 8 bits per frame 4 0 0 0000b Reserved DSP_Write 0x0000 RCR2 set up RCR2 per below configuration Table 9 26 Receive Control Register 2 Configuration DSP_Write 0x0000 RCR2 Bit Config Value Description 15 0b Set single phase frame 14 8 000 0000b Set receive frame length as one word per frame 7 5 000b Set receive word length as 8 bits per frame...

Page 622: ...ow configuration Table 9 28 Transmit Control Register 2 Configuration DSP_Write 0x0000 XCR2 Bit Config Value Description 15 0b Set single phase frame 14 8 000 0000b Set transmit frame length as one word per frame 7 5 000b Set transmit word length as 8 bits per frame 4 3 00b Set no companding data and transfer start with MSB first 2 0b Set FSX ignore after the first resets the transfer 1 0 00b Set ...

Page 623: ...ut of Reset for Transmit and Receive Starting SPCR 1 2 1 ARM_write SPCR1 or 0x0001 SPCR1 enabled receive port 2 ARM_write SPCR2 or 0x0001 SPCR2 enabled transmit port 9 4 4 21 Data Transfer DMA Channel The DMA channel transfers the received data to the appropriate data buffer and transfers the new transmit data to the appropriate TX buffer Clear interrupts flag on ITR when taking the interrupt hand...

Page 624: ...maximum number of operating conditions Master or slave clock control transmission clock and frame synchroniza tion pulse Programmable transmission clock frequency Single channel or multichannel x16 frame structure Programmable word length 3 to 16 bits Full duplex transmission Programmable frame configuration J Continuous or burst transmission J Normal or alternate framing J Normal or inverted fram...

Page 625: ...on pulse generated from an external device Control bit MAIN_ PARAMETERS _REG 6 MCSI_MODE 1 Master 0 Slave Single Channel Multichannel The frame structure can be either single channel based one channel per frame or multichannel based with the number of channels fixed at 16 Control bit MAIN_ PARAMETERS _REG 7 MULTI 1 Multichannel 0 Single channel Short Long Framing The frame synchronization pulse du...

Page 626: ...ne frame synchronization pulse at each frame Control bit MAIN_ PARAMETERS _REG 5 FRAME_MODE 1 Continuous 0 Burst Normal Inverted Clock The polarity of the clock can be either normal with writing on positive edge clock and reading on negative edge clock or inverted with writing on negative edge clock and reading on positive edge clock Control bit MAIN_ PARAMETERS _REG 4 CLOCK_POLARITY 1 Inverted 0 ...

Page 627: ...e Size To add any overhead bits at the end of each frame set the number of desired overhead bits in the over_size_register Control bit OVER_CLOCK_REG 9 0 OVER_CLK 0 OVER_CLK 1023 Transmission Clock Frequency In master mode the clock frequency is derived from the 12 MHz master clock and can be programmed from 5 8 kHz to 6 MHz in increments of 83 ns Control bit CLOCK_FREQUENCY_REG 10 0 CLK_FREQ 2 CL...

Page 628: ...for clock J Bit 3 0 0111b 8 bit data DSP_Write 0x0700 INTERRUPTS_REG all interrupts are enabled DSP_Write 0x0000 OVER_CLOCK_REG DSP_Write 0x0001 CONTROL_REG start MCSI Transmit Data Loading TX_INT ISR DSP_Write TX_REG Received Data Loading RX_INT ISR DSP_Read RX_REG Stop MCSI DSP_Write 0x0000 CONTROL_REG disable MCSI clock DSP_Write 0x0002 CONTROL_REG reset MCSI registers Figure 9 9 Communication ...

Page 629: ... 1 at the bit location in the status register The following list provides interrupt flag bit associations RX_INT RX_READY flag and acknowledge bit TX_INT TX_READY flag and acknowledge bit FERR_INT FRAME _ERROR flag and acknowledge bit Receive Interrupt The receive interrupt is generated every frame after the completion of the reception of a data word In single channel mode the interrupt is generat...

Page 630: ... the transmis sion of a data word In single channel mode the interrupt is generated one clock period after the beginning of the transmission of the word In multichannel mode the interrupt is generated one clock period after the transmission of the word of the channel whose number is defined by the NB_CHAN_IT_RX parameter of INTERRUPTS_REG register Figure 9 11 Transmit Interrupt Timing Diagram CLK ...

Page 631: ...the frame duration is longer than the expected value then the interrupt is generated one clock period after the number of the over_size clock periods as defined in OVER_CLOCK parameter If the frame duration is smaller than the expected value then the interrupt is generated one clock period after the occurrence of the next frame pulse first active edge Figure 9 12 Frame Duration Error Too Many Long...

Page 632: ... masked To validate an interrupt If in multichannel mode the RX and TX interrupts can be configured to occur in a dedicated channel of the frame 1 16 DSP_WRITE channel_nb INTERRUPTS_REG 3 0 for RX_INT INTERRUPTS_REG 7 4 for TX_INT Unmask the interrupt DSP_WRITE 1 J INTERRUPTS_REG 8 for RX_INT J INTERRUPTS_REG 9 for TX_INT J INTERRUPTS_REG 10 for FERR_INT On interrupt occurrence DSP_READ J STATUS_R...

Page 633: ...t DMA Transfers A new transmit DMA transfer is initiated during the transmission of the last channel of a frame at which time all data in the transmit registers TX_REGs has been moved to shift registers the TX_REGs are now ready to be rewritten If N channels are used the DMA controller successively accesses all consecu tive registers between TX_REG 0 and TX_REG N 1 If some channels between TX_REG ...

Page 634: ...s between RX_REG 0 and RX_REG N 1 are not used the DMA controller reads dummy values when addressing these unused registers see Figure 9 15 Figure 9 15 Receive DMA Transfers MCSI dma add dma data Val0 Ad0 Valn dum Adn TI peripheral bus ad n 1 Ad1 dum Value 0 Empty N Empty n 1 Value n Dummy n 1 Dummy 1 Value 0 Empty N Empty n 1 Value n Empty n 1 Empty 1 MCSI Rx registers MCSI Rx shift registers Ser...

Page 635: ... typical sequence to stop the interface is 1 Disable MCSI clock DSP_WRITE 0x0000 CONTROL_REG The status register keeps its content even after the stop of the transmission The control registers can now be modified 2 Software reset DSP_WRITE 0x0002 CONTROL_REG The software reset initializes the status register Software Reset The MCSI software reset is activated with the SW_RESET bit of the control r...

Page 636: ...gle Channel Alternate Long Framing Figure 9 16 Single Channel Alternate Long Framing T7 T6 T5 T4 T3 T2 T1 T0 T7 T6 T5 T4 T3 T2 T0 T1 First frame Last frame CLK TXD RXD FSYNCH R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0 Single Channel Alternate Long Framing Burst Figure 9 17 Single Channel Alternate Long Framing Burst T7 T6 T5 T4 T3 T2 T1 T0 T7 T6 T5 T4 T3 T2 CLK TXD RXD FSYNCH R7 R6 R5 R4 R3 R...

Page 637: ...R3 R2 OVER_CLOCK_REG 0x0003 Multichannel Normal Short Framing Channel4 Disable Figure 9 19 Multichannel Normal Short Framing Channel4 Disable Channel0 CLK TXD FSYNCH Channel1 Channel2 Channel3 Channel5 Channel6 Channel14 Channel15 Channel0 Multichannel Alternate Long Framing Continuous Burst Figure 9 20 Multichannel Alternate Long Framing Continuous Burst Channel0 CLK TXD FSYNCH Channel1 Channel14...

Page 638: ...CLOCK_REG 0x0013 Single Channel Normal Short Framing Figure 9 22 Single Channel Normal Short Framing T7 T6 T5 T4 T3 T2 T1 T0 T7 T6 T5 T4 T3 T2 T0 T1 First frame Last frame CLK TXD RXD FSYNCH R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0 Single Channel Normal Short Framing Burst Figure 9 23 Single Channel Normal Short Framing Burst T7 T6 T5 T4 T3 T2 T1 T0 T7 T6 T5 T4 T3 T2 CLK TXD RXD FSYNCH R7 R...

Page 639: ...5 T4 T3 T2 T1 T0 T7 T6 T5 T4 T3 T2 T0 T1 First frame Last frame CLK TXD RXD FSYNCH R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0 Single Channel Normal Long Framing Burst Figure 9 25 Single Channel Normal Long Framing Burst T7 T6 T5 T4 T3 T2 T1 T0 T7 T6 T5 T4 T3 T2 CLK TXD RXD FSYNCH R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 OVER_CLOCK_REG 0x0003 ...

Page 640: ...R1 R0 R7 Single Channel Alternate Short Framing Figure 9 27 Single Channel Alternate Short Framing T7 T6 T5 T4 T3 T2 T1 T0 T7 T6 T5 T4 T3 T2 T0 T1 First frame Last frame CLK TXD RXD FSYNCH R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0 Single Channel Alternate Short Framing Burst Figure 9 28 Single Channel Alternate Short Framing Burst T7 T6 T5 T4 T3 T2 T1 T0 CLK TXD RXD FSYNCH R7 R6 R5 R4 R3 R2 ...

Page 641: ...annel selection register is only used in multichannel mode see Table 9 29 Table 9 29 Channel Selection Register CHANNEL_USED_REG Bit Name Access Hardware Reset 15 use_ch15 R W 0 14 use_ch14 R W 0 13 use_ch13 R W 0 12 use_ch12 R W 0 11 use_ch11 R W 0 10 use_ch10 R W 0 9 use_ch9 R W 0 8 use_ch8 R W 0 7 use_ch7 R W 0 6 use_ch6 R W 0 5 use_ch5 R W 0 4 use_ch4 R W 0 3 use_ch3 R W 0 2 use_ch2 R W 0 1 us...

Page 642: ...frequency can be programmed from 5 8 kHz to 6 MHz in steps or increments of 83 ns Clock frequency 12 MHz clk_freq with 2 clk_freq 2047 R W 000 0000 0000 CLK_FREQ division factor of 12 MHz reference clock 2 clk_freq 2047 In master mode this register defines the transmission baud rate from a frequency ratio based on a 12 MHz reference clock The transmission clock frequency can be programmed from 5 8...

Page 643: ...R W 0000 3 0 Number channel for it_rx Channel number for receive interrupt generation 0 Nb_chan 15 R W 0000 Table 9 33 Main Parameters Register MAIN_PARAMETERS__REG Bit Name Value Description Access Hardware Reset 15 14 DMA enable Enable bits for DMA R W 00 00 Normal mode No DMA 01 DMA transmit mode normal receive mode 10 Normal transmit mode DMA receive mode 11 DMA transmit and receive mode 13 11...

Page 644: ... Frame synchronization pulse shape R W 0 0 Short 1 Long 7 Multi single Frame structure R W 0 0 Single 1 Multi 6 MCSI mode Interface transmission mode R W 0 0 Slave 1 Master 5 Continuous burst Frame mode R W 0 0 Burst 1 Continuous 4 clock_polarity Clock edge selection R W 0 0 Positive 1 Negative 3 0 Word size Word size in bits number 2 size 15 with 2 for 3 bits and 15 for 16 bits R W 0000 ...

Page 645: ...W 0 0 0 Disable 1 Enable Note The software reset is applied as long as the MCSI software reset bit is set to 1 A software reset disables the MSCI the MCSI clk enable bit is cleared and initializes the status register It does not modify the other registers To clear an interrupt on the MCSI the DSP must write to the MCSI status regis ter with the bit corresponding to the interrupt set to 1 The MCSI ...

Page 646: ... should always be written as 0 R W 0 0 5 TX underflow Transmit underflow R 0 0 0 No under 1 Under 4 TX ready Flag for transmit interrupt occurrence R W 0 0 0 No int 1 Int 3 RX overflow Receive overflow R 0 0 0 No over 1 Over 2 RX ready Flag for receive interrupt occurrence R W 0 0 0 No int 1 Int 1 Error type few many Too short few or too long frame many status R 0 0 0 Short 1 Long 0 Frame error Er...

Page 647: ...14 R U 13 b13 R U 12 b12 R U 11 b11 R U 10 b10 R U 9 b9 R U 8 b8 R U 7 b7 R U 6 b6 R U 5 b5 R U 4 b4 R U 3 b3 R U 2 b2 R U 1 b1 R U 0 b0 R U Note The MCSI receives the most significant bit first For example if the word_size equals 11 the upper 12 bits of the RX registers contain the received data and the lower 4 bits are zeroes ...

Page 648: ... 15 b15 R W U 14 b14 R W U 13 b13 R W U 12 b12 R W U 11 b11 R W U 10 b10 R W U 9 b9 R W U 8 b8 R W U 7 b7 R W U 6 b6 R W U 5 b5 R W U 4 b4 R W U 3 b3 R W U 2 b2 R W U 1 b1 R W U 0 b0 R W U Note The MCSI transmits the most significant bit first For example if the word_size equals 11 the upper 12 bits of the TX registers are transmitted ...

Page 649: ...I1 generates level 2 interrupts for both the DSP and the MPU Only one MPU MCSI1 interrupt covers TX RX and frame error conditions software must check the MCSI1 status register to determine the interrupt source Table 9 39 MCSI1 Interrupt Mapping Incoming Interrupts Level 2 DSP Interrupt Level 2 MPU Interrupt MCSI1 TX interrupt IRQ_06 IRQ_16 MCSI1 RX interrupt IRQ_07 IRQ_16 MCSI1 Frame Error IRQ_10 ...

Page 650: ...N txd_z Rxd Reset MPU Interrupts DMA requests I F 16 RX DMA_REQ_2 TX DMA_REQ_1 RX interrupt IRQ_7 TX interrupt IRQ_6 DSP public Peripheral bus DSPPER_nRST DSPXOR_CK TX RX frame error RX DMA_REQ_2 TX DMA_REQ_1 DSP DMA DSP level 2 interrupt handler System DMA MPU level 2 interrupt handler DSP peripheral bridge Clock generation and management Power on reset Frame error IRQ_10 Interrupt IRQ_16 ...

Page 651: ...r both the DSP and the MPU Only one MPU MCSI2 interrupt covers TX RX and frame error conditions software must check the MCSI2 status register to determine the interrupt source Table 9 42 MCSI2 Interrupt Mapping Incoming Interrupts Level 2 DSP Interrupt Level 2 MPU Interrupt MCSI2 TX interrupt IRQ_08 IRQ_17 MCSI2 RX interrupt IRQ_09 IRQ_17 MCSI2 Frame Error IRQ_11 IRQ_17 9 7 3 MCSI2 DMA Request Map...

Page 652: ...MCSI2 DOUT MCSI2 DIN txd_z Rxd Reset MPU Interrupts DMA requests I F 16 RX DMA_REQ_4 TX DMA_REQ_3 RX interrupt IRQ_9 TX interrupt IRQ_8 DSP public peripheral bus DSPPER_nRST DSPXOR_CK TX RX frame error DSP DMA DSP level 2 interrupt handler MPU level2 interrupt handler DSP peripheral bridge Clock generation and management Power on reset interrupt IRQ_16 Frame error IRQ_10 ...

Page 653: ...tes DRR2 15 0 Data receive register 2 0x00 DRR1 15 0 Data receive register 1 0x02 DXR2 15 0 Data transmit register 2 0x04 DXR1 15 0 Data transmit register 1 0x06 SPCR2 15 0 Serial port control register 2 0x08 SPCR1 15 0 Serial port control register 1 0x0A RCR2 15 0 Receive control register 2 0x0C RCR1 15 0 Receive control register 1 0x0E XCR2 15 0 Transmit control register 2 0x10 XCR1 15 0 Transmi...

Page 654: ...ster partition E 0x2E RCERF 15 0 Receive channel enable register partition F 0x30 XCERE 15 0 Transmit channel enable register partition E 0x32 XCERF 15 0 Transmit channel enable register partition F 0x34 RCERG 15 0 Receive channel enable register partition G 0x36 RCERH 15 0 Receive channel enable register partition H 0x38 XCERG 15 0 Transmit channel enable register partition G 0x3A XCERH 15 0 Tran...

Page 655: ... TX8 0x50 RX12 0x78 TX7 0x4E RX11 0x76 TX6 0x4C RX10 0x74 TX5 0x4A RX9 0x72 TX4 0x48 RX8 0x70 TX3 0x46 RX7 0x6E TX2 0x44 RX6 0x6C TX1 0x42 RX5 0x6A TX0 0x40 RX4 0x68 Unused 0x3F RX3 0x66 RX2 0x64 Unused 0x0E RX1 0x62 Status 0x0C RX0 0x60 Clock frequency 0x0A TX15 0x5E Over clock 0x08 TX14 0x5C Channel used 0x06 TX13 0x5A Interrupts 0x04 TX12 0x58 Main parameters 0x02 TX11 0x56 Control 0x00 ...

Page 656: ...chapter describes the MPU DSP shared peripherals for the OMAP5910 multimedia processor Topic Page 10 1 Introduction 10 2 10 2 Interprocessor Communication 10 3 10 3 General Purpose I O 10 7 10 4 UART1 UART2 and UART3 IrDA 10 11 Chapter 10 ...

Page 657: ...ePeripherals bus DSP public shared pheripheral bus 32 MPU public 16 DSP DSP public peripherals McBSP1 McBSP3 MPU public peripherals USB Host I F JTAG emulation I F OSC 12 MHz Clock OSC OMAP5910 ETM9 Timers 3 MPU DSP shared peripherals Mailbox MPU private peripherals Timers 3 16 Memory interface Reset External clock MPU Bus 32 kHz 1 5M bits traffic controller TC Watchdog timer Level 1 2 interrupt h...

Page 658: ...writing to the command word processor an interrupt is generated to the other processor and the 1 bit flag register is set Use of the data word is option al and at the discretion of the software but the data word must always be writ ten before the command field The ARM2DSP1 and ARMDSP2 interrupts are registered as INT5 and INT19 respectively in the DSP The DSP2ARM1 and DSP2ARM2 interrupts are mappe...

Page 659: ... for the other processor at this point the associated word command for the other processor should not have been set yet 4 The interrupting processor writes to the mailbox command word a prede fined command predefined and understood by both processors This write issues the interrupt to the other processor 5 In response to the interrupt the interrupted processor acknowledges the interrupt by reading...

Page 660: ...register the interrupt and the ARM2DSP2_Flag are cleared This register must always be written or read after ARM2DSP2 Can be written only by the MPU 0x28 0000 15 0 DSP2ARM1 Writing to this location stores a software defined data value to be used in conjunction with the DSP2ARM1 interrupt Can be written only by the DSP 0x08 0000 15 0 DSP2ARM1b Writing to this location stores a software defined comma...

Page 661: ...ad of ARM2DSP1b This bit can only be read by the MPU 15 1 DSP2MPU1_Flag Reserved 0x1C xxxx 0 Flag indicating that the DSP2ARM1 interrupt has been generated Set by DSP write to DSP2ARM1b cleared by MPU read of DSP2ARM1b This bit can only be read by the DSP 15 1 DSP2MPU2_Flag Reserved 0x20 xxxx 0 Flag indicating that the DSP2ARM2 interrupt has been generated Set by DSP write to DSP2ARM2b cleared by ...

Page 662: ... this register is shown as the configura tion and control register This register is read write from the MPU but read only from the DSP The MPU is responsible for writing to this register to assign any necessary GPIO signals to the DSP By default all GPIO are assigned to the MPU GPIO interrupts are routed to both the MPU and DSP interrupt handlers but a GPIO can only signal an interrupt to the proc...

Page 663: ...bus I F MPU TI peripheral bus I F Table 10 2 GPIO Port Registers Name R W Size Offset Description DATA_INPUT_REG R 16 bits 0x00 Data input register DATA_OUTPUT_REG R W 16 bits 0x04 Data output register DIRECTION_CONTROL_REG R W 16 bits 0x08 Direction control register INTERRUPT_CONTROL_REG R W 16 bits 0x0C Interrupt control register INTERRUPT_MASK_REG R W 16 bits 0x10 Interrupt mask register INTERR...

Page 664: ...gh Table 10 8 both the MPU and the DSP have read write access to only the bits they control within a regis ter bits associated with GPIO they control The MPU DSP can write values to the bits not controlled by the MPU DSP but the written value is not valid and does not affect the configuration of the associated GPIO Table 10 3 Data Input Register DATA_INPUT_REG Bit Function Access R W Reset Value 1...

Page 665: ...cess R W Reset Value 15 0 0 Enables interrupt R W 0xFFFF 1 Disables interrupt The interrupt status register is used to determine which of the input pins requested an interrupt Bit 0 corresponds to GPIO0 and so forth If the value is a 1 then that pin is requesting the interrupt The processor services the inter rupt and resets the appropriate bit in the status register If the user wants to reset the...

Page 666: ...GPIO pin R W 0xFFFF 1 MPU GPIO pin The pin control status register is only in the DSP This is a read only register The status register allows the DSP to find out how the MPU has configured the top level GPIO pins Table 10 10 DSP GPIO Pin Control Status Register PIN_CONTROL_STATUS_REG Bit Value Function Access R W Reset Value 15 0 0 DSP GPIO pin R 0xFFFF 1 MPU GPIO pin 10 4 UART1 UART2 and UART3 Ir...

Page 667: ...1 Module Overview 11 2 11 2 Display Specifications 11 7 11 3 LCD Controller Operation 11 9 11 4 Lookup Palette 11 14 11 5 Color Grayscale Dithering 11 15 11 6 Output FIFO 11 16 11 7 LCD Controller Pins 11 17 11 8 LCD Controller Registers 11 23 11 9 Interface to LCD Panel Signal Reset Values 11 49 Chapter 11 ...

Page 668: ...lock where each horizontal line of pixels is mapped to a set of consecutive bytes of words in the frame memory Frame sizes and frame rates supported in specific applications depend upon the available memory bandwidth allowed by the application Figure 11 1 shows the OMAP5910 device with the LCD controller highlighted Figure 11 2 shows the LCD controller in more detail The principal features of the ...

Page 669: ...ic 16 DSP DSP public peripherals McBSP1 McBSP3 MPU public peripherals USB Host I F JTAG emulation I F OSC 12 MHz Clock OSC OMAP5910 ETM9 Timers 3 MPU DSP shared peripherals Mailbox MPU private peripherals Timers 3 16 Memory interface Reset External clock MPU Bus 32 kHz 1 5M bits traffic controller TC Watchdog timer Level 1 2 interrupt handlers Configuration registers Clock and reset management Wat...

Page 670: ...ta that bypasses the palettes The data is then processed according to the desired type of display For passive monochrome panels the 4 bit value indexed from the palette is passed to the patented dither logic where the desired brightness is created using spatial and temporal dithering The pixels are passed to the panel via a 4 wire interface 4 pixels in parallel per pixel clock For passive color pa...

Page 671: ... monitor The LCD line clock pin functions as a horizontal synchronization HSYNC signal and the frame clock pin functions as a vertical synchronization VSYNC signal The pixel clock frequency is derived from the clock provided to the LCD controller LCD_CK from the OMAP5910 clock management logic and is programmable from LCD_CK 2 to LCD_CK 255 see Chapter 15 Clock Generation and System Reset Manageme...

Page 672: ...s available on the data lines In active mode the pixel clock transitions continuously and the ac bias pin is used as an output enable to signal when data is available on the LCD pins LCD HS Out LCD panel display Line clock used by the LCD display to signal the end of a line of pixels that transfers line data from the shift register to the screen and to increment the line pointer s Also used by TFT...

Page 673: ... possible colors 8 BPP 256 palette entries from 3375 possible colors 12 BPP 3375 possible on screen colors 16 BPP 3375 possible on screen colors Active 2 BPP 4BPP 8BPP 12 BPP and 16BPP 2 BPP Four palette entries selecting from 4096 colors 4 BPP 16 palette entries selecting from 4096 colors 8 BPP 256 palette entries selecting from 4096 colors 12 BPP Maximum 64K colors 16 BPP Maximum 64K colors depe...

Page 674: ... To satisfy the system requirement the following equation must be met NJ256 15 FDD Nj NJǒHBP HFP PPL 1 d HSW 3Ǔ VSW PCDNj d Display 1 TFT 2 2 3 STN color 4 Mono 4 bits Note If the condition is not true the LCD controller displays a black screen every other frame Pixels per line PPL must be in multiples of 16 Most LCD panels ignore data at the end of the line that is not needed that is they ignore data...

Page 675: ...g with the pins that interface to the LCD display 11 3 1 Frame Buffer The frame buffer is an area within on chip SRAM or off chip memory that is used to supply enough encoded pixel values to fill the entire screen one time The first 32 bytes of the buffer for 2 4 12 and 16 bit mode operation 512 bytes for 8 BPP mode of operation are used to store the look up palette data for each frame Not all of ...

Page 676: ... BPP is only contained within the first palette entry palette entry0 256 Entry Palette Buffer Bit 15 0 Base 0x0 Palette entry 0 Base 0x2 Palette entry 1 Base 0x1FC Palette entry 254 Base 0x1FE Palette entry 255 Base 0x200 Start of pixel data Figure 11 4 16 Palette Entry Buffer Format 1 2 4 12 16 BPP 16 Entry Palette Buffer Bit 15 0 Base 0x0 Palette entry 0 Base 0x2 Palette entry 1 Base 0x1C Palett...

Page 677: ...pply 16 bit values directly to the output FIFOs when active mode is enabled Table 11 2 shows the encoding of the BPP bit field Table 11 2 Bits Per Pixel Encoding for Palette Entry 0 Buffer Bit Name Value Description 14 12 BPP Bits per pixel 001 2 bits per pixel 010 4 bits per pixel 011 8 bits per pixel 1xx 12 bits per pixel and 16 bits per pixel Note Four 2 bit pixels and two 4 bit pixels are pack...

Page 678: ...Base 1 P4 P5 P6 P7 Base 2 P8 P9 P10 P11 Base 3 P12 P13 P14 P15 w w w Figure 11 6 4 BPP Frame Buffer Memory Organization Frame Buffer Byte Address 7 0 Base P0 P1 Base 1 P2 P3 Base 2 P4 P5 Base 3 P6 P7 w w w Figure 11 7 8 BPP Frame Buffer Memory Organization Frame Buffer Byte Address 7 0 Base P0 Base 1 P1 Base 2 P2 Base 3 P3 w w w ...

Page 679: ...ase 1 P0 15 8 Base 2 P1 7 0 Base 3 P1 15 8 The OMAP5910 MPU operates in little endian mode and the number and posi tion of pixels in an access depend on access type byte half word or word For example if the LCD controller is in 2 BPP mode and the MPU performs a read at the beginning of the frame buffer the result of the read is Byte access 8 bit read P0 P1 P2 P3 Half word access 16 bit read P4 P5 ...

Page 680: ...BufferSize 512 Lines Columns For 12ń16 bitsńpixel FrameBufferSize 32 2 Lines Columns 11 4 Lookup Palette The encoded pixel data from the input FIFO is used as an address to index and select individual palette locations 2 bit pixels address four locations 4 bit pixels address sixteen locations and 8 bit pixels select any of the 256 palette entries When a palette entry is selected by the encoded pix...

Page 681: ...ts calculations to give the screen image a smooth appearance The proprietary dither algorithm is opti mized to provide a range of intensity values that match the visual perception of color gray gradations In color mode three separate dither blocks are used to process the three color components red green and blue The duty cycle and resultant intensity level for all 15 color grayscale levels is summ...

Page 682: ...hifter can be configured to be 4 or 8 bits wide Single panel monochrome screens use either four or eight data lines single panel color screens use eight data pins Once the correct number of pixels has been placed within the shifter 4 8 or 2 2 3 pixel values the value is transferred to the top of the output FIFO The value is then transferred down until it reaches the last empty location within the ...

Page 683: ...in by programming the number of line clock transitions between each toggle When active display mode is enabled the timing of the pixel line and frame clocks and the ac bias pin change The pixel clock transitions continuously in this mode for as long as the LCD is enabled The ac bias pin functions as an output enable When it is asserted the display can use it to latch data from the LCD pins using t...

Page 684: ...P and 8 BPP 256 color palette as well as direct graphics depths of 12 BPP and 16 BPP For passive color displays eight signals are supplied Each signal represents one color channel of one pixel that is dithered over successive frames to achieve a maximum of 15 shade levels per color for a total of 15x15x15 3375 colors This means that each set of eight signals represents 2 2 3 pixels 8 signals 3 col...

Page 685: ...uration is constant for all modes Connecting these signals to the appropriate input signals of the panel allows support of a color TFT panel of any color depth Table 11 6 to Table 11 9 illustrate the relationship of these signals to the most common panel types Note The actual number of colors displayed is limited to the smaller of 2output depth and 2panel input pins Connecting a 12 bit panel for 1...

Page 686: ...to the 15 bits required by the panel see Table 11 7 Table 11 7 16 Bit or Per Pixel and 15 Bit Panel OMAP5910 LCD Controller Output 12 Bit TFT Panel Input LCD P 15 red 4 red 4 LCD P 14 red 3 red 3 LCD P 13 red 2 red 2 LCD P 12 red 1 red 1 LCD P 11 red 0 red 0 LCD P 10 green 5 green 4 LCD P 9 green 4 green 3 LCD P 8 green 3 green 2 LCD P 7 green 2 green 1 LCD P 6 green 1 green 0 LCD P 5 green 0 n c ...

Page 687: ...lor error see Table 11 8 Table 11 8 16 Bit Per Pixel and 18 Bit Panel OMAP5910 LCD Controller Output 18 Bit TFT Panel Input LCD P 15 red 4 red 5 LCD P 14 red 3 red 4 LCD P 13 red 2 red 3 LCD P 12 red 1 red 2 LCD P 11 red 0 red 1 LCD P 15 red 4 red 0 LCD P 10 green 5 green 5 LCD P 9 green 4 green 4 LCD P 8 green 3 green 3 LCD P 7 green 2 green 2 LCD P 6 green 1 green 1 LCD P 5 green 0 green 0 LCD P...

Page 688: ...910 LCD Controller Output 24 Bit TFT Panel Input LCD P 15 red 4 red 7 LCD P 14 red 3 red 6 LCD P 13 red 2 red 5 LCD P 12 red 1 red 4 LCD P 11 red 0 red 3 LCD P 15 red 4 red 2 LCD P 14 red 3 red 1 LCD P 13 red 2 red 0 LCD P 10 green 5 green 7 LCD P 9 green 4 green 6 LCD P 8 green 3 green 5 LCD P 7 green 2 green 4 LCD P 6 green 1 green 3 LCD P 5 green 0 green 2 LCD P 10 green 5 green 1 LCD P 9 green...

Page 689: ...minimum delay between each LCD palette request to ensure enough bus bandwidth is given to other systems access This field is only used for palette load The status register contains bits that signal FIFO underrun error Frame synchronization error When the last active frame has completed after the LCD is disabled maskable ac counter if programmed Each of these hardware detected events signals an int...

Page 690: ...put pixel data for 1 2 4 and 8 BPP are converted to 5 6 5 format using pins 15 0 R3 R2 R1 R0 R3 G3 G2 G1 G0 G3 G2 B3 B2 B1 B0 B3 22 LCDCB1 LCD control bit 1 See Table 11 16 for proper settings for this field 0 21 20 PLM Palette loading mode Must precede data loading only mode 0 00 Palette and data loading reset value 01 Palette loading 10 Data loading 19 12 FDD FIFO DMA request delay Encoded value...

Page 691: ...ata from the frame buffer to the output bus LCD P 16 0 See Table 11 16 for proper settings for this field 0 7 LCDTFT LCD TFT 0 0 Passive or STN display operation enabled dither logic is enabled 1 Active or TFT display operation enabled external palette and DAC required dither logic bypassed pin timing changes to support continuous pixel clock output enable VSYNC HSYNC signals 5 6 Reserved 0 4 Load...

Page 692: ...sive color 16 BPP 0x01000000 0x4XXX Active color 2 BPP 0x00C00080 0x1XXX Active color 4 BPP 0x00C00080 0x2XXX Active color 8 BPP 0x00800080 0x3XXX Active color 12 BPP 0x00800080 0x4XXX Active color 16 BPP 0x00000080 0x4XXX Bits Per Pixel STN Mode 5 6 5 STN The 16 BPP STN mode is handled similarly to the 12 BPP mode The differ ences are in how the pixel data is organized in the frame buffer and in ...

Page 693: ...STN resolution is equal to the 12 bit STN resolution 3375 colors NOTE Red bit 11 Green bits 6 5 Blue bit 0 Dither Logic Bits 15 14 13 12 10 9 8 7 4 3 2 1 11 0 6 5 1 4 1 4 1 The 12 BPP 5 6 5 mode can be used if the operating system does not support 12 BPP in the frame buffer Data is arranged in 16 BPP instead but only 12 bits are dithered and sent to the display 16 Bits Per Pixel STN Mode The 16 bi...

Page 694: ...1 B0 B3 When this bit is set to 0 default the four red bits the four green bits and the four blue bits are right aligned on LCD P 11 0 pins The upper LCD P 15 12 are set to 0 LCD Control Bit 1 The LCD control bit 1 is used along with LCD control bit 0 to control the mapping of pixel data from the frame buffer to the output bus LCD P 15 0 Table 11 16 shows the appropriate settings for this bit Tabl...

Page 695: ...d and is used to select an entry from the palette for 1 2 4 and 8 bits per pixel modes just as for passive mode see Figure 11 11 Figure 11 11 Passive Mode Pixel Clock and Data Pin Timing Data Pins Change LCD PCLK LCD P 3 0 LCD HS LCD VS Pixel 0 through 3 Pixel 4 through 7 Pixel 8 through 11 Pixel 12 through 15 Data Pins Samples by the Display LCDTFT 0 M8B 0 IPC 0 The value read from the palette ho...

Page 696: ...B dithering Increasing the size of the pixel representation allows a total of 64K colors to be addressed using an off chip palette that is used in conjunction with the LCD controller LCD Monochrome LCDBW The color monochrome select LCDBW bit is used to determine whether the LCD controller operates in color or monochrome mode When LCDBW 0 Color mode is selected Palette entries are 12 bits wide 4 bi...

Page 697: ... Completion of the current frame is signaled by the DMA when it sets the frame done bit Done within the LCD status register which generates an interrupt request Table 11 18 shows the location of all seven bit fields located in the LCD control register LCDControl LCDEN is the only control bit that is reset to a known state ensuring that the LCD is disabled after a reset of the LCD controller The us...

Page 698: ... value from 1 256 used to specify number of pixel clock periods to add to the end of a line transmission before line clock is asserted program to value minus one The pixel clock is held in its inactive state during the end of line wait period in passive display mode and is permitted to transition in active display mode x 15 10 HSW Horizontal synchronization pulse width Encoded value from 1 64 used...

Page 699: ... the middle of a frame not at the beginning or end where VSYNC also occurs See Section 11 8 3 LCD Timing 1 Register for information on VSYNC timing In Figure 11 14 the dashed lines on LCD PCLK indicate that the signal is not actively toggling LCD PCLK is inactive at end of line mode Virtual clocks are shown to demonstrate the behavior of the HFP HSW and HBP bit fields in the timing 0 register Hori...

Page 700: ...ode End of Line Timing HFP 0 LCD PCLK LCD HS LCD P HSW 0 HBP 1 LCD AC First Data New Row Last Data in Row Figure 11 14 Passive Mode End of Line Timing HFP 1 LCD HS LCD P LCD PCLK HSW 0 HBP 1 Internal Clock Last pixel data line n First pixel data line n 1 ...

Page 701: ...nerate a line clock pulse width ranging from 1 64 pixel clock periods program to value required minus one Note The pixel clock does not transition during the line clock pulse in passive dis play mode but transitions in active display mode Also the polarity active and inactive state of the line clock is programmed using the invert HSYNC IHS bit in LCDTiming2 Pixels Per Line PPL The pixels per line ...

Page 702: ...transitions during the insertion of the extra line clock periods 0 23 16 VFP Vertical front porch Value 0 255 used to specify number of line clock periods to add to the end of each frame The line clock transitions during the insertion of the extra line clock periods 0 15 10 VSW Vertical synchronization pulse width In active mode LCDTFT 1 encoded value 1 64 used to specify number of line clock peri...

Page 703: ...egister 1 control fields for active and passive displays respectively Vertical Front Porch VFP The 8 bit vertical front porch VFP field is used to specify the number of hori zontal synchronizations line clocks to insert at the end of each frame Once a complete frame of pixels is transmitted to the LCD display the value in VFP is used to count the number of horizontal synchronization periods to wai...

Page 704: ...alue in VSW is transferred to a 6 bit down counter that uses the line clock frequency to decrement When the counter reaches zero LCD VS is negated VSW can be programmed to generate a vertical synchronization pulse width ranging from 1 64 line clock periods program to value required minus one In passive mode LCDTFT 0 VSW does not affect the timing of the LCD VS pin but instead can be used to add ex...

Page 705: ...ising edge of the first pixel clock for each frame The frame clock remains asserted for the remainder of the first line as pixels are output to the display and during the assertion of the first line clock for the frame and are then negated on the rising edge of the first pixel clock of the second line of each frame Lines Per Panel LPP The lines per panel LPP bit field is used to specify the number...

Page 706: ...rol on off on only when in TFT mode off by default 0 0 LCD HS and LCD VS are driven on the opposite edges of the pixel clock than the lcd_data 1 LCD HS and LCD VS are driven according to bit 24 24 PHSVS RF Program HSYNC VSYNC rise and fall 0 0 LCD HS and LCD VS are driven on the falling edge of the pixel clock bit 25 is set to 1 1 LCD HS and LCD VS are driven on the rising edge of the pixel clock ...

Page 707: ...frame 19 16 ACBI ac bias line transitions per interrupt Value 0 255 used to specify the number of ac bias pin transitions to count before setting the line count status LCS bit signaling an interrupt request Counter is frozen when LCS is set and is restarted when LCS is cleared by software This function is disabled when ACBI 0x0000 0 15 8 ACB ac bias pin frequency Value 0 255 used to specify number...

Page 708: ...l data is driven on the rising edge of pixel clock However if the invert pixel clock IPC bit is set to 1 then the HSYNC and VSYNC signals are driven on the rising edge of the pixel clock and pixel data is driven on the falling edge By setting the PHSVS_RISE_FALL bit and enab ling it PHSVS_ON_OFF 1 you can control on which edge the signals are driven The waveforms in Figure 11 17 show PHSVS_ON_OFF ...

Page 709: ...hich signals an interrupt request After the LCD controller is enabled the value in ACBI is loaded to a 4 bit down counter and the counter decrements each time the ac bias line state is inverted When the counter reaches zero it stops and the ac bias count ABC bit is set in the status register When ABC is set the 4 bit down counter is reloaded with the value in ACBI and is disabled until ABC is clea...

Page 710: ...n output enable signal The ac bias is asserted by the LCD control ler in active mode this occurs whenever pixel data is driven out to the data pins to signal to the display when it can latch pixels using the pixel clock Pixel Clock Divider PCD The 8 bit pixel clock divider PCD field is used to select the frequency of the pixel clock see Table 11 21 PCD can generate a range of pixel clock frequenci...

Page 711: ... Number of Signals Minimum Pixel Clock Divider Active 16 1 pixel clock 2 Monochrome 4 4 pixels clock 4 Passive color 8 2 2 3 pixels clock 3 11 8 5 LCD Status Register LcdStatus The LCD controller status register LCSR contains bits that signal overrun and underrun errors for the input and output FIFOs and the ac bias pin transi tion count LCD disabled DMA base update ready and DMA transfer bus erro...

Page 712: ...ion counter has decremented to zero indicating that the LCD AC line has transitioned the number of times specified by the ACBI control bit field Counter is reloaded with value in ACBI but is disabled until the user clears ABC 2 Sync Synchronization lost read only Cleared by setting LCDEN to 0 which also resets the input FIFO in the DMA controller 0 0 Normal 1 Frame synchronization lost has occurre...

Page 713: ...r panel threshold This field defines the number of lines to be refreshed 1 1024 Program to value minus 1 0 15 0 DPD Default pixel data DPD defines the default value of the pixel data sent to the panel for the lines until LPPT is reached or after passing the LPPT 0 The ability to display only the first or last n lines of the panel and send a fixed contents for the other lines is supported with the ...

Page 714: ...CD Controller Registers 11 48 Figure 11 19 LCD Subpanel Display Register LcdSubpanel Line N Threshold PANEL Line 0 Line N Line 0 Threshold Line N Line n 1 SPEN 1 HOLS 0 Line 0 Line N SPEN 1 HOLS 1 LPPT n ...

Page 715: ...y disabling the LCD setting LCDEN bit to low The default value depends solely upon the signal polarity control as defined in the LCD timing 2 register except for LCD P 15 0 when driven low and LCD AC which does not change status when in STN mode Table 11 24 LCD Panel Signals Reset Values LCD P 0 15 0 LCD PCLK LCD HS LCD VS LCD AC Reset LCD_RESET_I 0 0 0 0 0 0 Disable LCDEN 0 0 0 IPC 0 1 IPC 1 0 HI...

Page 716: ...Control and Status Registers 12 17 12 4 UART Autobaud Modes of Operation 12 37 12 5 UART Autobaud Functional Description 12 38 12 6 UART Autobaud Configuration Example 12 50 12 7 UART IrDA Control and Status Registers 12 52 12 8 UART IrDA Modes of Operation 12 83 12 9 UART IrDA Functional Description 12 88 12 10 UART IrDA Configuration Example 12 101 12 11 UART Software Reset 12 101 12 12 UART FIF...

Page 717: ...atePeripherals bus DSP public shared pheripheral bus 32 MPU public 16 DSP DSP public peripherals McBSP1 McBSP3 MPU public peripherals USB Host I F JTAG emulation I F OSC 12 MHz Clock OSC OMAP5910 ETM9 Timers 3 MPU DSP shared peripherals Mailbox MPU private peripherals Timers 3 16 Memory interface Reset External clock MPU Bus 32 kHz 1 5M bits traffic controller TC Watchdog timer Level 1 2 interrupt...

Page 718: ...ropriate baud rates An interrupt request to the system if there are multiple DMA requests 12 1 1 1 UART Modem Functions UART1 2 3 Baud rate from 300 bits s up to 1 5M bits s Autobaud between 1200 bits s and 115 2K bits s Software hardware flow control J Programmable XON XOFF characters J Programmable AUTO_RTS and AUTO_CTS Programmable serial interface characteristics J 5 6 7 or 8 bit characters J ...

Page 719: ...ith selectable trigger levels available to monitor frame length and frame errors Table 12 1 describes the I O module at the module level 12 1 1 3 UART Signals The signals available on the UART modules are illustrated in Figure 12 2 These signals are described in Table 12 1 Figure 12 2 UART Signals UART RX TX CTS RTS DSR DTR TXIR SD_MODE RXIR These signals are only available on UART3 ...

Page 720: ...ve data Setting modem control register bit 1 activates RTS It becomes inactive as a result of a module reset loop back mode or by clearing the MCR1 In automatic RTS mode it becomes inactive as a result of the receiver threshold logic 1 DSR I Data set ready Active low modem status signal Reading bit 5 of the modem status register checks the condition of DSR Reading bit 1 of that register checks a c...

Page 721: ...TR Data transmit ready output UART1 DTR DSR Data set ready input UART1 DSR The functional clock is either a 12 MHz or a 48 MHz clock You can select the clock with the CONF_MOD_UART1_CLK_MODE_R bit 29 of the MOD_CONF_CTRL_0 register see Section 6 8 OMAP5910 Configuration Registers as follows CONF_MOD_UART1_CLK_MODE_R 0 12 MHz default CONF_MOD_UART1_CLK_MODE_R 1 48 MHz NDMA_REQ 1 0 are connected to ...

Page 722: ...T NIRQ NDMAREQ UART1 RX UART1 CTS UART1 RTS DMA request 1 0 2 Input clock TI peripheral bus ULPD Uart1_dpll_clk 12 MHz 48 MHz 1 0 TIPB switch P_CLK P_NBRST CLKIN_DSP CLKIN_MPU NRESET P_NIRQ P_NDMAREQ DSP PER_CLK 12 MHz MPU PER_CLK 12 MHz PER RESET IRQ 14 MPU interrupt level2 IRQ 5 DSP interrupt level2 DMA 13 12 DSP DMA DMA 13 12 MPU system DMA public rx tx UART1 DTR UART1 DSR 1 0 UART1 TX ...

Page 723: ...t the clock with the CONF_MOD_UART2_CLK_MODE_R bit 30 of the MOD_CONF_CTRL_0 register see Section 6 8 OMAP5910 Configuration Registers as follows CONF_MOD_UART1_CLK_MODE_R 0 32 kHz 12 MHz default CONF_MOD_UART1_CLK_MODE_R 1 48 MHz The frequency of the 32 kHz 12 MHz clock depends on the OMAP5910 system state 32 kHz in deep sleep modes 12 MHz in big sleep and awake mode Note that the UPLD clock cont...

Page 724: ... and 100 Figure 12 4 shows the sequence of the wakeup by UART2 RX Figure 12 4 UART2 RX Wakeup Sequence 12 MHz Start UART2 clock UART2 BDCLK UART2 RX t 1 t 2 t 3 t 4 Bit1 Bit0 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Stop 32 768 kHz 12 MHz 12 N MHz 32 768 N kHz 12 N MHz T 1 The MPU goes to standby and enters Deep Sleep state The 12MHz osc is turned off The Baud clock automatically switches to 32 768 N N Uart ...

Page 725: ...line IRQ 15 of the MPU level 2 interrupt handler Interrupt line IRQ 4 of the DSP level 2 interrupt handler Figure 12 5 shows the UART2 environment Figure 12 5 UART2 Environment MPU TIPB public DSP TIPB public Interrupt to MPU Interrupt to DSP OMAP5910 TX2 UART2 FCLK NRESET NIRQ NDMAREQ 1 0 RX2 CTS2 RTS2 DMA request 1 0 rx tx 2 Input clock TI peripheral bus ULPD Uart1_dpll_clk Uart_mcko 32 kHz 12 M...

Page 726: ...ECT 1 Table 12 4 Available UART3 Signals in IrDA 1 Mode Generic UART Signal Name Description UART1 Signal Name TXIR IrDA serial data input TX3 RXIR IrDA serial data output UART3 RX RX Serial data input High SD_MODE Signal used to configure transceivers RTS3 Table 12 5 lists the UART3 IrDA signals accessible at the OMAP5910 level when IRDA_SELECT 0 Table 12 5 Available UART3 Signals in IrDA 0 Mode ...

Page 727: ...2 is connected to The interrupt line IRQ 15 of the MPU level 1 interrupt handler The interrupt line IRQ 10 of the DSP level 1 interrupt handler Figure 12 6 shows the UART3 environment Figure 12 6 UART3 Environment MPU TIPB public DSP TIPB public Interrupt to MPU Interrupt to DSP OMAP5910 UART3 FCLK IRDA_SELECT NRESET NIRQ NDMAREQ DMA request 1 0 rx tx 2 Input clock TI peripheral bus ULPD Uart1_dpl...

Page 728: ...e DSP accessible registers are listed in Table 12 9 Table 12 10 and Table 12 11 describe the register bits Table 12 6 MPU Registers UART Register Description R W Bits Address UART1 RHSW_ARM_CNF TIPB switch configuration R W 16 FFFB C800 UART1 RHSW_ARM_STA TIPB switch status R 16 FFFB C804 UART2 RHSW_ARM_CNF TIPB switch configuration R W 16 FFFB C840 UART2 RHSW_ARM_STA TIPB switch status R 16 FFFB ...

Page 729: ...ending error 0 RHSW_ERR_NIRQ 0 Clears IRQ line and all others status bits of register R W 1 1 Normal operation Table 12 9 DSP Registers UART Register Description R W Bits Address UART1 RHSW_DSP_CNF TIPB switch control R W 16 001 C800 UART1 RHSW_DSP_STA TIPB switch status R 16 001 C802 UART2 RHSW_DSP_CNF TIPB switch control R W 16 001 C820 UART2 RHSW_DSP_STA TIPB switch status R 16 001 C822 UART3 R...

Page 730: ...LOCK 0 No lock R 1 1 MPU bus is allocated Table 12 11 TIPB Switch Status DSP Register RHSW_DSP_STA Bit Name Value Function R W Reset Value 15 4 Reserved 3 RHSW_BOTH_LCK_ERR 0 Normal operation R 0 1 Lock error 2 RHSW_ITPEND_ERR 0 Normal operation R 0 1 DMA request error 1 RHSW_DMAREQ_ERR 0 Normal operation R 0 1 IT pending error 0 RHSW_ERR_NIRQ 0 Clears IRQ line and all others status bits of regist...

Page 731: ...HSW_DSP_CNF to lock UART2 For switching UART3 to DSP 1 MPU Write 0 into the UART3 TIPB switch configuration MPU register RHSW_ARM_CNF to unlock UART3 2 DSP Write 2 into UART3 TIPB switch configuration DSP register RHSW_DSP_CNF to lock UART3 Note PERIF_LOCK Bits If either the DSP_PERIF_LOCK in the RHSW_DSP_CNF register or the ARM_PERIF_LOCK bit in the RHSW_ARM_CNF register is already set to 1 then ...

Page 732: ...m Register Program Registers MPU Byte Off DSP Byte Off LCR 7 0 LCR 7 1 LCR 7 0 0xBF LCR 7 0 0xBF Off set Off set READ WRITE READ WRITE READ WRITE 0x00 0x00 RHR THR DLL DLL DLL DLL 0x04 0x02 IER IER DLH DLH DLH DLH 0x08 0x04 IIR FCR IIR FCR EFR EFR 0x0C 0x06 LCR LCR LCR LCR LCR LCR 0x10 0x08 MCR MCR MCR MCR XON1 XON1 0x14 0x0A LSR LSR XON2 XON2 0x18 0x0C MSR TCR TCR MSR TCR TCR XOFF1 TCR XOFF1 TCR ...

Page 733: ...SC_12M_ SEL 0x50 0x28 MVR MVR MVR MCR 7 5 FCR 5 4 and IER 7 4 can only be written when EFR 4 1 Transmission control register TCR and trigger level register TLR are accessible only when EFR 4 1 and MCR 6 1 Table 12 13 lists the UART autobaud registers Table 12 14 through Table 12 41 describe specific register bits Table 12 13 UART Autobaud Registers Register Description Size Access RHR Receive hold...

Page 734: ...ch high 8 bit R W TCR Transmission control 8 bit R W TLR Trigger level 8 bit R W MDR1 Mode definition 1 8 bit R W UASR UART autobauding status 8 bit R OSC_12M_SEL 12 MHz oscillator select 8 bit R MVR Module version 8 bit R The receiver section consists of the receiver holding register RHR and the receiver shift register The RHR is actually a 64 byte FIFO The receiver shift register receives serial...

Page 735: ...olding Register THR Bit Name Function R W Reset Value 7 0 THR Transmit holding register W Undefined Table 12 16 FIFO Control Register FCR Bit Name Value Function R W Reset Value 7 6 RX_FIFO_TRIG Sets the trigger level for the RX FIFO If SCR7 0 and TLR7 4 0000 W 00 00 8 characters 01 16 characters 10 56 characters 11 60 characters If SCR7 0 and TLR7 4 0000 RX_FIFO_TRIG is not considered If SCR7 1 R...

Page 736: ...RT_nDMA_REQ0 in TX UART_nDMA_REQ1 in RX This register only has effect if SCR0 0 2 TX_FIFO_CLEAR 0 No change W 0 1 Clears the transmit FIFO and resets its counter logic to zero Returns to zero after clearing FIFO 1 RX_FIFO_CLEAR 0 No change W 0 1 Clears the receive FIFO and resets its counter logic to zero Returns to zero after clearing FIFO 0 FIFO_EN 0 Disables the transmit and receive FIFOs W 0 1...

Page 737: ...ling edge of pins RX CTS or DSR to generate an interrupt 3 TX_EMPTY_CTL_IT 0 Normal mode for THR interrupt see Table 12 23 R W 0 1 The THR interrupt is generated when TX FIFO and TX shift register are empty 2 1 DMA_MODE_2 Used to specify the DMA mode valid if SCR0 1 R W 00 00 DMA mode 0 no DMA 01 DMA mode 1 UART_nDMA_REQ0 in TX UART_nDMA_REQ1 in RX 10 DMA mode 2 UART_nDMA_REQ0 in RX 11 DMA mode 3 ...

Page 738: ...mat if LCR3 1 If LCR5 1 and LCR4 0 the parity bit is forced to 1 in the transmitted and received data If LCR5 1 and LCR4 1 the parity bit is forced to 0 in the transmitted and received data R W 0 4 PARITY_TYPE1 0 Odd parity is generated if bit 3 1 R W 0 1 Even parity is generated if bit 3 1 3 PARITY_EN 0 No parity R W 0 1 A parity bit is generated during transmission and the receiver checks for re...

Page 739: ...alue 7 RX_FIFO_STS 0 Normal operation R 0 1 At least one parity error framing error or break indication in the receiver FIFO Bit 7 is cleared when no more errors are present in the FIFO 6 TX_SR_E 0 Transmitter hold and shift registers are not empty R 1 1 Transmitter hold and shift registers are empty 5 TX_FIFO_E 0 Transmit hold register is not empty R 1 1 Transmit hold register is empty The proces...

Page 740: ...ot transferred to the RX FIFO This case can occurs only when receive FIFO is full 0 RX_FIFO_E 0 No data in the receive FIFO R 0 1 At least one data character in the RX_FIFO When the LSR is read LSR 4 2 reflect the error bits BI FE PE of the charac ter at the top of the RX FIFO next character to be read Therefore reading the LSR and then reading the RHR identifies errors in a character Reading RHR ...

Page 741: ... emulating the modem Table 12 21 Modem Control Register MCR Bit Name Value Function R W Reset Value 7 CLKSEL 0 No action R W 0 1 Divide clock input by 4 6 TCR_TLR 0 No action R W 0 1 Enables access to the TCR and TLR registers 5 XON_EN 0 Disable XON any function R W 0 1 Enable XON any function 4 LOOPBACK_EN 0 Normal operating mode R W 0 1 Enable local loop back mode internal In this mode the MCR3 ...

Page 742: ...egister MSR provides information about the current state of the control lines from the modem data set or peripheral device to the host MPU or DSP It also indicates when a control input from the modem changes state Table 12 22 Modem Status Register MSR Bit Name Function R W Reset Value 7 6 RESERVED Reserved R Input signal 5 NDSR_STS This bit is the complement of the DSR input In loop back mode it i...

Page 743: ...he RTS interrupt R W 0 1 Enables the RTS interrupt 5 XOFF_IT 0 Disables the XOFF interrupt R W 0 1 Enables the XOFF interrupt 4 SLEEP_MODE 0 Disables sleep mode R W 0 1 Enables sleep mode stops baud rate clock when the module is inactive 3 MODEM_STS_IT 0 Disables the modem status register interrupt R W 0 1 Enables the modem status register interrupt 2 LINE_STS_IT 0 Disables the receiver line statu...

Page 744: ...R change state from active low to inactive high R 00000 0 IT_PENDING 0 An interrupt is pending nIRQ active R 1 1 No interrupt is pending nIRQ inactive The enhanced feature register EFR enables or disables enhanced features Table 12 25 Enhanced Feature Register EFR Bit Name Value Function R W Reset Value 7 AUTO_CTS_EN Automatic CTS enable bit R W 0 0 Normal operation 1 Automatic CTS flow control is...

Page 745: ...and MCR bits 5 7 1 Enables writing to IER bits 4 7 FCR bits 4 5 and MCR bits 5 7 3 0 SW_FLOW_CON TROL Combinations of software flow control can be selected by programming bit 3 bit 0 See Section 12 5 10 Software Flow Control R W 0 Table 12 26 EFR 0 3 Software Flow Control Options Bit 3 Bit 2 Bit 1 Bit 0 TX RX Software Flow Controls 0 0 X X No transmit flow control 1 0 X X Transmit XON1 XOFF1 0 1 X...

Page 746: ...R W 0x00 Table 12 29 XOFF1 Register XOFF1 Bit Name Function R W Reset Value 7 0 XOFF_WORD1 Used to store the 8 bit XOFF1 character R W 0x00 Table 12 30 XOFF2 Register XOFF2 Bit Name Function R W Reset Value 7 0 XOFF_WORD2 Used to store the 8 bit XOFF2 character R W 0x00 The scratchpad register SPR does not control the module in any way rather it is used by the programmer to hold temporary data Tab...

Page 747: ...visor Latch High Register DLH Bit Name Function R W Reset Value 7 0 CLOCK_MSB Used to store the 8 bit MSB divisor value R W 0x00 To achieve the required baud rate you must program DLL DLH with the integer part of the divisor value Choosing the appropriate divisor value UART Divisor value Operating Frequency 16 x Baud Rate Just as in autobaud mode the input frequency of the UART modem must be fixed...

Page 748: ...must ensure that TCR 3 0 TCR 7 4 whenever automatic RTS or software flow control is enabled to avoid a faulty operation of the device 3 In FIFO interrupt mode with flow control programmer must also ensure that trigger level to HALT transmission is greateror equal to receive FIFO trigger level either TLR 7 4 or FCR 7 6 otherwise FIFO operation stalls In FIFO DMA mode with flow control this issue do...

Page 749: ...ired All zeros result in unpredictable behavior Note The protocol to set the concatenation of TLR and FCR is Set SCR 6 0 Set the value of threshold into FCR and TLR Set SCR 6 1 Table 12 37 RX FIFO Trigger Level Setting Summary SCR 7 TLR 7 4 RX FIFO Trigger Level 0 0000 Defined by FCR7 6 either 8 16 56 60 characters 0 00000 Defined by TLR7 4 from 4 to 60 characters with a granularity of 4 character...

Page 750: ...by setting MODE_SELECT 0x7 but by putting the UART into sleep mode The lowest power state is achieved when in sleep mode witht DLL 0xFFFF and DLH 0xFFFF The UART autobauding status register UASR returns the speed the number of bits by characters and the type of the parity in UART autobaud mode Table 12 39 Autobauding Status Register UASR Bit Name Value Function R W Reset Value 7 6 PARITY_TYPE 00 0...

Page 751: ... This register is used to set up transmission according to characteristics of previous reception instead of LCR DLL and DLH registers when UART is in autobaud mode To reset the autobauding hardware to start a new AT detection or to set the UART in standard mode no autobaud MDR1 2 0 must be set to reset state 111 then to the UART in autobaud mode 010 or UART in standard mode 000 Table 12 40 OSC_12_...

Page 752: ...d by buffering received transmitted characters Both the receiver and transmitter FIFOs can store up to 64 bytes of data plus three additional bits of error status per byte for the receiver FIFO and have selectable trigger levels Both interrupts and DMA are available to control the data flow between the host MPU or DSP and the module 12 4 1 UART Mode The UART modem uses a wired interface for serial...

Page 753: ...bit 5 6 7 or 8 bits of data according to LCR register Parity bit see LCR register 1 or 2 stop bit according to LCR register 12 5 UART Autobaud Functional Description 12 5 1 UART Autobaud Functional Block Diagram Figure 12 8 shows the UART autobaud FSM stands for finite state machine Figure 12 8 Functional Block Diagram TIPB RX TX TX FSM TX FIFO Control TIPB interface RX FIFO Data exchanges Control...

Page 754: ...zed to six different levels When an interrupt is generated the interrupt identification register IIR indi cates a pending interrupt by bringing IIR 0 to logic 0 and it specifies the type of interrupt through IIR 5 1 Table 12 42 summarizes the interrupt control functions Table 12 42 Generic Interrupt Descriptions in Modem Mode IIR 5 0 Priority Level Interrupt Type Interrupt Source Interrupt Reset M...

Page 755: ...terrupt identification register IIR 12 5 3 2 Wake Up Interrupt The wake up interrupt is uniquely designed and is enabled when SCR 4 is set to 1 The interrupt identification register IIR is not modified when this interrupt occurs SSR 1 must be checked to detect a wake up event When wake up interrupt occurs the only way to clear it is to reset SCR 4 to 0 12 5 3 3 FIFO Interrupt Mode In FIFO interrup...

Page 756: ...ly be deasserted when the host MPU or DSP has handled enough bytes to make the FIFO level below threshold Notice that flow control threshold is set at a higher value than FIFO threshold Figure 12 10 Transmit FIFO IT Request Generation Number of spaces Programmable FIFO threshold Transmit FIFO level Zero byte time Interrupt request ti Interrupt request active low Full level In transmit mode an inte...

Page 757: ...are four modes of DMA operation DMA mode 0 DMA mode 1 DMA mode 2 and DMA mode 3 They can be selected as follows When SCR 0 0 J Setting FCR 3 to 0 enables DMA mode 0 J Setting FCR 3 to 1 enables DMA mode 1 When SCR 0 1 SCR 2 1 determine DMA mode 0 to 3 according to SCR register description So for instance If no DMA operation is desired set SCR 0 to 1 and SCR 2 1 to 00 FCR 3 is disregarded If DMA mo...

Page 758: ...l Zero byte time DMA request time DMA request active low In receive mode a DMA request is generated as soon as receive FIFO reach es its threshold This request is deasserted when the number of bytes defined by the threshold level has been read by the system DMA Figure 12 12 Transmit FIFO DMA Request Generation Programmable threshold Transmit FIFO level Zero byte time DMA request time DMA request T...

Page 759: ...rrupts Sleep mode is a good way to lower UART power consumption but this state can be achieved only when the UART is set in modem mode Therefore even if the UART does not have a functional key role it must be initialized in a func tional mode to take advantage of sleep mode In sleep mode the module clock and baud rate clock are stopped internally Since most registers are clocked using these clocks...

Page 760: ... as follows J Reset transmit FIFO if enabled J Wait for transmit shift register to become empty LSR 6 1 J Take a guard time according to stop bit definition J Set LCR 6 to 1 The break condition is asserted as long as LCR 6 is set to 1 12 5 8 Programmable Baud Rate Generator The programmable baud generator takes any clock input and divides it by a divisor between 1 and 216 1 The CLKSEL register bit...

Page 761: ... are stored in the TCR RTS is active if the RX FIFO level is below the HALT trigger level in TCR 3 0 When the receiver FIFO HALT trigger level is reached RTS is deasserted The sending device for example another UART may send an additional byte after the trigger level is reached because it may not recognize the deassertion of RTS until it has begun sending the additional byte RTS is automatically r...

Page 762: ...d characters in certain cases XOFF1 and XOFF2 must be received sequentially When the correct XOFF characters are received transmission is halted after completing transmission of the current character XOFF detection also sets IIR 4 if enabled via IER 5 and causes nIRQ to go low To resume transmission an XON1 2 character must be received in certain cases XON1 and XON2 must be received sequentially W...

Page 763: ...umed that software flow control and hardware flow control are never enabled simultaneously 12 5 11 Autobauding Mode In autobaud mode UART can extract transfer characteristics speed length and parity from an AT command These characteristics are used to receive data following an AT and to send data Here are valid AT commands AT DATA CR at DATA CR A a A line break during the acquisition of the sequen...

Page 764: ...transition 0 1 is considered as valid after a majority vote on three sampling periods 3 Compare the sampled value with a table If the sampled value is outside a valid range an error is reported no speed identified and the hardware goes back to the first state 1 4 Otherwise the first data bit in the received register for serial to parallel conversion is stored and goes to frame format identificatio...

Page 765: ...ramming stages to operate one UART module with FIFO interrupt and no DMA capabilities It is a three step procedure that ensures quick start of these modules it does not cover all UART module features and performance 1 Software reset of the module interrupts status and controls 2 FIFO configuration and enable 3 Baud rate data and stop configuration This procedure is programming language agnostic UA...

Page 766: ...R registers set EFR 4 and MCR 6 to 1 To write into FCR set EFR 4 to 1 Notice that EFR 4 1 has already been done in the software reset so a simple write to MCR 6 is necessary 2 Set TCR TLR and FCR to the desired value 3 Disable accesses to TCR TLR and FCR to avoid any further undesired write to these registers J LCR 0xBF provides EFR access J EFR 4 0 J LCR 7 0 J MCR 6 0 12 6 3 Baud Rate Data and St...

Page 767: ... DLH DLH 0x08 0x04 IIR FCR IIR FCR EFR EFR 0x0C 0x06 LCR LCR LCR LCR LCR LCR 0x10 0x08 MCR MCR MCR MCR XON1 ADDR1 XON1 ADDR1 0x14 0x0A LSR LSR XON2 ADDR2 XON2 ADDR2 0x18 0x0C MSR TCR TCR MSR TCR TCR XOFF1 TCR XOFF1 TCR 0x1C 0x0E SPR TLR SPR TLR SPR TLR SPR TLR XOFF2 TLR XOFF2 TLR 0x20 0x10 MDR1 MDR1 MDR1 MDR1 MDR1 MDR1 0x24 0x12 MDR2 MDR2 MDR2 MDR2 MDR2 MDR2 0x28 0x14 SFLSR TXFLL SFLSR TXFLL SFLSR...

Page 768: ...nly be written when EFR 4 1 In SIR mode EFR 4 has no impact on the access to IER 7 4 MCR 7 5 and FCR 5 4 can only be written when EFR 4 1 Transmission control register TCR and trigger level register TLR are accessible only when EFR 4 1 and MCR 6 1 Table 12 44 lists the UART IrDA registers Table 12 45 through Table 12 87 describe the register bits Table 12 44 UART IrDA Registers Register Descriptio...

Page 769: ...CR Transmission control 8 bits R W TLR Trigger level 8 bits R W MDR1 Mode definition 1 8 bits R W MDR2 Mode definition 2 8 bits R W TXFLL Transmit frame length low 8 bits W TXFLH Transmit frame length high 8 bits W RXFLL Received frame length low 8 bits W RXFLH Received frame length high 8 bits W SFLSR Status FIFO line status 8 bits R RESUME Resume 8 bits R SFREGL Status FIFO low 8 bits R SFREGH S...

Page 770: ...ata in the RHR is not overwritten Table 12 45 Receive Holding Register RHR Bit Name Function R W Reset Value 7 0 RHR Receive holding register R Undefined The transmitter section consists of the transmit holding register THR and the transmit shift register The THR is actually a 64 byte FIFO The host MPU or DSP writes data to the THR The data is placed into the transmit shift register where it is sh...

Page 771: ... 6 bits with granularity of 1 5 4 TX_FIFO_TRIG Sets the trigger level for the TX FIFO If SCR6 0 and TLR3 0 0000 00 8 spaces 01 16 spaces 10 32 spaces 11 56 spaces W 00 00 8 characters 01 16 characters 10 56 characters 11 60 characters If SCR6 1 TX_FIFO_TRIG is two LSBs of the trigger level 1 63 on 6 bits with granularity of 1 Notes 1 Bits 4 and 5 can only be written when EFR 4 1 2 Bits 0 to 3 can ...

Page 772: ...ounter logic to zero Returns to zero after clearing FIFO 1 RX_FIFO_CLEAR 0 No change W 0 1 Clears the receive FIFO and resets its counter logic to zero Returns to zero after clearing FIFO 0 FIFO_EN 0 Disables the transmit and receive FIFOs W 0 1 Enables the transmit and receive FIFOs Notes 1 Bits 4 and 5 can only be written when EFR 4 1 2 Bits 0 to 3 can be changed only when baud clock is not runn...

Page 773: ...ng edge of pins RX CTS or DSR to generate an interrupt 3 TX_EMPTY_CTL_IT 0 Normal mode for THR interrupt see Table 12 55 R W 0 1 The THR interrupt is generated when TX FIFO and TX shift register are empty 2 1 DMA_MODE_2 Used to specify the DMA mode valid if SCR0 1 R W 00 00 DMA mode 0 no DMA 01 DMA mode 1 UART_nDMA_REQ0 in TX UART_nDMA_REQ1 in RX 10 DMA mode 2 UART_nDMA_REQ0 in RX 11 DMA mode 3 UA...

Page 774: ...al 5 PARITY_TYPE2 Selects the forced parity format if LCR3 1 If LCR5 1 and LCR4 0 the parity bit is forced to 1 in the transmitted and received data If LCR5 1 and LCR4 1 the parity bit is forced to 0 in the transmitted and received data R W 0 4 PARITY_TYPE1 0 Odd parity is generated if bit 3 1 R W 0 1 Even parity is generated if bit 3 1 3 PARITY_EN 0 No parity R W 0 1 Parity is generated during tr...

Page 775: ...et Value 7 RX_FIFO_STS 0 Normal operation R 1 1 At least one parity error framing error or break indication in the receiver FIFO Bit is cleared when no more errors are present in FIFO 6 TX_SR_E 0 Transmitter hold and shift registers are not empty R 1 1 Transmitter hold and shift registers are empty 5 TX_FIFO_E 0 Transmit hold register is not empty R 1 1 Transmit hold register is empty The processo...

Page 776: ...er held in the receive shift register is not transferred to the RX FIFO This case can occur only when the receive FIFO is full 0 RX_FIFO_E 0 No data in the receive FIFO R 0 1 At least one data character in the RX_FIFO When the line status register LSR is read LSR 4 2 reflect the error bits BI FE PE of the character at the top of the RX FIFO next character to be read Therefore reading the LSR and t...

Page 777: ...termine the frame boundary Cleared by first reading the last received byte then reading the SIR_LSR register 4 FRAME_TOO_LONG 0 No frame too long error in frame R 0 1 Frame too long error in the frame at the top of the STATUS FIFO next character to be read This bit is set to 1 when a frame exceeding the maximum length set by RXFLH and RXFLL registers has been received When this error is detected c...

Page 778: ...ror bits FL CRC ABORT of the frame at the top of the STATUS FIFO next frame status to be read In SIR mode the LSR bits 4 2 reflect the same values as the SFLSR bits 3 1 Table 12 52 Supplementary Status Register SSR Bit Name Value Function R W Reset Value 7 2 Reserved R 000000 1 RX_CTS_DSR_WAKE _UP_STS 0 No falling edge event on RX CTS and DSR R 0 1 A falling edge occurred on RX CTS or DSR 0 TX_FIF...

Page 779: ...0 1 Enable local loopback mode internal In this mode the MCR3 0 signals are looped back into MSR7 4 The transmit output is looped back to the receive input internally 3 CD_STS_CH 0 In loopback mode forces IRQ outputs to inactive state R W 0 1 In loopback mode forces IRQ outputs to inactive state 2 RESERVED Reserved This bit should always be written as 0 R W 0 1 RTS 0 Forces RTS output to inactive ...

Page 780: ... Register MSR Bit Name Function R W Reset Value 7 6 RESERVED Reserved R 5 NDSR_STS This bit is the complement of the DSR input In loopback mode it is equivalent to MCR0 R Input signal 4 NCTS_STS This bit is the complement of the CTS input In loopback mode it is equivalent to MCR1 R Input signal 3 2 RESERVED Reserved R 0 1 DSR_STS 1 Indicates that DSR input or MCR0 in loopback has changed state Cle...

Page 781: ...ables the RTS interrupt R W 0 1 Enables the RTS interrupt 5 XOFF_IT 0 Disables the XOFF interrupt R W 0 1 Enables the XOFF interrupt 4 SLEEP_MODE 0 Disables sleep mode R W 0 1 Enables sleep mode stop baud rate clock when the module is inactive 3 MODEM_STS_IT 0 Disables the modem status register interrupt R W 0 1 Enables the modem status register interrupt 2 LINE_STS_IT 0 Disables the receiver line...

Page 782: ... received EOF interrupt 6 LINE_STS_IT 0 Disables the receiver line status interrupt R W 0 1 Enables the receiver line status interrupt 5 TX_UNDERRUN_IT 0 Disables the TX underrun interrupt R W 0 1 Enables the TX underrun interrupt 4 STS_FIFO_TRIG_IT 0 Disables status FIFO trigger level interrupt R W 0 1 Enables status FIFO trigger level interrupt 3 RX_OVERRUN_IT 0 Disables the RX overrun interrupt...

Page 783: ... R W Reset Value 7 6 FCR_MIRROR Mirror the contents of FCR 0 on both bits R 00 5 1 IT_TYPE Priority 5 4 3 2 1 Source 1 0 0 0 1 1 Receiver line status error 2 0 0 1 1 0 RX time out 2 0 0 0 1 0 RHR interrupt 3 0 0 0 0 1 THR interrupt 4 0 0 0 0 0 Modem interrupt 5 0 1 0 0 0 XOFF special character 6 1 0 0 0 0 CTS RTS DSR change state from active low to inactive high R 00000 0 IT_PENDING 0 An interrupt...

Page 784: ...tive R 0 1 Receiver line status interrupt active 5 TX_UE_IT 0 TX underrun interrupt inactive R 0 1 TX underrun interrupt active 4 STS_FIFO_IT 0 Status FIFO trigger level interrupt inactive R 0 1 Status FIFO trigger level interrupt active 3 RX_OE_IT 0 RX overrun interrupt inactive R 0 1 RX overrun interrupt active 2 RX_FIFO_LAST_ BYTE_IT 0 Last byte of frame in RX FIFO interrupt inactive R 0 1 Last...

Page 785: ...S flow control is enabled that is the RTS pin goes high inactive when the receiver FIFO HALT trigger level TCR3 0 is reached and goes low active when the receiver FIFO restore transmission trigger level is reached 5 SPECIAL_CHAR_ DETECT 0 Normal operation R W 0 1 Special character detect enable bit Received data is compared with XOFF2 data If a match occurs the received data is transferred to FIFO...

Page 786: ...F2 characters mustbetransmitted receivedsequentially with XON1 XOFF1 followed by XON2 XOFF2 XON1 and XON2 must be set to different values if the software flow control is enabled Table 12 61 XON1 Address Register 1 XON1 ADDR1 Bit Name Function R W Reset Value 7 0 XON_WORD1 Used to store the 8 bit XON1 character in UART mode and ADDR1 address 1 for SIR mode R W 0x00 Table 12 62 XON2 Address Register...

Page 787: ...ner ation of the baud clock in the baud rate generator DLL stores the least signifi cant part of the divisor DLH stores the most significant part of the divisor DLL and DLH can only be written to before sleep mode is enabled that is before IER 4 is set Table 12 66 Divisor Latch Low Register DLL Bit Name Function R W Reset Value 7 0 CLOCK_LSB Used to store the 8 bit LSB divisor value R W 0x00 Table...

Page 788: ...LT RCV FIFO trigger level to halt transmission 0 60 R W 1111 Note Trigger levels from 0 60 bytes are available with a granularity of four trigger level 4 x 4 bit register value The programmer must ensure that TCR 3 0 is greater than TCR 7 4 whenever automatic RTS or software flow control is enabled to avoid spurious operation of the device In FIFO interrupt mode with flow control the programmer mu...

Page 789: ...ne space required All zeros result in unpredictable behavior Note The protocol to set the concatenation of TLR and FCR is Set SCR 6 0 Set the value of threshold into FCR and TLR Set SCR 6 1 Table 12 71 Receive FIFO Trigger Level Setting Summary SCR 7 TLR 7 4 TX FIFO Trigger Level 0 0000 Defined by FCR7 6 either 8 16 56 and 60 characters 0 00000 Defined by TLR7 4 from 4 to 60 characters with a gran...

Page 790: ... Stores and controls the transmission R W 0 0 Starts the SIR transmission as soon as a value is written to THR 1 Starts the SIR transmission with the control of ACREG2 4 Reserved R 0 3 IR_SLEEP 0 SIR sleep mode disabled R W 0 1 SIR sleep mode enabled 2 0 MODE_SELECT 000 UART mode R W 111 001 SIR mode 111 Disable UART default state All the other values are reserved The MODE_SELECT 0x7 setting disab...

Page 791: ...e length registers TXFLL and TXFLH hold the 13 bit trans mit frame length TXFLL holds the least significant bits and TXFLH holds the most significant bits The frame length value is used if the frame length method of frame closing is used In terms of the IrDA frame format see Figure 12 14 the value stored in the TXFLH TXFLL registers is the byte length from A to I Table 12 74 Transmit Frame Length ...

Page 792: ...rame format with CRC and stop flag In terms of the IrDA frame format see Figure 12 14 the value stored in the RXFLH RXFLL registers is the byte length from A to EOF Table 12 76 Received Frame Length Low Register RXFLL Bit Name Function R W Reset Value 7 0 RXFLL LSB register used to specify the frame length in reception W 00000000 Offset Address hex 0x0D x Start Address Table 12 77 Received Frame L...

Page 793: ...FIFO when frame at top of FIFO was received R 0 3 FRAME_LENGTH_ ERROR 1 Frame length error in frame at top of FIFO R 0 2 ABORT_DETECT 1 Abort pattern detected in frame at top of FIFO R 0 1 CRC_ERROR 1 CRC error in frame at top of FIFO R 0 0 Reserved R 0 The resume register RESUME is used to clear internal flags which halt trans mission reception when an underrun overrun error occurs Reading this r...

Page 794: ...atus FIFO Register Low SFREGL Bit Name Function R W Reset Value 7 0 SFREGL LSB part of the frame length R Undefined Table 12 81 Status FIFO Register High SFREGH Bit Name Function R W Reset Value 7 4 Reserved R 0000 3 0 SFREGH MSB part of the frame length R Undefined The beginning of frame control register BLR 6 selects whether 0xC0 or 0xFF start patterns are to be used and when multiple start flag...

Page 795: ...DIV_1 6L Used to generate the 1 6 µs pulse R W 00000000 In SIR the DIV1 6 register DIV16 is used to generate 1 6 µs pulse encoding instead of 3 16 encoding when selected using ACREG 7 The value of DIV_1 6 is coded on ten bits by MDR2 4 3 for its MSB and DIV_1 6 7 0 for its MSB In SIR mode DIV1 6 must be programmed as follows DIV1 6 3 16 baud rate 1 6E 6 FCLK_frequency DIV1 6 0 is forbidden If the ...

Page 796: ...Name Value Function R W Reset Value 7 PULSE_TYPE SIR pulse width select R W 0 0 3 16 of baud rate pulse width 1 1 6 µs 6 SD_MOD Primary output used to configure transceivers Connected to the SD MODE input of transceivers R W 0 0 SD_MODE pin is set to high 1 SD_MODE pin is set to low 5 DIS_IR_RX 0 Enables RXIR input R W 0 1 Disables RXIR input for half duplex purpose 4 DIS_TX_UNDERRUN 0 Long stop b...

Page 797: ...writes the last byte to the TX FIFO in set EOT bit frame closing method This bit automatically gets cleared when the host writes to the THR TX FIFO R W 0 Table 12 86 OSC 12 MHz Select Register OSC_12M_SEL Bit Name Function R W Reset Value 7 1 Reserved R 0000000 0 OSC_12M_SEL When 1 selects 6 5 division factor with a 12 MHz system clock W 0 This register is write only and cannot be read Table 12 87...

Page 798: ... The UART uses a wired interface for serial communication with a remote device UART modules are functionally compatible to the TL16C750 UART and are also functionally compatible with earlier designs such as the TL16C550 UART modules can use hardware or software flow controls to manage transmission reception Hardware flow control significantly reduces software overhead and increases system efficien...

Page 799: ...host MPU or DSP reads the line status register LSR to find out the errors if any of the received frame Data can be transferred both ways simultaneously by the module but transmit and receive must not take place at the same time according to the standard The infrared output in SIR mode can either be 1 6 µs or 3 16 encoding selected by ACREG 7 In 1 6 µs encoding the infrared pulse width is 1 6 µs an...

Page 800: ...CE byte 3 Complements the bit 5 of the byte following the CE 4 Send the complemented byte to the CRC detector and stores it in the RX FIFO 12 8 2 3 Abort Sequence The transmitter may decide to prematurely close a frame The transmitting station aborts by sending the sequence 0x7dc1 The abort pattern closes the frame without a CRC field or an ending flag It is possible to abort a transmission frame ...

Page 801: ... Figure 12 15 While the serial data input to TXD is high the output TXIR is always low and the counter used to form a pulse on TXIR is continuously cleared After TXD resets to 0 TXIR rises on the falling edge of the 7th 16XCLK On the falling edge of the 10th 16XCLK pulse TXIR falls creating a 3 clock wide pulse While TXD remains low a pulse is trans mitted during the 7th to the 10th clocks of each...

Page 802: ...Mechanism RXD 1 2 4 5 6 3 7 8 10 11 12 9 13 14 16 15 16XCLK RXIR 12 8 2 7 Address Checking In SIR mode only frames intended for the device are written to the RX FIFO if address checking has been enabled This avoids receiving frames not meant for this device in a multipoint infrared environment You can program two frame addresses the UART IrDA receives with the XON1 ADDR1 and XON2 ADDR2 registers S...

Page 803: ... TX FSM TX FIFO Control TIPB interface RX FIFO Data exchanges Controls CLKGEN Clocks to all blocks RX FSM RXIR TXIR RX FSM SIR TX FSM UART RX FSM SIR RX FSM 12 9 2 Trigger Levels The UART provides programmable trigger levels for both receiver and trans mitter DMA and interrupt generation After reset both transmitter and receiver FIFOs are disabled in effect the trigger level is the default value o...

Page 804: ...rity Level Interrupt Type Interrupt Source Interrupt Reset Method 0 0 0 0 0 1 None None None None 0 0 0 1 1 0 1 Receiver line sta tus OE FE PE or BI errors occur in characters in the RX FIFO FE PE BI All erroneous characters are read form the RX FIFO OE Read LSR 0 0 1 1 0 0 2 RX time out Stale data in RX FIFO Read RHR 0 0 0 1 0 0 2 RHR interrupt DRDY data ready FIFO disable RX FIFO above trigger l...

Page 805: ...eneric Interrupt Functions in SIR Mode IIR Bit No Interrupt Type Interrupt Source Interrupt Reset Method 7 Received EOF Received end of frame Read IIR 6 Receiver line status interrupt CRC ABORT or frame length error is written into STATUS FIFO Read STATUS FIFO Read until empty maximum eight reads required 5 TX underrun THR empty before EOF sent Read RESUME register 4 Status FIFO interrupt Status F...

Page 806: ...ule in receive mode and from any source to UART FIFO in transmit mode When UART flow control is enabled along with interrupt capabilities you must ensure that the UART flow control FIFO threshold TCR 3 0 is greater than or equal to the receive FIFO threshold Figure 12 18 and Figure 12 19 show the receive and transmit IT operations respectively Figure 12 18 Receive FIFO IT Request Generation Progra...

Page 807: ... the threshold level The interrupt line is deasserted until a sufficient number of elements has been transmitted to go below FIFO threshold 12 9 5 FIFO Polled Mode Operation In FIFO polled mode FCR 0 0 with relevant interrupts disabled via interrupt enable register IER the status of the receiver and transmitter can then be checked by polling the line status register LSR This mode is an alternative...

Page 808: ...n is desired set SCR 0 to 1 and SCR 2 1 to 00 FCR 3 is disregarded If DMA mode 1 is desired either set SCR 0 to 0 and FCR 3 to 1 or set SCR 0 to 1 SCR 2 1 to 01 FCR 3 is disregarded If the FIFOs are disabled FCR 0 0 DMA occurs in single character trans fers When DMA mode 0 has been programmed the signals associated with DMA operation are not active 12 9 6 2 DMA Transfers DMA Mode 1 2 or 3 Figure 1...

Page 809: ...eration Programmable threshold Transmit FIFO level Zero byte time DMA request time DMA request Transmit FIFO level Full level active low Threshold writes from system DMA Number of spaces In transmit mode a DMA request is automatically asserted when FIFO is empty This request is deasserted when the number of bytes defined by the threshold level has been written by the system DMA The DMA request is ...

Page 810: ...clock are stopped internally Because most registers are clocked using these clocks the power consump tion is greatly reduced The module wakes up when any change is detected on the RX line when data is written to the TX FIFO or when there is any change in the state of the modem input pins An interrupt can be generated on a wake up event by setting SCR 4 to 1 Note Writing to the divisor latches DLL ...

Page 811: ...J Reset transmit FIFO if enabled J Wait for transmit shift register becomes empty LSR 6 1 J Take a guard time according to stop bit definition J Set LCR 6 to 1 The break condition is asserted as long as LCR 6 is set to 1 12 9 9 Programmable Baud Rate Generator The programmable baud generator takes any clock input and divides it by a divisor between 1 and 216 1 The CLKSEL register bit MCR 7 can be ...

Page 812: ...d in automatic RTS are stored in the TCR RTS is active if the RX FIFO level is below the HALT trigger level in TCR 3 0 When the receiver FIFO HALT trigger level is reached RTS is deasserted The sending device for example another UART can send an additional byte after the trigger level is reached because it may not recognize the deassertion of RTS until it has begun sending the additional byte RTS ...

Page 813: ...F2 must be received sequentially When the correct XOFF characters are received transmission is halted after completing transmission of the current character XOFF detection also sets IIR 4 if enabled via IER 5 and causes nIRQ to go low To resume transmission an XON1 2 character must be received in certain cases XON1 and XON2 must be received sequentially When the correct XON characters are received...

Page 814: ... but this functionality is included to maintain compatibility with earlier designs It is assumed that software flow control and hardware flow control are never enabled simultaneously 12 9 12 Frame Closing There are two methods by which a transmission frame can be properly terminated 1 The frame length method is selected when MDR1 7 0 The host MPU or DSP writes the frame length value to TXFLH and T...

Page 815: ...r transmission Before the next frame can be transmitted the system host must Reset the TX FIFO Read the RESUME register this clears the internal flag This functionality can be disabled or compensated for by the extension of the stop bit in transmission in case the TX FIFO is empty 12 9 15 Overrun During Receive Overrun occurs during receive if the RX state machine tries to write data into the RX F...

Page 816: ...modules obviously it does not cover every UART module feature The first stage covers software reset of the module interrupts status and controls the second stage deals with FIFO configura tion and enable and the last stage deals with baud rate data and stop configu ration The procedure below is programming language agnostic 12 11 UART Software Reset The goal of the UART software reset is to clear ...

Page 817: ...LR and FCR must be disabled to avoid any further undesired write to these registers J LCR 0xBF provides access to EFR J EFR 4 0 J LCR 7 0 J MCR 6 0 12 12 1 Baud Rate Data and Stop Configuration The goals of the baud rate and stop configuration are to configure UART data stop LCR register baud rate DLH and DLL registers and enable UART operation If interrupt capability is added configuration must b...

Page 818: ...al serial bus USB function module Topic Page 13 1 Overview 13 2 13 2 Register Map 13 9 13 3 USB Transactions 13 52 13 4 Device Initialization 13 79 13 5 Preparing for Transfers 13 83 13 6 Interrupt Service Routine ISR Flowcharts 13 86 13 7 DMA Operation 13 114 13 8 Power Management 13 127 Chapter 13 ...

Page 819: ... assumed All references to local host LH in this chapter refer to the MPU processor Figure 13 1 shows the OMAP5910 device with the USB function module high lighted Figure 13 2 shows the connection of the USB function module within the OMAP5910 in more detail 13 1 1 OMAP5910 Inputs Outputs Several configurations are possible for the USB function USB function usable with internal transceiver default...

Page 820: ...eripherals bus DSP public shared pheripheral bus 32 MPU public 16 DSP DSP public peripherals McBSP1 McBSP3 MPU public peripherals USB Host I F JTAG emulation I F OSC 12 MHz Clock OSC OMAP5910 ETM9 Timers 3 MPU DSP shared peripherals Mailbox MPU private peripherals Timers 3 16 Memory interface Reset External clock MPU Bus 32 kHz 1 5M bits traffic controller TC Watchdog timer Level 1 2 interrupt han...

Page 821: ...EQ_ON ULPD_nIrq Irq24 WKUP_REQ 12 MHz CLKIN PERCLK VBUS_MODE VBUS_CTRL FUNC_MUX_CTRL_0 18 FUNC_MUX_CTRL_0 19 MOD_CONF_CTRL_0 17 USB _GPIO GPIO 0 FUNC_MUX_CTRL_7 11 9 0 DVDD2 OMAP5910 PU_EN_O FUNC_MUX_CTRL_D 5 3 1 5 K D D Clock generation USB_CLKO USB_PUEN 6 MHz USB HOST HMC USB_DP USB_DN USB transcievers SUSPEND_O TXD_O GZ_O RXD RXDP RXDM SEO_O PORT0 OMAP5910 MOD_CONF_CTRL_0 6 1 Detection Cell RES...

Page 822: ...hutdown by the USB function DISABLE_CLK48_O when J The USB is suspended idle state J The USB is disconnected This shutdown must be enabled beforehand Set SOFF_Dis bit 1 of the SYSCON1 register to 0 default value The MPU TIPB reset MPU_PER_RST resets the USB function 13 1 4 USB Function DMA Requests The USB function can use Three receive DMA channels DMA_RX_REQ_ON 2 0 Any endpoint number 1 15 can b...

Page 823: ...anagement Once the interface clock is present the USB function can generate an attached unattached interrupt when it detects that the OMAP5910 device is connected to an external USB host or hub or when it becomes disconnected This attached unattached interrupt uses the general USB interrupt line connected to the MPU level 2 interrupt handler line 20 and the connection state is given by the ATT bit...

Page 824: ...his detection must be enabled by software as follows In either the OMAP1509 or OMAP5910 configuration mode when the VBUS_GPIO0_SELECT bit 12 FUNC_MUX_CTRL_1 register is set Or In the OMAP5910 configuration mode when the CONF_GPIO0_MODE bits 11 9 FUNC_MUX_CTRL_7 register are set to 010 The results of this detection are as follows GPIO0 input 0 USB not connected default value via internal pulldown G...

Page 825: ...t cannot detect the OMAP5910 USB function PullUp_En bit 1 The external 1 5 kΩ is seen as a pullup on the USB D the USB host detects this level and therefore the presence of the OMAP5910 USB function The USB host can then configure the USB function The USB PUEN signal is multiplexed inside OMAP5910 with the USB CLKO clock Bits 5 3 of the FUNC_MUX_CTRL_D register control this multiplexing FUNC_MUX_C...

Page 826: ...x10 RXFSTAT Receive FIFO status R 0x14 SYSCON1 System configuration 1 R W 0x18 SYSCON2 System configuration 2 Set only 0x1C DEVSTAT Device status R 0x20 SOF Start of frame R 0x24 IRQ_EN Interrupt enable R W 0x28 DMA_IRQ_EN DMA interrupt enable R W Clear 0x2C IRQ_SRC Interrupt source R Clear 0x30 EPN_STAT Endpoint interrupt status R 0x34 DMAN_STAT DMA endpoint interrupt status R 0x38 Reserved 0x3C ...

Page 827: ...84 EP2_RX Receive endpoint configuration 2 R W 0x88 EP15_RX Receive endpoint configuration 15 R W 0xBC Reserved 0xC0 EP1_TX Transmit endpoint configuration 1 R W 0xC4 EP2_TX Transmit endpoint configuration 2 R W 0xC8 EP15_TX Transmit endpoint configuration 15 R W 0xFC Note on register accesses The local host may read from or write into registers using one of the follow ing accesses J 16 bit access...

Page 828: ... current USB function module This value is fixed by hardware 0x01 Revision 0 1 0x02 Revision 0 2 0x21 Revision 2 1 Local host LH and universal serial bus USB reset have no effect on this register 13 2 2 Endpoint Selection Register EP_NUM The read write endpoint selection register EP_NUM selects and enables the endpoint that can be accessed by the local host Table 13 3 Endpoint Selection Register E...

Page 829: ...P_Sel Set by the local host to access the status STAT_FLG RXFSTAT and data DATA registers for the endpoint selected If EP_Dir bit is set to 0 the local host can read data from endpoint RX FIFO by reading the DATA register if EP_Dir bit is set to 1 the local host can write data into endpoint TX FIFO by writing into the DATA register After each access to an endpoint during interrupt handling the loc...

Page 830: ... a selected TX endpoint to read data from a selected RX endpoint or to read data from the setup FIFO If selected endpoint direction is OUT this register is read only and a write into it is forbidden If selected endpoint direction is IN this register is write only and a read of this register is forbidden Table 13 4 Data Register DATA Bit Name Description 15 0 DATA Transmit receive FIFO data 13 2 3 ...

Page 831: ...Name Description 15 8 Reserved 7 Clr_Halt Clear halt endpoint non isochronous 6 Set_Halt Set halt endpoint non isochronous 5 3 Reserved 2 Set_FIFO_En Set FIFO enable non isochronous 1 Clr_EP Clear endpoint 0 Reset_EP Endpoint reset non Ctrl 13 2 4 1 Clear Halt Endpoint Clr_Halt Only concerns non isochronous endpoints Used by the local host to clear an endpoint halt condition 0 No action 1 Clear ha...

Page 832: ...uring the handling of an interrupt to the endpoint the local host must not set the EP_Sel bit before setting the Set_Halt bit in order to avoid possible impacts on interrupts The local host must check that FIFO is empty before setting the halt feature for the endpoint A stalled transaction has no effect in clearing the FIFO 13 2 4 3 Set FIFO Enable Set_FIFO_En Only concerns non isochronous endpoin...

Page 833: ...ear Endpoint Clr_EP This bit is set by the local host to clear the selected endpoint FIFO pointers and flags This resets the FIFO pointers and the FIFO empty status bit The FIFO enable bit and other FIFO flags are cleared upon completion of the FIFO reset Previous transaction handshake status is also cleared For isochronous end points or non isochronous double buffered endpoints both foreground an...

Page 834: ...he endpoint Note Non transparent non isochronous IN transactions are those transactions responding with an ACK handshake a STALL handshake or optionally a NAK handshake if the Nak_En bit is asserted to 1 An ERR handshake or a NAK handshake when the Nak_En bit is 0 is considered transparent A write to this register has no effect Table 13 6 Status Register STAT_FLG Bit Name Description 15 Reserved 1...

Page 835: ...ata was flushed Value after local host or USB reset is low 13 2 5 2 Isochronous Receive Data Flush Data_Flush Only concerns isochronous OUT endpoints When set this bit indicates that data was flushed from the isochronous FIFO that was moved from the foreground to the background This happens when the local host does not read all of the data from the foreground FIFO in a frame This bit is updated ev...

Page 836: ...O Full ISO_FIFO_Full Only concerns isochronous endpoints Set when the FIFO for the selected isochronous endpoint is full This condition is cleared by setting the Clr_EP bit or the Reset_EP bit or after one successful read by the local host or the USB host 0 Isochronous FIFO not full 1 Isochronous FIFO full Value after local host or USB reset is low FIFO empty 13 2 5 6 Endpoint Halted Flag EP_Halte...

Page 837: ...urrent buffer The USB core automatically returns a NAK handshake to the USB host if a valid IN token is received by a TX endpoint or if a valid OUT transaction is received by an RX endpoint and the FIFO_En bit is not set for the endpoint The bit is cleared when the local host has finished handling the corresponding interrupt at EP_Sel bit deselection 0 No NAK handshake was returned the Nak_En bit ...

Page 838: ...he FIFO for the selected non isochronous endpoint is empty either via an appropriate Clr_EP bit or the Reset_EP bit or after successful reads from the selected FIFO 0 Non isochronous FIFO not empty 1 Non isochronous FIFO empty Value after local host or USB reset is high FIFO empty 13 2 5 12 Non Isochronous FIFO Full Non_ISO_FIFO_Full Only concerns non isochronous endpoints Set when the FIFO for th...

Page 839: ...10 Reserved 9 0 RXF_Count Receive FIFO byte count 13 2 6 1 Receive FIFO Byte Count RXF_Count This 10 bit field indicates the number of bytes currently in the receive FIFO Value after local host or USB reset is low all 10 bits 13 2 7 System Configuration Register 1 SYSCON1 The read write system configuration 1 register SYSCON1 provides control functions for power management and miscellaneous contro...

Page 840: ...when cleared NAK handshake response to the USB host is made transparent to the local host and no interrupt is asserted 0 NAK disabled 1 NAK enabled Value after local host or USB reset is low Note If the local host sets this bit it must wait for a NAK interrupt before selecting the TX endpoint to write TX data 13 2 7 3 Self Powered Self_Pwr Indicates to the USB host whether the device is bus powere...

Page 841: ...egister always returns 0 Table 13 9 SYSCON2 System Configuration Register 2 SYSCON2 Bit Name Description 15 7 Reserved 6 Rmt_Wkp Remote wakeup 5 Stall_Cmd Stall command 4 Reserved 3 Dev_Cfg Device configured 2 Clr_Cfg Clear configured 1 0 Reserved 13 2 8 1 Remote Wakeup Rmt_Wkp This set only bit when written with a 1 initiates the remote wakeup sequence regardless of whether or not the R_Wk_OK bit...

Page 842: ...codes that the device has moved to the configured state The CFG bit is set to 1 by the core If the device is already configured when the SET_CONFIGURATION request is received the local host must not set this bit If the new configuration value is 0 it must set the Clr_Cfg bit in order to move to the addressed state Reading this bit always returns 0 Writing 0 to this bit has no effect 0 No action 1 ...

Page 843: ... change is not visible because the background register was updated and not moved into foreground position Table 13 10 Device Status Register DEVSTAT Bit Name Description 15 7 Reserved 6 R_WK_OK Remote wakeup granted 5 USB_Reset USB reset signaling is active 4 SUS Suspended state 3 CFG Configured state 2 ADD Addressed state 1 DEF Default state 0 ATT Attached state 13 2 9 1 Remote Wakeup Enabled R_W...

Page 844: ...pended State SUS Device is at minimum attached to the USB and is powered has been reset by the USB host and has not seen bus activity for 5 ms It may also have a unique address and be configured for use However because the device is suspended the host can not use the device function This bit returns 1 when the USB device is in suspend state 0 Not suspended 1 Suspended Value after local host or USB...

Page 845: ...returns 1 when the USB device is attached to the USB and powered and has been reset This bit remains set to 1 until the device becomes depow ered Device moves into default state as soon as the USB reset is effective 0 Not in default 1 Default Value after local host is low and after USB reset is high 13 2 9 7 Attached State ATT This bit returns 1 when the device is attached to the USB and powered T...

Page 846: ...IF allowed by USB 1 1 speci fication IF 11964 12036 USB bit time If TF is out of this interval the FT_Lock value remains 0 and a local SOF is generated by the core When the FT_Lock bit is set and the frame timer is locked to the timing TF a local SOF is generated if no valid SOF has been received in an interval of TF since the last valid the The FT_Lock bit is cleared if a valid SOF is received ou...

Page 847: ... non DMA interrupts control state changed isochronous non isochronous Table 13 12 Interrupt Enable Register IRQ_EN Bit Name Description 15 8 Reserved 7 SOF_IE Start of frame interrupt enable 6 Reserved 5 EPn_RX_IE Receive endpoint n interrupt enable non isochronous 4 EPn_TX_IE Transmit endpoint n interrupt enable non isochronous 3 DS_Chg_IE Device state changed interrupt enable 2 1 Reserved 0 EP0_...

Page 848: ...rt of frame interrupt flag 6 Reserved 5 EPn_RX EPn OUT transactions interrupt flag 4 EPn_TX EPn IN transactions interrupt flag 3 DS_Chg Device state changed interrupt flag 2 Setup Setup transaction interrupt flag 1 EP0_RX EP0 OUT transactions interrupt flag 0 EP0_TX EP0 IN transactions interrupt flag Common to all bits The local host can only clear a set bit location by writing a 1 into the bit lo...

Page 849: ...on isochronous transmit DMA transfer for a channel has ended Value after local host or USB reset is low 13 2 12 2 RX DMA CH n Transactions Count Interrupt Flag RXn_Cnt Only for non isochronous DMA transfer This bit is never set for isochronous DMA transfer This bit is set automatically by the core during an active receive DMA transfer each time RXn_TC equals 0 after an OUT transaction with ACK sta...

Page 850: ...he RXn_Stop bit is set When this bit is asserted the local host must read the DMAn_RX_IT_src to identify the endpoint number for which the transfer completed and must read the DMAn_RX_SB to be informed of an odd number of bytes received during the last transaction useful for 16 bit read access from DATA_DMA register The endpoint interrupt EPn_RX bit is never set for the assigned endpoint to RX DMA...

Page 851: ...er to identify the endpoint causing the interrupt 0 No action 1 IN transaction detected on an endpoint Value after local host or USB reset is low 13 2 12 7 Device State Changed Interrupt Flag DS_Chg This bit is automatically set by the core when the state of the device changes This is when the core modifies any of the bits present in the DEVSTAT register When this bit is cleared the background DEV...

Page 852: ...with the Nak_En bit set ACK or STALL 0 No action 1 OUT transaction on EP0 Value after local host or USB reset is low 13 2 12 10 IRQ_SRC 0 EP0_TX IN Transaction Endpoint 0 Interrupt Flag This bit is set automatically by the core when a handshake sequence occurs for a non autodecoded IN transaction to control endpoint NAK with the Nak_En bit set ACK or STALL 0 No action 1 IN transaction on EP0 Value...

Page 853: ...nt interrupt source non isochronous 7 4 Reserved 3 0 EPn_TX_IT_src Transmit endpoint interrupt source non isochronous 13 2 13 1 Receive Endpoint Interrupt Source EPn_RX_IT_src Only concerns non isochronous endpoints When the EPn_RX flag bit is set the endpoint causing the interrupt condition is encoded in these four register bits When the EPn_RX flag bit is cleared the four bits read as 0 0000 No ...

Page 854: ...MA receive single byte non isochronous 11 8 DMAn_RX_IT_src DMA receive interrupt source non isochronous 7 4 Reserved 3 0 DMAn_TX_IT_src DMA transmit interrupt source non isochronous 13 2 14 1 DMA Receive Single Byte DMAn_RX_SB Only concerns non isochronous endpoints isochronous endpoints receive a constant number of bytes This bit is set when the RXn_EOT interrupt is asserted and the core receives...

Page 855: ...point causing this flag to be set is encoded in these four register bits When the EPn_TX flag is cleared the four bits read as 0 0000 No transmit DMA interrupt is pending 0001 EP1 1111 EP15 Value after local host or USB reset is low all 4 bits 13 2 15 Receive DMA Channels Configuration Register RXDMA_CFG The read write receive DMA channels configuration register RXDMA_CFG enables the three possibl...

Page 856: ...o value indicates that the DMA channel 2 is deactivated Any other value automatically enables receive DMA transfer for the selected endpoint 0000 Receive DMA channel 2 is deactivated 0001 EP1 1111 EP15 Value after local host or USB reset is low all 4 bits 13 2 15 2 Receive Endpoint Number for DMA Channel 1 RXDMA1_EP The endpoint number binary encoded in these four bits is the current receive endpo...

Page 857: ... TXDMA_CFG The read write transmit DMA channels configuration register TXDMA_CFG enables the three possible DMA transmit channels and selects the endpoint number that is assigned to each of these DMA channels An endpoint used by a TX DMA channel must have been configured through register EPn_TX TXDMA_CFG register can be filled when the Cfg_Lock bit is set There is no hardware mechanism to protect ...

Page 858: ...n these four bits is the current transmit endpoint selected for DMA channel 1 A zero value indicates that the DMA channel 1 is deactivated Any other value automatically enables transmit DMA transfer for the selected endpoint 0000 Transmit DMA channel 1 is deactivated 0001 EP1 1111 EP15 Value after local host or USB reset is low all 4 bits 13 2 16 3 Transmit Endpoint Number for DMA Channel 0 TXDMA0...

Page 859: ...a TX DMA request is active for a channel only one active at a given time this register contains the data written by the main DMA controller engine write access in response to a DMA request for the transmit channel to be sent to the USB host during the next IN transaction It is possible for both an RX DMA request and a TX DMA request to be active at the same time In this case the main DMA controlle...

Page 860: ... of the endpoint buffer size the TX done interrupt is asserted only after an IN transaction with an empty data packet When cleared the transfer size set in TXn_TSC is in full buffer size for the end point selected BULK only A TX done interrupt is asserted when the last buff er is sent with the last IN transaction This mode is to be used for a partial bulk transfer of a large file exceeding 1023 by...

Page 861: ...smit This read mode is only provided for software debug purposes For isochronous transfer the user must verify that the set value does not exceed the isochronous FIFO size for the endpoint There is no hardware mechanism to protect from this situation If it happens results are unpredictable For bulk transfer when TXn_EOT 0 a set value of TXn_TSC 0 means 1024 buffers and not 0 The counter then opera...

Page 862: ... transfer At end of transfer the DMA channel is disabled and all OUT transactions received to the assigned endpoint are sent NAK by the core The local host must set the Set_FIFO_En for the endpoint to reenable the channel Value after local host or USB reset is low 13 2 19 2 Receive DMA Ch n Transactions Count RXn_TC The local host can ask for an interrupt each n OUT transactions where n is the enc...

Page 863: ...eceding configuration phase Status flags the Non_ISO_FIFO_Empty the Non_ISO_FIFO_Full and overrun underrun con ditions are based on this value for all IN and OUT transactions to endpoint 0 The local host must fill this field before setting the Cfg_Lock bit 00 8 bytes 01 16 bytes 10 32 bytes 11 64 bytes Value after local host reset is low both bits after USB reset is unchanged 13 2 20 2 Endpoint 0 ...

Page 864: ...the Cfg_Lock bit and must not change the values once Cfg_Lock bit is set Table 13 22 Receive Endpoint n Configuration Registers EP1_RX EP15_RX Bit Name Description 15 EPn_RX_Valid Receive endpoint n valid 14 EPn_RX_Size Db Receive non isochronous endpoint n double buffer Db Or receive isochronous endpoint n size 2 13 12 EPn_RX_Size Receive endpoint n size 11 EPn_RX_Iso Receive isochronous endpoint...

Page 865: ...fter local host reset or USB reset is unchanged 13 2 21 3 Receive Endpoint n Size EPn_RX_Size This paragraph includes description of EPn_RX 14 bit for isochronous endpoints This field contains the endpoint n FIFO size value Status flags the Non_ISO_FIFO_Empty the Non_ISO_FIFO_Full the ISO_FIFO_Empty the ISO_FIFO_Full and overrun and underrun conditions are based on this value for all OUT transacti...

Page 866: ...nter EPn_RX_ptr This field contains the address of the receive endpoint n pointer Value 0x000 is forbidden reserved for setup FIFO For isochronous endpoints or for non isochronous endpoints that allow double buffering 2 RX buffer size must be reserved for ping pong 0x000 address BASE forbidden 0x001 address BASE 8 bytes 0x002 address BASE 16 bytes 0x003 address BASE 24 bytes 0x0FF address BASE 204...

Page 867: ..._TX_Valid Transmit Endpoint n Valid This bit must be set by the local host to allow transmit endpoint n to be used for USB transfers as part of the device configuration If not set all transactions to this endpoint are ignored by the core 1 Transmit endpoint n is part of the device configuration 0 Transmit endpoint n does not exist for this configuration Value after local host reset is low after US...

Page 868: ...oes not distinguish bulk type from interrupt 0 Transmit endpoint n type is isochronous 1 Transmit endpoint n type is bulk or interrupt Value after local host or USB reset is unchanged 13 2 22 5 Transmit Endpoint n Pointer EPn_TX_ptr This field contains the address of the transmit endpoint n pointer For isochronous endpoints or for non isochronous endpoints that allow double buffering 2 TX buffer s...

Page 869: ...ing in the confusion of special cases related to other styles 13 3 1 Non Isochronous Non Setup OUT USB HOST LH Transactions Non isochronous non setup OUT transactions refer to USB transactions where data is moved from the USB host to the local host and where the USB handshaking protocols are in effect and data transmission is guaranteed These types of transactions apply to all OUT transactions on ...

Page 870: ...PID check error bit stuffing error or overrun conditions EPx Rx Interrupt EPx RX Interrupt EPx RX Interrupt STAT_FLG bits after interrupt ACK STALL EP_Halted NAK 1 0 0 0 STAT_FLG bits after interrupt 0 0 0 1 STAT_FLG bits after interrupt 0 1 1 0 0 1 0 0 or After interrupt EP s RX FIFO contains received data After interrupt EP s RX FIFO is empty After interrupt EP s RX FIFO is empty No EPx RX inter...

Page 871: ... local host software has dealt with the OUT transaction data in the endpoint RX FIFO it must re enable the endpoint OUT transaction reception by setting the Set_FIFO_En bit Local host software can use the Set_FIFO_En bit as a receive flow control mechanism Acknowledged Transactions ACK At completion of an OUT transaction to an endpoint the USB module issues an endpoint specific interrupt to the lo...

Page 872: ...1 2 Non Isochronous Non Control OUT Transaction Error Conditions STALLed Transactions The USB module responds to an endpoint OUT transaction with a STALL handshake to indicate an error condition on the endpoint either if the end point s EP_Halted bit is set or if a request error occurs control transactions only When an endpoint OUT transaction is given a STALL handshake the endpoint s STALL bit is...

Page 873: ...ata packet of an OUT transaction no handshake is returned to the USB host to signal an error Sequence Bit Errors If the core does not receive expected DATA PID during an OUT transaction the module automatically returns an ACK handshake to the USB host regard less of the FIFO_En bit per USB spec Data is ignored and no interrupt is asserted to the local host This error occurs if an ACK handshake fro...

Page 874: ... the endpoint s previous transmit activity is taken care of the local host code gains access to endpoint s FIFO and status by setting EP_Sel bit Then the local host can write the new transmit data to the endpoint TX FIFO via the DATA register being careful not to overflow the FIFO Once all of the transmit data has been written to the endpoint FIFO local host code sets the Set_FIFO_En bit to allow ...

Page 875: ... TX FIFO is empty Endpoint TX FIFO is unchanged by this USB transaction No interrupt occurs STAT_FLG is unchanged Indicates a packet received by the device Indicates a packet sent by the device Data Stage not executed Stage not executed No handshake received when token was received STAT_FLG bits after interrupt ACK STALL EP_Halted NAK 1 0 0 0 STAT_FLG bits after interrupt 0 0 0 1 STAT_FLG bits aft...

Page 876: ...s transmitted during the IN transaction If the local host has more data to transmit to the USB host it must fill the TX FIFO following the process indicated above It must then clear the EP_Sel bit This clears the ACK bit for this endpoint and allows the next transaction status to be written to the STAT_FLG register Non must Transactions NAK For the case where the local host is not ready to provide...

Page 877: ... is set as shown in the third case in Figure 13 4 or if a request error occurs control transaction only A STALL handshake indicates that the de vice endpoint is in a condition where it is not able to transfer data and that the USB host must not retry the transaction The device typically requires interven tion via some other mechanism to clear the condition typically a control trans fer via endpoin...

Page 878: ...onfigured FIFO size 13 3 3 Isochronous OUT USB HOST LH Transactions Isochronous OUT transactions are USB transactions where a given amount of data is transferred from the USB host to the USB function module device every 1 ms USB frame No USB handshaking is provided and no endpoint specific interrupt to the local host is generated at completion of an isochronous OUT transaction The local host is re...

Page 879: ... second case in Figure 13 4 Figure 13 5 Isochronous OUT Transaction Phases and Interrupts ISO OUT Token Data Successful data transfer from USB host No handshake occurs Endpoint RX FIFO contains receive data after data packet completes No interrupt occurs Indicates a packet received by the device Indicates a packet sent by the device SOF Token Reception of SOF causes SOF interrupt SOF Interrupt LH ...

Page 880: ...y the RXF_Count If the USB host sends more data than the FIFO can contain the FIFO is cleared and the ISO_Err bit is set at the next SOF interrupt A properly configured USB system does not do this Both foreground and background isochronous FIFOs are cleared when the Clr_EP bit is set 13 3 4 Isochronous IN LH USB HOST Transactions Isochronous IN transactions are USB transactions where a given amoun...

Page 881: ... implemented for isochronous IN endpoints Figure 13 6 shows the transaction phases associated with isochronous IN transactions and the SOF transaction No endpoint specific interrupt to the local host is generated as a result of an isochronous IN transaction There is no handshake phase The SOF transaction causes an SOF interrupt to the local host it is assumed that the local host refills the isochr...

Page 882: ...rror Conditions If the local host attempts to overfill the configured endpoint FIFO data written to the DATA register after the TX FIFO is full is lost but any data that was suc cessfully put into the FIFO is transmitted when that FIFO is the background FIFO and an IN transaction for that endpoint occurs Since an isochronous TX FIFO is cleared automatically on the toggle from background to foregro...

Page 883: ...ngth data Completion Status Data Stage Setup Stage Status Stage Setup Token Command ACK IN Token Stall Status Token 0 length data Stall set address clear set device interface feature due to wrong setup data Wrong Autodecode control read transfers correct status get device endpoint status Autodecode control read transfers request error due to wrong setup or command data Autodecode control read tran...

Page 884: ...tus Stage Non autodecode control read transfers request error due to LH setting CTRL Stall_Cmd EP0 RX Interrupt STAT_FLG STALL bit set EP0 TX Interrupt STAT_FLG STALL bit set one per In transaction EP0 RX Interrupt STAT_FLG ACK bit set EP0 TX Interrupt STAT_FLG ACK bit set EP0 TX Interrupt STAT_FLG STALL bit set Setup Interrupt EP0 RX Interrupt STAT_FLG ACK bit set one per OUT transaction EP0 RX I...

Page 885: ...SB endpoint 0 TX interrupt indicates that the previously provided transmit data has been sent Any additional data must be written to the endpoint 0 FIFO For control writes the write data must be pulled from the endpoint 0 FIFO and when all control write data is available interpret the write data and act on the write request After han dling the last data phase interrupt the local host must set the ...

Page 886: ...dule device address register If the new address is different from 0 the device moves into addressed state the ADD bit set if it was not already addressed For set and clear feature control writes the appropriate feature information bit is set or cleared When a set or clear feature transfer occurs to set or clear the device s remote wakeup feature the R_WK_OK bit is set or cleared as appropriate If ...

Page 887: ...which is ignored by the USB module The FIFO_En and Stall_Cmd bits have no effect on the handshaking If the status packet has a DATA0 PID instead of a DATA1 PID status is STALLed and no interrupt is asserted to the local host If the setup packet has a DATA1 PID instead of a DATA0 PID setup transaction is ignored error Autodecoded Control Read Transfer Error Conditions If the token phase or the data...

Page 888: ...due to the setup stage request see Figure 13 8 If there is one or more data stages for the transfer the local host must set the Set_FIFO_en bit for endpoint 0 to allow the core to accept RX data from the coming OUT transaction The data stage for non autodecoded control writes consists of zero or more OUT transactions Transaction handshaking and interrupt generation apply as for non isochronous non...

Page 889: ...e to move back into the addressed state the CFG bit cleared If the device receives a valid set interface request it must reset all endpoints used by the interface set by setting the Reset_EP control bits and must set the halt conditions for endpoints not used by this interface Other local host required actions are specific to the request and not detailed in this document Non Autodecoded Control Wr...

Page 890: ...UPT transactions If a packet is received corrupted the core ignores the transaction and no interrupt is asserted 13 3 5 4 Non Autodecoded Control Read Transfers Non autodecoded control read transfers include the GET_INTERFACE_STA TUS GET_CONFIGURATION GET_INTERFACE GET_DESCRIPTOR SYNCH_FRAME and class or vendor specific control read transfers Non autodecoded control read transfers consist of three...

Page 891: ...size no zero length packet is required A zero length packet is required only when the amount of data the device has to return is less than the amount requested by the host and the amount returned is a multiple of the maximum packet size Non Autodecoded Control Read Transfer Handshaking Handshaking for the setup stage of non autodecoded control read transfers is forced by the USB module to always b...

Page 892: ...y setting endpoint 0 s Stall_Cmd bit which causes stalling of all the remaining transactions of all remaining stages of a non autodecoded control transfer up to the reception of the next valid SETUP command Error conditions are handled as for bulk interrupt transactions The USB func tion module responds to control read status stage transactions that have a bad token or bad data by not sending a ha...

Page 893: ...t must reset the endpoint after having handled the pending transactions if CLEAR or set halt condition if SET For EP 0 local host only has to clear or set halt condition FIFO and data PID are always correct for next setup Command is passed to the local host SET_ ADDRESS Device Autodecoded None Whether the device is addressed or not is available in DEVSTAT register A valid SET_ADDRESS request with ...

Page 894: ...configuration set and then set the Dev_Cfg bit if config nb is not 0 or set the Clr_Cfg bit if config nb is 0 before allowing status stage to complete The device goes to configured state if Dev_Cfg set or moves to addressed state if Clr_Cfg set and a DS_Chg interrupt is asserted to the local host Command is passed to the local host GET SET INTERFACE Interface Non autode coded The local host must s...

Page 895: ... control transfer data stage length is indicated in setup data packet During control reads if the USB host requests more data than indicated in set up packet an unexpected IN transaction is STALLed causing STALL hand shake for all remaining transactions of the transfer until next SETUP If the USB host requires less data than indicated in the setup packet the transfer is not STALLed However if the ...

Page 896: ...fied size 2048 bytes and the local host can choose its configuration by setting appropriate value Figure 13 9 shows an example of RAM organization Once the endpoints are configured the local host must set the Cfg_Lock bit If this bit is not set all transactions are ignored by the core Then when the local host is ready to communicate with the USB host it must set the Pullup_En bit The local host ca...

Page 897: ...tr EP0_Size EP1_RX_Size or 2 EP1_RX_Size if Double Buffering or ISO EP1_RX_ptr EP3_RX_ptr EP15_RX_ptr EP1_TX_ptr EP2_TX_ptr EP3_TX_ptr EP15_TX_ptr EP2_RX_Size or 2 EP2_RS_Size if EP15_RX_Size or 2 EP15_RX_Size if EP1_TX_Size or 2 EP1_TX_Size if EP2_TX_Size or 2 EP2_TX_Size if EP15_TX_Size or 2 EP15_TX_Size if Double Buffering or ISO Double Buffering or ISO Double Buffering or ISO Double Buffering ...

Page 898: ...ields Nak_En Self_Pwr SOFF_Dis Pullup_En The LH can keep Pullup_En value set to 0 if not ready to communicate with the USB host No At this point the LH must initialize all flags used by ISR flowcharts including Set DS_mem flag to 0x0000 see device state changed handler Set control read and control write flags to 0 Set FIFO not full and double buffer flag to 0 Fill IRQ_EN register with appropriate ...

Page 899: ..._ptr Ptr_flag Ptr_flag Ptr_flag EP0_Size Fill EPn_TX register with EPn_TX_Valid 1 EPn_TX_Db 0 EPn_TX_Size EP Size 2 bits EPn_TX_Iso 0 EPn_TX_ptr Ptr_flag Fill EPn_TX register with EPn_TX_Valid 1 EPn_TX_Size EP Size 3 bits EPn_TX_Iso 1 EPn_TX_ptr Ptr_flag Double buffer allowed for EPn Fill EPn_RX register with EPn_RX_Valid 1 EPn_RX_Db 0 EPn_RX_Size EP Size 2 bits EPn_RX_Iso 0 EPn_RX_ptr Ptr_flag Fi...

Page 900: ...oint interrupts Whether double buffering is allowed or not is transparent to the local host unless both FIFOs are cleared through the Clr_EP or the Reset_EP bits In that case and in the case where the local host finishes handling an interrupt without having set the Set_FIFO_En bit the local host must reenter the Prepare for USB RX Transfers routine For transmit endpoints the local host enters the ...

Page 901: ...n Write EP_NUM register EP_NUM EP_Num n EP_NUM EP_Dir 0 EP_NUM EP_Sel 0 EP_NUM Setup_Sel 0 Set CTRL Set_FIFO_En Any OUT endpoint configured EPn Another OUT endpoint configured EPn Yes End of prepare for USB RX transfers routine Yes Note This applies to all non ISO endpoints with or without DMA No No Yes This enables both FIFOs if double buffering is used ...

Page 902: ...Setup_Sel 0 Set CTRL Set_FIFO_En bit Write one packet Size EPn_TX_Size This does not apply to TX endpoints using DMA which are enabled when TXDMAn Start is set by the LH End of prepare for USB TS transfer for Endpoint n routine At this point TX data is written in response to EPn_TX interrupts Write EP_NUM register EP_NUM EP_Num n EP_NUM Dir 1 EP_NUM EP_Sel 0 EP_NUM Setup_Sel 0 6 WAIT STATES Note N...

Page 903: ...ion module The flow charts in this section assume that the Nak_En bit is cleared A key assumption behind the flowcharts presented here is that the application provides separate buffers for each direction of endpoint except for endpoint 0 The flowcharts show reads from these application buffers for IN transactions on TX endpoints and they show writes to these application buffers for OUT transaction...

Page 904: ...nsfers on endpoint 0 or non isochronous DMA transfers in either receive or transmit mode Multiple interrupts may be active at any time and all interrupts must be dealt with by the ISR before returning from the ISR Figure 13 14 shows an appropriate flowchart for parsing the general USB interrupts 13 6 3 Setup Interrupt Handler A separate interrupt flag exists for setup transactions so that the loca...

Page 905: ... IRQ_SRC EP0_TX 1 EP0 TX Handler Set IRQ_SRC EP0_TX 1 to clear the IT IRQ_SRC RXn_EOT 1 Non ISO RX DMA End of Transfer Handler IRQ_SRC RXn_Cnt 1 Non ISO RX DMA Transactions Count Handler IRQ_SRC TXn_Done 1 Non ISO TX DMA Done Handler The interrupt must be cleared within the device state changed handler IRQ_SRC Chg 1 Setup Handler DMA interrupts are cleared within their respective handlers Yes No N...

Page 906: ...tion wlength_count 0 Ready to receive data Want to go out of the ISR Set CTRL Set_FIFO_En to 1 Wait until ready to receive Set CTRL Set_FIFO_En to 1 Prepare for control write stage status wlength_count wlenght Application specific action to cancel any ongoing transfer Clear control flags Set control write flag Set control read flag No No No Write EP_NUM register EP_NUM EP_Num 0 EP_NUM EP_Dir 0 EP_...

Page 907: ... Read byte from DATA register Save LS byte of windex Read byte from DATA register Save MS byte of windex Read byte from DATA register Save LS byte of wLength Read byte from DATA register Save MS byte of wLength Write EP_NUM register EP_NUM EP_Num 0 EP_NUM EP_Dir 0 EP_NUM EP_Sel 0 EP_NUM Setup_Sel 1 This clears the IRQ_SRC Setup bit Write EP_NUM register EP_NUM EP_Num 0 EP_NUM EP_Dir 0 EP_NUM EP_Se...

Page 908: ...Endpoint 0 TX Interrupt Handler The endpoint 0 TX portion of the general USB interrupt handler shown in Figure 13 19 must handle general USB interrupts related to control IN transactions on endpoint 0 The endpoint 0 TX interrupt handler must be able to move data into the end point 0 TX FIFO when the application buffer for endpoint 0 TX data is not empty and an endpoint 0 TX interrupt occurs signal...

Page 909: ...ll the command Is LH initiated stall and can remove halt condition Set CTRL Clr_Halt bit to 1 Application specific action to resolve stall No Yes Yes Yes No If control write data stage OUT transactions on EP0 is out of control write data stage and control read status stage are automatically stalled by the core Yes wlength_count is 0 OUT transactions with more bytes than expected are automatically ...

Page 910: ...uest is clear endpoint feature set config or set interface Set halt for relevant endpoints if request is set endpoint feature set config or set interface Set SYSCON2 Dev_Cfg if request is valid set config and device is addressed Set SYSCON2 Clr_Cfg if request is valid set config with config_nb of 0 and device is configured Set SYSCON1 Self_Pwr if request is set config and device is self powered in...

Page 911: ...s on EP0 is out of control read data stage or control write status stage are automatically stalled by the core Yes No Must be STAT_FLG STALL Flush data from EPO application s TX buffer based on amount previously put into TX FIFO Write non ISO TX data Write EP_NUM register EP_NUM EP_Num 0 EP_NUM EP_Dir 1 EP_NUM EP_Sel 1 EP_NUM Setup_Sel 0 Write EP_NUM register EP_NUM EP_Num 0 EP_NUM EP_Dir 1 EP_NUM...

Page 912: ...ons to determine control read action and status result Set CTRL Clr_EP to 1 then set CTRL Set_FIFO_En to 1 Want to respond with ACK No Want to respond with stall Set SYSCON2 Stall_Cmd to 1 Yes Enable NAK interrupt by setting SYSCON1 Nak_En to 1 if not already enabled No Write EP_NUM register EP_NUM EP_Num 0 EP_NUM EP_Dir 0 EP_NUM EP_Sel 1 EP_NUM Setup_Sel 0 Write EP_NUM register EP_NUM EP_Num 0 EP...

Page 913: ...e USB powered and reset Addressed The device is attached to the USB powered reset and an address has been assigned The device moves into the addressed state after a SET_ADDRESS request with an address number different of 0 Configured The device is attached to the USB powered reset has an address different from 0 and is configured The device moves into the configured state after a valid SET_CONFIGU...

Page 914: ...N2 Dev_Cfg not set or SET_CONFIGURATION stalled SET_CONFIGURATION SYSCON2 Dev_Cfg set USB RESET SET_CONFIGURATION SYSCON2 Dev_Cfg set SET_ADDRESS 0 or USB RESET Behavior not specified by USB 1 1 specifications see chapter 9 USB reset generates two interrupts when USB reset is asserted and then when USB reset completes No interrupt is asserted by the core for tansitions shown with dashed lines Remo...

Page 915: ...fic Action to Handle Configured State to Addressed State Transition Application Specific Action to Handle Addressed State to Configured State Transition Application Specific Action to Handle Configured State to Default State Transition DEVSTAT ADD changed Action Specific Action to Handle Default State to Addressed State Transition Application Specific Action to Handle Addressed State to Default St...

Page 916: ...into deep sleep or to initialize any application specific informa tion relating to the USB device Figure 13 23 Attached Unattached Handler Yes End of attached unattached handler Attached unattached handler DEVSTAT ATT No The device can now be put in deep sleep LH clock can be shutoff Inform application that the device has been connected to a USB host or hub Inform application that the device has b...

Page 917: ...hardware is implemented to trigger only after 5 ms of bus IDLE This forces compliance with the USB Spec Version 1 1 tWTRSM timing parameter 3 ms of IDLE to identify suspend 2 ms before remote device can signal resume If the local host wants to wake the device from suspend mode and remote wakeup enable is set bit R_WK_OK 1 it must first turn its clock on if stopped then set the Rmt_Wkp The device t...

Page 918: ...fic actions to mark all endpoints unhalted Application specific actions to mark device as not in suspend mode Application specific actions to clear app s Config Alt I F s Application specific actions to mark device as not remote wake enabled Application specific actions to clear local copy of frame number USB_Reset 1 Yes Inform application that the USB reset has completed and that device is in def...

Page 919: ... to mark all endpoints un halted Application specific actions to mark device as not in suspend mode Application specific actions to clear app s Config Alt I F s Application specific actions to mark device as not remote wake enabled Application specific actions to clear local copy of frame number USB_Reset 1 Yes Inform application that the USB reset has completed and that device is in default state...

Page 920: ...B Interrupt Handler Suspend resume handler Inform application that entering suspend DEVSTAT SUS No Yes Inform application of resume End of suspend resume handler Is remote wake up supported Is low power mode supported Set IRQ_SRC DS to clear the IT device is _Chg 1 Set IRQ_SRC DS to clear the IT _Chg 1 Read DEVSTAT R_Wk_ OK value 1 ...

Page 921: ...P_Num endp_nb EP_NUM EP_Dir 0 EP_NUM EP_Sel 1 EP_NUM Setup_Sel 0 Yes Write EP_NUM register EP_NUM EP_Num endp_nb EP_NUM EP_Dir 0 EP_NUM EP_Sel 0 EP_NUM Setup_Sel 0 Read endp_nb value from EPN_STAT EPn_TX_IT_src Write EP_NUM register EP_NUM EP_Num endp_nb EP_NUM EP_Dir 1 EP_NUM EP_Sel 1 EP_NUM Setup_Sel 0 RX handler Write EP_NUM register EP_NUM EP_Num endp_nb EP_NUM EP_Dir 1 EP_NUM EP_Sel 0 EP_NUM ...

Page 922: ...r Figure 13 30 shows the operations necessary to handle non isochronous non control IN endpoint specific transmit interrupts This flowchart shows two TX transaction handshaking interrupts There is a third interrupt handshaking possibility when NAK interrupts are enabled which is not depicted here Depending on the application specific actions needed for various endpoints in the real system it is po...

Page 923: ... preparation to receive endpoint data End of non ISO RX handler Yes Yes No Must be STAT_FLG STALL Set RXCON1 Clr_Halt remove halt conditions LH initiated stall and can remove stall Yes No Application specific actions to resolve stall No ACK 1 and flag FIFO not full and DB 0 to 1 Note If flag FIFO not full and DB Caution the core responds to is set to 1 Set_FIFO_En must be set later after EP is des...

Page 924: ...e application s RX buffer counter End of read non ISO RX FIFO data STAT_FLG non_ISO FIFO _Empty 1 Yes No A A Yes Inform application of completion of endpoint s RX transaction STAT_FLG Non_ISO_FIFO _Full 1 Set RXbyte counter to EP buffer size Yes Read received bytes count in RXFSTAT RXF_Count Set RXbyte counter to RXF_Count value No No EPn_RX EPn_RX_ Size or DB 1 Set FIFO not full and DB to 1 Yes N...

Page 925: ...dler No Yes No Must be STAT_FLG STALL Set CTRL Cir_Halt remove halt condition LH initiated stall and can remove stall Yes No Application specific actions to remove stall Retire the data that was just sent to the USB host from the application s endpoint TX buffer Yes TX data that was previously placed in the endpoint s TX FIFO remains in the application s buffer until that data is properly sent to ...

Page 926: ...o Set loop count to endpoint s current configured length The TX data copied from the application s TX buffer is not retired from the buffer until it is correctly received by the USB host The loop count must be set to 0 for sending an empty data packet In transaction with ACK The count saved here is used at that time to retire the correct amount of TX buffer data If double buffer is used two packet...

Page 927: ..._Sel 0 Write EP_NUM register EP_NUM EP_Num n EP_NUM EP_Dir 0 EP_NUM EP_Sel 0 EP_NUM Setup_Sel 0 Another ISO RX endpoint configured EPn Yes No Any ISO TX endpoint configured EPn Write EP_NUM register EP_NUM EP_Num n EP_NUM EP_Dir 1 EP_NUM EP_Sel 1 EP_NUM Setup_Sel 0 ISO TX handler Write EP_NUM register EP_NUM EP_Num n EP_NUM EP_Dir 1 EP_NUM EP_Sel 0 EP_NUM Setup_Sel 0 Another ISO TX endpoint config...

Page 928: ...X byte count decrement loop count Update application s RX buffer count Yes End of RX ISO Handler Loop_count RXFSTAT RXF_Count STAT_FLG Data_Flush 1 Application specific actions to handle case for data flush No Yes STAT_FLG ISO_Error 1 Application specific actions to handle unrecovered ISO packet Yes No STAT_FLG ISO_FIFO_Empty 1 Application specific actions to handle empty ISO packet or no packet Y...

Page 929: ...ation s TX buffer count Yes End of TX ISO handler STAT_FLG Miss_In 1 Yes No Wish to resend missed data Yes Set CTRL Cir_EP to clear the current FIFO No Set Loop_count to TX ISO packet length max is endpoint size When a Missed_in occurs missed data are from TWO frames previous Application specific actions to handle missed in data Reload TX byte count Must put missed transmit data into foreground IS...

Page 930: ...e by Endpoint Type General USB IRQs EP Specific IRQs SOF Interrupt Type Setup EP0 Control EP0 Out Control EP0 In Other Bulk or Interrupt Out Bulk or Interrupt In Isochronous SOF Transaction ACKd Transaction NAKed if enabled Transaction STALLed Setup SOF Device State Changed RX DMA EOT non_ISO RX DMA Trans Count non_ISO TX DMA Done non_ISO ...

Page 931: ...eceived OUT data must be read when a RX DMA request is active through the register DATA_DMA The RX FIFO accessed is that of the endpoint for which DMA request is active only one RX DMA request active at a time 13 7 2 Non Isochronous OUT USB HOST LH DMA Transactions During non isochronous transfers to a DMA operated OUT endpoint a re quest to the local host DMA controller is generated when data has...

Page 932: ...ion count interrupt does not disable the ongoing DMA transfer A transaction count interrupt occurs each time the number of received transactions and not bytes has reached the programmed value in the receive transaction counter for the DMA channel One transaction has a size equal to the buffer size of the selected non isochronous endpoint An RXn_Count interrupt is asserted even if RXn_Stop has been...

Page 933: ...RXn_EOT interrupt is asserted when the DMA transfer completes Set max transactions count into RXDMAn RXn_TC Optional step required only if max transactions count IT is enabled DMA_IRQ_EN RXn_Cnt_IE 1 RXDMA_CFG RXDMAn_EP LH wants to be interrupted with EOT after a given number of transactions Nt Set RXDMAn RXn_TC to Nt 1 and set RXDMAn RXn_Stop to 1 Yes No Endpoints assigned to a DMA channel must h...

Page 934: ...pplication The LH must renable End of Non ISO RX DMA EOT handler Read DMAN_STAT Read endpoint number IRQ_SRC RXn_EOT 1 the endpoint to allow next transfer in DMAN_STAT DMAn_RX_IT_src register DMAn_RX_SB register to be informed of an odd number of bytes for last transaction that the RX DMA transfer on channel n is completed to clear the IT ...

Page 935: ...er Non ISO RX DMA count handler End of Non ISO RX DMA count handler Set IRQ_SRC RXn_Cnt 1 to clear the IT Inform the application that Read channel number n in DMAN_STAT DMAn_RX_IT_src register the RX DMA transfer on channel n has sent RXDMAn RXn_TC transaction count without detecting an EOT ...

Page 936: ... 4 Host message FIFO content System DMA read Dma_request 1 2 2 3 3 4 4 Error 6 6 6 Figure 13 40 Isochronous RX DMA Start Routine ISO RXDMA 0 1 2 start routine Assign ISO endpoint number to DMA channel n End of ISO RXDMA 0 1 2 start routine If no interrupt is signaled to the LH except SOF if enabled the Device DMA sends a new DMA request to the LH DMA controller every frame till the HOST stops send...

Page 937: ...he following manner The transfer size counter TXn_TSC corre sponds to either the number of bytes to transmit EOT bit set or the number of buffers to transmit EOT bit cleared The buffer size corresponds to the programmed size of the TX endpoint A request to the local host main DMA controller is generated when the end point buffer is empty initially after that the START bit is set and then each time...

Page 938: ...er of any size It also effectively starts the initial DMA transfer The completion of this DMA task is signaled to local host via a DONE interrupt as depicted in Figure 13 43 The start routine and the associated interrupt handler are tightly coupled An example would be 100603 bytes to transfer via 32 bytes IN bulk endpoint which gives XSWL 0x3 FBT 0x47 EOTB 0x1b In this example five passes of DMA t...

Page 939: ...n to initialize the main system DMA controller LH DMA write access must point to TXDCHn TXDATn in response to DMA channel n request End of non ISO TXDMA 0 1 2 start routine Start single pass DMA transfer of size FTZ bytes IRQ_SRC TXn_Done interrupt is asserted when the DMA transfer completes Start 1st pass of 2 DMA transfer of size FTBn x EP size bytes Start DMA transfer TXDMAn TXn_TSC 0 TXDMAn TX...

Page 940: ...ransfer TXDMAn TXn_TSC 0 TXDMAn TXn_EOT 0 TXDMAn TXn_Start 1 FBTn 0 Needed for next pass Start new DMA transfer of FBTn EP buffer size Needed for next pass Start new DMA transfer of EOTBn bytes could be null packet End of non ISO TX DMA handler Set IRQ_SRC TXn_Done 1 to clear the IT Read the endpoint umber n in DMAN_STAT DMAn_TX_IT_src register Initiate new DMA transfer TXDMAn TXn_TSC FBTn TXDMAn ...

Page 941: ...interrupt is signaled to the local host during DMA operation to isochronous IN endpoints 13 7 7 Important Note on DMA Requests For each direction only one DMA request can be active at any time A request must then be serviced to allow the next pending request on the same direction to be asserted In particular a TX DMA request is asserted at each start of frame if a TX DMA channel is configured for ...

Page 942: ...nitialize the main system DMA controller LH DMA write access must point to TXDCHn TXDATn in response to DMA channel n request End of ISO TXDMA 0 1 2 start routine Start DMA transfer TXDMAn _TSC FTZ TXDMAn TXn_EOT 1 TXDMAn TXn_Start 1 If no interrupt is signaled to the LH except SOF if enabled the Device DMA sends a new request to the LH DMA controller every frame EOT bit is don t care for ISO endp...

Page 943: ... been handled and the TX data has been sent through an IN transaction both buffers in case of double buffer ing with both buffers full No TX_Done interrupt is asserted even if TSC bit value is 0 after the transaction If TX DMA request is inactive when the endpoint is unselected deconfi guration is effective when all data available in TX buffer s have been sent through IN transaction s If TXDMAn_TS...

Page 944: ...t in the functioning of the device state These signals are PUEN_O Pullup enable signal which always reflects the Pullup_En register bit SHUTOFF_O Power circuitry shutoff signal controlled by the core and the SOFF_Dis bit DS_WAKE_REQ_ON Deep sleep wake request asserted low when interface clock is needed SUSPEND_O Suspend signal asserted high when the device is in suspend mode ...

Page 945: ... 1 DS_WAKE_REQ_ON 0 LH sets SYSCON1 Pullup_En USB cable inserted Power on PUEN_O 1 SUSPEND_O 1 SHUTOFF_O 1 DS_WAKE_REQ_ON 0 LH sets SYSCON1 Pullup_En USB cable inserted PUEN_O 1 SUSPEND_O 0 SHUTOFF_O 0 DS_WAKE_REQ_ON 0 USB reset PUEN_O 1 SUSPEND_O 1 SHUTOFF_O 1 DS_WAKE_REQ_ON 1 after DS_Chg interrupt handling Idle for more Reset or resume SHUTOFF_O value is 0 if the LH has set SYSCON1 SOFF_D bit S...

Page 946: ...oller Interface Functionality 14 5 14 3 USB Host Controller Registers 14 8 14 4 USB Host Controller Interrupt Sources 14 46 14 5 USB Pin Multiplexing 14 48 14 6 USB Host Controller Access to System Memory 14 81 14 7 OMAP5910 Local Bus 14 93 14 8 OMAP5910 Local Bus MMU 14 101 14 9 USB Host Controller Reset and Clock Control 14 115 14 10 OMAP5910 USB Hardware Considerations 14 118 Chapter 14 ...

Page 947: ... OMAP5910 USB host controller accesses these data structures without direct intervention by the processor using the OMAP5910 s local bus These data structures and data buffers can be located in internal or external system RAM The local bus MMU allows the USB host controller to access the full address range of internal and external memories The OMAP5910 USB host controller is connected to the OMAP5...

Page 948: ... 16 16 32 16 32 32 32 32 32 32 16 MPU privatePeripherals bus DSP public shared pheripheral bus 32 MPU public 16 DSP DSP public peripherals McBSP1 McBSP3 MPU public peripherals USB Host I F JTAG emulation I F OSC 12 MHz Clock OSC OMAP5910 ETM9 Timers 3 MPU DSP shared peripherals Mailbox MPU private peripherals Timers 3 16 Memory interface Reset External clock MPU Bus 32 kHz 1 5M bits traffic contro...

Page 949: ...sciever USB transceiver ESD protection MPU s MMU OHCI controller OMAP5910 USB connector ESD protection USB transceiver ESD protection Internal memory External memory USB function controller USB power switching GPIO Memory controller Local bus controller LB s MMU MPU public peripheral bus Top level pin Signals to from other peripherals INTH2 UART 1 Peripheral multiplexing USB connector USB connecto...

Page 950: ...information presented in the OHCI Specification for USB or the USB Specification OMAP5910 USB host control ler users can refer to the USB Specification and the OHCI Specification for USB for detailed discussions of USB requirements and OHCI controller operation 14 2 2 OMAP5910 USB Host Controller Differences from OHCI Specification for USB The OMAP5910 USB host controller implementation does not i...

Page 951: ... register or top level pin multiplexing settings When the CONF_MOD_USB_HOST_HMC_MODE_R field setting of the MOD_CONF_CTRL_0 register disables a USB host controller port the USB host controller sees that port as unattached When OMAP5910 top level pin multiplexing configures a pin for functionality other than the USB the USB host controller is disconnected from that pin and that pin does not affect ...

Page 952: ...r ED List Head Pointers The OHCI Specification for USB provides a specific sequence of operations for the host controller driver to perform when setting up the host controller Failure to follow that sequence can result in malfunction As a specific example the HcControlHeadED and HCBulkHeadED pointer registers and the 32 HccaInterruptTable pointers must all point to valid local bus addresses of val...

Page 953: ...R 32 FFFB A000h HcControl HC operating mode R W 32 FFFB A004h HcCommandStatus HC command and status R W 32 FFFB A008h HcInterruptStatus HC interrupt status R W 32 FFFB A00Ch HcInterruptEnable HC interrupt enable R W 32 FFFB A010h HcInterruptDisable HC interrupt disable R 32 FFFB A014h HcHCCA Local bus virtual address of HCCA R W 32 FFFB A018h HcPeriodCurrentED Local bus virtual address of current ...

Page 954: ... 1 control and status R R W 32 FFFB A054h HcRhPortStatus2 HC port 2 control and status R R W 32 FFFB A058h HcRhPortStatus3 HC port 3 control and status R R W 32 FFFBA05Ch Reserved Reserved None FFFB A060h to FFFB A0DFh HostUEAddr Host UE address R 32 FFFB A0E0h HostUEStatus Host UE status R 32 FFFB A0E4h HostTimeoutCtrl Host timeout control R W 32 FFFB A0E8h HostRevision Host revision R 32 FFFB A0...

Page 955: ...the operating mode of the USB host controller Table 14 3 HC Operating Mode Register HcControl Bit Name Value Description Type Reset Value 31 11 Reserved Reserved 10 RWE Remote wake up enable This bit has no effect in OMAP5910 The OMAP5910 USB host controller does not provide a processor wake up mechanism R W 0 9 RWC Remote wake up connected This bit has no effect in OMAP5910 The OMAP5910 USB host ...

Page 956: ...ext 1 ms frame Host controller driver can modify the list If driver removes the ED pointed to by the HcBulkCurrentED from the ED list it must update HcBulk CurrentED to point to an ED still on the list before it reenables the bulk list 1 Enables processing of bulk ED List HcBulkHeadED must be 0 or point to a valid ED before setting this bit HcBulkCurrentED must point to a valid ED or be 0 before s...

Page 957: ...ronous EDs might not occur in the current frame but is enabled in the next frame 2 PLE Periodic list enable R W 0 0 The periodic ED lists are not processed When written to 0 periodic list processing is disabled beginning with the next frame 1 Enables processing of the periodic ED lists When written to 1 periodic list processing begins in the next frame 1 0 CBSR Control bulk service ratio Specifies...

Page 958: ... modifies the bulk list to include new TDs If HcBulkCurrentED is 0 the USB host controller does not begin processing bulk list EDs unless this bit is set When the USB host controller sees this bit set and begins processing the bulk list it clears this bit R W 0 1 CLF Control list filled The host controller driver must set this bit if it modifies the control list to include new TDs If HcControlHead...

Page 959: ...d Write of 0 has no effect Write of 1 clears this bit R W 0 5 FNO Frame number overflow When 1 indicates a frame number overflow has occurred Write of 0 has no effect Write of 1 clears this bit R W 0 4 UE Unrecoverable error When 1 indicates that an unrecoverable error has occurred on the local bus or that an isochronous TD PSW field condition code was not set to Not Accessed when the USB host con...

Page 960: ...indicates that a scheduling overrun has occurred Write of 0 has no effect Write of 1 clears this bit R W 0 The HC interrupt enable register enables various OHCI interrupt sources to generate interrupts to the OMAP5910 level 2 interrupt handler Table 14 6 HC Interrupt Enable Register HcInterruptEnable Bit Name Description Type Reset Value 31 MIE Master interrupt enable When 1 allows other enabled O...

Page 961: ...he OMAP5910 level 2 interrupt controller When 0 or when MIE is 0 frame number overflow interrupts do not propagate A write of 0 has no effect on this bit A write of 1 sets this bit R W 0 4 UE Unrecoverable error When 1 and MIE is 1 allows unrecoverable error interrupts to propagate to the OMAP5910 level 2 interrupt controller When 0 or when MIE is 0 unrecoverable error interrupts do not propagate ...

Page 962: ...this bit A write of 1 sets this bit R W 0 1 WDH Write done head When 1 and MIE is 1 allows write done head interrupts to propagate to the OMAP5910 level 2 interrupt controller When 0 or when MIE is 0 write done head interrupts do not propagate A write of 0 has no effect on this bit A write of 1 sets this bit R W 0 0 SO Scheduling overrun When 1 and MIE is 1 allows scheduling overrun interrupts to ...

Page 963: ...eserved 6 RHSC Root hub status change Read always returns 0 Write of 0 has no effect Write of 1 clears the HcInterruptEnable RHSC bit R W 0 5 FNO Frame number overflow Read always returns 0 Write of 0 has no effect Write of 1 clears the HcInterruptEnable FNO bit R W 0 4 UE Unrecoverable error Read always returns 0 Write of 0 has no effect Write of 1 clears the HcInterruptEnable UE bit R W 0 3 RD R...

Page 964: ...eset Value 31 8 HCCA See Section 14 6 1 Local Bus Addressing for the restrictions on local bus virtual addresses R W 0 7 0 Reserved Reserved R 0 The HC current periodic register defines the local bus virtual address of the next endpoint descriptor ED on the periodic ED List Table 14 9 HC Current Periodic Register HcPeriodCurrentED Bit Name Description Type Reset Value 31 4 PCED Local bus virtual a...

Page 965: ...d R 0x0 The HC current control register defines the local bus virtual address of the next ED on the control ED list Table 14 11 HC Current Control Register HcControlCurrentED Bit Name Description Type Reset Value 31 4 CCED Local bus virtual address of current ED on the control ED list This field represents bits 31 4 of the local bus virtual address of the next ED on the control ED list EDs are ass...

Page 966: ...eserved Reserved R 0x0 The HC current bulk register defines the local bus virtual address of the next ED on the bulk ED list Table 14 13 HC Current Bulk Register HcBulkCurrentED Bit Name Description Type Reset Value 31 4 BCED Local bus virtual address of current ED on the bulk ED list This field represents bits 31 4 of the local bus virtual address of the next ED on the bulk ED list EDs are assume...

Page 967: ...hat there are no TDs on the done queue This register is automatically updated by the USB host controller R 0x0000000 3 0 Reserved Reserved R 0x0 The HC frame interval register defines the number of 12 MHz clock pulses in each USB frame Table 14 15 HC Frame Interval Register HcFmInterval Bit Name Description Type Reset Value 31 FIT Frame interval toggle The host controller driver must toggle this b...

Page 968: ...t times remaining in the current frame This field is automatically reloaded with the frame interval field value at the beginning of every frame R 0 The HC frame number register reports the current USB frame number Table 14 17 HC Frame Number Register HcFmNumber Bit Name Description Type Reset Value 31 16 Reserved Reserved 15 0 FN Frame number This field reports the current USB frame number It is i...

Page 969: ... frame R W 0 The HC low speed threshold register defines the latest time in a frame that the USB host controller can begin a low speed packet Table 14 19 HC Low Speed Threshold Register HcLSThreshold Bit Name Description Type Reset Value 31 14 Reserved Reserved 13 0 LST Low speed threshold This field defines the number of full speed bit times in the frame after which the USB host controller may no...

Page 970: ...pecific and must be calculated based on the amount of time the VBUS supply takes to provide valid VBUS to a worst case downstream USB function controller The implementation specific value must be computed and then written to this register before the USB host controller driver is initialized Because OMAP5910 does not provide a direct control from the USB host controller to switch VBUS on and off th...

Page 971: ...ler to control external VBUS switching this bit defaults to 1 8 PSM Power switching mode R W 0 0 Indicates that all ports are powered at the same time 1 Indicates that individual port power switching is supported Because OMAP5910 does not provide signals from the USB host controller to control external VBUS switching this bit defaults to 0 7 0 NDP Number of downstream ports This register defaults ...

Page 972: ... for downstream port 2 PPCM bit 3 is the port power control mask for downstream port 3 PPCM bits 4 through 15 are reserved OMAP5910 does not provide connections from the USB host controller to pins to provide external port power switching Systems that implement port power switching must use other mechanisms to control port power R W 0x0000 15 0 DR Device removable Each bit defines whether a corres...

Page 973: ...e root hub does not support the local power status feature Write of 0 has no effect Write of 1 sets the PortPowerStatus bits for all ports if PowerSwitchingMode is 0 A write of 1 sets PortPowerStatus bits for ports with their corresponding PortPowerControlMask bits cleared if PowerSwitchingMode is 1 R W 0 15 DRWE Device remote wake up enable When 1 this bit enables a ConnectStatusChange event to b...

Page 974: ... provide signals for external hardware to report overcurrent status to the USB host controller this bit is always 0 R 0 0 LPS Local power status The root hub does not support the local power status feature This bit always reads as 0 Write of 0 has no effect Write of 1 when in global power mode power switching mode 0 turns off power to all ports If in per port power mode power switching mode 1 a wr...

Page 975: ...Port 1 overcurrent indicator change This bit indicates when 1 that the port 1 port overcurrent indicator has changed Write of 0 has no effect Write of 1 clears this bit The OMAP5910 does not provide inputs for signaling external overcurrent indication to the USB host controller Overcurrent monitoring if required must be handled through some other mechanism R W 0 18 PSSC Port 1 suspend status chang...

Page 976: ...rt 1 A 0 in this bit indicates a full speed device This bit is only valid when port 1 CurrentConnectStatus is 1 The host controller driver can write a 1 to this bit to clear the port 1 PortPowerStatus A write of 0 to this bit has no effect OMAP5910 USB host controller does not control external port power using OHCI mechanisms so if required USB host port power must be controlled through other mean...

Page 977: ...n to the USB host controller Overcurrent monitoring if required must be handled through some other mechanism A write of 1 to this bit when port 1 port suspend status is 1 causes resume signaling on port 1 A write of 1 when port 1 port suspend status is 0 has no effect A write of 0 has no effect R W 0 2 PSS SPS Port 1 port suspend status set port suspend When read as 1 indicates that port 1 is in t...

Page 978: ...f a USB suspend if the port was not enabled when the USB resume completed A write of 1 to this bit when port 1 CurrentConnectStatus is 1 sets the port 1 port enable status bit A write of 1 when port 1 current connect status is 0 has no effect A write of 0 has no effect R W 0 0 CCS CPE Port 1 current connection status clear port enable When read as 1 indicates that port 1 currently has a USB device...

Page 979: ...effect R W 0 19 OCIC Port 2 overcurrent indicator change This bit indicates when 1 that the port 2 port overcurrent indicator has changed A write of 1 clears this bit A write of 0 has no effect The OMAP5910 does not provide inputs for signaling external overcurrent indication to the USB host controller Overcurrent monitoring if required must be handled through some other mechanism R W 0 18 PSSC Po...

Page 980: ... 2 A 0 in this bit indicates a full speed device This bit is only valid when port 2 CurrentConnectStatus is 1 The host controller driver can write a 1 to this bit to clear the port 2 PortPowerStatus A write of 0 to this bit has no effect The OMAP5910 USB host controller does not control external port power using OHCI mechanisms so if required USB host port power must be controlled through other me...

Page 981: ...ation to the USB host controller Overcurrent monitoring if required must be handled through some other mechanism A write of 1 to this bit when port 2 port suspend status is 1 causes resume signaling on port 2 A write of 1 when port 2 port suspend status is 0 has no effect A write of 0 has no effect R W 0 2 PSS SPS Port 2 port suspend status set port suspend When read as 1 indicates that port 2 is ...

Page 982: ...f a USB suspend if the port was not enabled when the USB resume completed A write of 1 to this bit when port 2 CurrentConnectStatus is 1 sets the port 2 port enable status bit A write of 1 when port 2 current connect status is 0 has no effect A write of 0 has no effect R W 0 0 CCS CPE Port 2 current connection status clear port enable When read as 1 indicates that port 2 currently has a USB device...

Page 983: ...t R W 0 19 OCIC Port 3 overcurrent indicator change This bit indicates when 1 that the port 3 port overcurrent indicator has changed A write of 1 clears this bit A write of 0 has no effect The OMAP5910 does not provide inputs for signaling external overcurrent indication to the USB host controller Overcurrent monitoring if required must be handled through some other mechanism R W 0 18 PSSC Port 3 ...

Page 984: ...ort 3 A 0 in this bit indicates a full speed device This bit is only valid when port 3 CurrentConnectStatus is 1 The host controller driver may write a 1 to this bit to clear the port 3 PortPowerStatus A write of 0 to this bit has no effect OMAP5910 USB host controller does not control external port power using OHCI mechanisms so if required USB host port power must be controlled through other mea...

Page 985: ...ation to the USB host controller Overcurrent monitoring if required must be handled through some other mechanism A write of 1 to this bit when port 3 port suspend status is 1 causes resume signaling on port 3 A write of 1 when port 3 port suspend status is 0 has no effect A write of 0 has no effect R W 0 2 PSS SPS Port 3 port suspend status set port suspend When read as 1 indicates that port 3 is ...

Page 986: ...f a USB suspend if the port was not enabled when the USB resume completed A write of 1 to this bit when port 3 CurrentConnectStatus is 1 sets the port 3 port enable status bit A write of 1 when port 3 current connect status is 0 has no effect A write of 0 has no effect R W 0 0 CCS CPE Port 3 current connection status clear port enable When read as 1 indicates that port 3 currently has a USB device...

Page 987: ...pecification Table 14 26 Host UE Address Register HostUEAddr Bit Name Description Type Reset Value 31 0 UE_ADDR Unrecoverable error address This register captures the local bus virtual address of any local bus operation that is started by the USB host controller that encounters an unrecoverable error condition This information along with the information in HostUEStatus can help a developer determi...

Page 988: ...tUEStatus Bit Name Description Type Reset Value 31 1 Reserved Reserved R xxxxxxxx 0 UEAccess Access type when unrecoverable error occurred When an unrecoverable error occurs due to timeout of a local bus write this bit is set When an unrecoverable error occurs due to timeout of a local bus read this bit is cleared This bit has no meaning before an unrecoverable error occurs This information along ...

Page 989: ...a local bus access to system memory If the local bus cycle does not complete in that time the USB host controller signals an unrecoverable error This bit has no effect on MPU DSP or DMA controller accesses to local bus slave peripherals R W 0 The host revision register returns the revision number for the OMAP5910 USB host controller This register is not defined by the OHCI specification Table 14 2...

Page 990: ...tware must access the USB data structures and USB data buffers in system memory See Section 14 6 5 Endianism and USB Host Controller Access to System Memory for details on endianism data buffers and data structures 14 3 3 USB Host Controller Registers USB Reset and USB Clocking When the USB host controller is not clocked because the MOD_CONF_CTRL_0 register CONF_MOD_USB_HOST_HHC_UHOST_EN _R bit is...

Page 991: ...I Specification for USB 14 4 1 4 OHCI Resume Detect Interrupt The OHCI resume detect interrupt is supported as described in the OHCI Specification for USB 14 4 1 5 OHCI Unrecoverable Error Interrupt The OHCI unrecoverable error interrupt is supported as described in the OHCI Specification for USB This interrupt occurs if the USB host controller is unable to complete a local bus read or local bus w...

Page 992: ...nership change interrupt is not supported 14 4 2 Local Bus MMU Interrupts Interrupts from the local bus MMU to the MPU level 1 interrupt handler IRQ_17 input occur if the USB host controller attempts an access which the local bus MMU cannot perform This interrupt can be an important tool when debugging a USB host controller driver and can be used to help identify operational faults in a final prod...

Page 993: ...t provides a USB host controller must implement certain features These features include a USB type A receptacle power on the VBUS signal may be switched or unswitched power transient suppression pulldown resistors and USB compatible downstream port transceiver These elements are shown in Figure 14 3 Figure 14 3 Typical USB Host Connections USB transceiver VBUS control USB type A receptacle Transie...

Page 994: ...hat connect to the USB host controller overcurrent status bits so some other mechanism must be used if overcurrent sensing is required 14 5 2 USB Function Controller Connectivity With USB Transceivers To provide a robust USB solution a system that provides a USB function con troller must implement certain features These features include a USB type B receptacle VBUS power detection transient suppre...

Page 995: ...h the pullup resistor must be connected to the D signal to indicate implementation of a full speed USB device 14 5 3 On Board Transceiverless Connection Using OMAP5910 Transceiverless Link Logic The transceiverless link logic feature of the OMAP5910 USB signal multiplex ing enables connection of the OMAP5910 device to an external on board USB host controller or external on board USB function contr...

Page 996: ... transmit control signals from the external USB integrated circuit and similar signals from the OMAP5910 USB host controller or OMAP5910 USB function controller and computes the equivalent USB differential pair state The com puted differential pair state is interpreted and the appropriate transceiver out put signals are provided to the external USB integrated circuit and to the OMAP5910 USB host c...

Page 997: ...ns are listed in Table 14 30 and are shown in Figure 14 7 through Figure 14 31 Each of these figures shows the external connectivity used to implement a typical system using one of the USB signal multiplexing modes Each diagram assumes that OMAP5910 top level signal multiplexing has been initialized to select the USB signal multiplexer as the source destination for those signals shown as actively ...

Page 998: ...LL 10 USB host port 1 UART 1 USB host port 3 with TLL 11 USB host port 1 USB function USB host port 3 with TLL 12 USB function USB host port 2 USB host port 3 with TLL 13 USB host port 1 USB host port 3 with TLL 14 USB function USB host port 3 with TLL 15 USB host port 1 USB host port 2 USB host port 3 with TLL 16 USB host port 1 CONF_MOD_USB_HOST_HMC_MODE_R values that select UART 1 bring UART1 C...

Page 999: ...ng 24 USB host port 1 UART 1 USB host port 3 with TLL TXD signaling 25 USB host port 1 USB function USB host port 3 with TLL TXD signaling 26 31 CONF_MOD_USB_HOST_HMC_MODE_R values that select UART 1 bring UART1 CTS RX and TX signals to pins that can in other CONF_MOD_USB_HOST_HMC_MODE_R values be used for USB CONF_MOD_USB_HOST_HMC_MODE_R 7 provides an internal signal path from six of the USB rela...

Page 1000: ... SYNC USB1 VP MCSI1 CLK USB1 VM MCSI1 DIN USB1 RCV USB host controller Host port 1 Host port 2 Host port 3 USB function controller UART 1 USB singal multiplexing TLL OMAP5910 HMC_MODE 0 GPIO00 USB VBUS USB PUEN USB transceiver MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM UART2 CTS USB2 RCV Top Level Pin Multiplexing Assumes pins h...

Page 1001: ...ontrol USB type A receptacle Transient suppressor USB transceiver USB type A receptacle Transient suppressor CLK32K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1_SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUT USB1 TXD MCSI1 SYNC USB1 VP MCSI1 CLK USB1 VM MCSI1 DIN USB1 RCV MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM UART2 CTS USB2 RC...

Page 1002: ... type A receptacle Serial transceiver Serial device Transient suppressor Transient suppressor USB function CLK3 2K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUTUART1_TX MCSI1 SYNC USB1 VP MCSI1 CLK UART1_RX MCSI1 DIN UART1_CTS MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM UART2 CTS USB2 RC...

Page 1003: ...GPIO00 USB VBUSI USB PUEN USB transceiver VBUS control USB type B receptacle USB transceiver USB type A receptacle Level translator Transient suppressor CLK32K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUT USB1 TXD MCSI1 SYNC USB1 VP MCSI1 CLK USB1 VM MCSI1 DIN USB1 RCV MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DI...

Page 1004: ...B receptacle GPIO00 USB VBUSI USB PUEN USB transceiver VBUS control USB type A receptacle USB transceiver USB type A receptacle Level translator Transient suppressor CLK32K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUT USB1 TXD MCSI1 SYNC USB1 VP MCSI1 CLK USB1 VM MCSI1 DIN USB1 RCV MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2...

Page 1005: ...SB transceiver USB type A receptaclle Transient suppressor Transient suppresor CLK3 2K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUTUART1_TX MCSI1 SYNC USB1 VP MCSI1 CLK UART1_RX MCSI1 DIN UART1_CTS MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM UART2 CTS USB2 RCV Top level pin multipexing ...

Page 1006: ...US control USB transceiver USB type A receptaclle Transient suppressor Transient suppressor CLK3 2K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUTUART1_TX MCSI1 SYNC USB1 VP MCSI1 CLK UART1_RX MCSI1 DIN UART1_CTS MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM UART2 CTS USB2 RCV Top level pin...

Page 1007: ...USB transceiver VBUS control Transient suppressor CLK32K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUT USB1 TXD MCSI1 SYNC USB1 VP MCSI1 CLK USB1 VM MCSI1 DIN USB1 RCV MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM UART2 CTS USB2 RCV Top level pin multiplexing Assumes pins have configured f...

Page 1008: ...sceiver VP RCV VM TXSE0 TXD TXEN USB transceiver Host port 2 USB type A receptacle Transient suppressor Transient suppressor CLK32K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUT USB1 TXD MCSI1 SYNC USB1 VP MCSI1 CLK USB1 VM MCSI1 DIN USB1 RCV MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM U...

Page 1009: ... TXD TXEN Host port 2 UART 1 Serial transceiver Serial device Transient suppressor On board without CLK3 2K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUTUART1_TX MCSI1 SYNC USB1 VP MCSI1 CLK UART1_RX MCSI1 DIN UART1_CTS MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM UART2 CTS USB2 RCV Top l...

Page 1010: ...sceiver VP RCV VM TXSE0 TXD TXEN USB transceiver Host port 2 USB type B receptacle Transient suppressor Transient suppressor CLK32K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUT USB1 TXD MCSI1 SYNC USB1 VP MCSI1 CLK USB1 VM MCSI1 DIN USB1 RCV MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM U...

Page 1011: ...SB function controller USB type B receptacle Transient suppressor Level translator Transient suppressor On board without CLK32K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUT USB1 TXD MCSI1 SYNC USB1 VP MCSI1 CLK USB1 VM MCSI1 DIN USB1 RCV MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM UART2...

Page 1012: ...B host transceiver VP RCV VM TXSE0 TXD TXEN Host port 2 Transient suppressor On board without CLK3 2K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUTUART1_TX MCSI1 SYNC USB1 VP MCSI1 CLK UART1_RX MCSI1 DIN UART1_CTS MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM UART2 CTS USB2 RCV Top level p...

Page 1013: ...eiver VP RCV VM TXSE0 TXD TXEN Host port 2 Transient suppressor On board without CLK3 2K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUTUART1_TX MCSI1 SYNC USB1 VP MCSI1 CLK UART1_RX MCSI1 DIN UART1_CTS MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM UART2 CTS USB2 RCV Top level pin multiplexi...

Page 1014: ... TXSE0 TXD TXEN Host port 2 USB transceiver USB type A receptacle Transient suppressor Transient suppressor On board without CLK32K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUT USB1 TXD MCSI1 SYNC USB1 VP MCSI1 CLK USB1 VM MCSI1 DIN USB1 RCV MCSI2 CLK USB2_SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM U...

Page 1015: ... TLL USB function controller Transient suppressor CLK3 2K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUT USB1 TXD MCSI1 SYNC USB1 VP MCSI1 CLK USB1 VM MCSI1 DIN USB1 RCV MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM UART2 CTS USB2 RCV Top level pin multiplexing Assumes pins have configured ...

Page 1016: ... USB type A receptacle TLL USB function controller Transient suppressor Transient suppressor CLK32K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUT USB1 TXD MCSI1 SYNC USB1 VP MCSI1 CLK USB1 VM MCSI1 DIN USB1 RCV MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM UART2 CTS USB2 RCV Top level pin ...

Page 1017: ...ller UART 1 Serial transceiver Serial device Transient suppressor CLK3 2K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUT UART1_TX MCSI1 SYNC USB1 VP MCSI1 CLK UART1_RX MCSI1 DIN UART1_CTS MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM UART2 CTS USB2 RCV Top level pin multiplexing Assumes pin...

Page 1018: ...L USB function controller USB transceiver USB type B receptacle Transient suppressor Level translator CLK32K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUT USB1 TXD MCSI1 SYNC USB1 VP MCSI1 CLK USB1 VM MCSI1 DIN USB1 RCV MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM UART2 CTS USB2 RCV Top l...

Page 1019: ...essor TLL GPIO00 USB VBUSI USB type B receptacle Transient suppressor Level translator CLK32K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUT USB1 TXD MCSI1 SYNC USB1 VP MCSI1 CLK USB1 VM MCSI1 DIN USB1 RCV MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM UART2 CTS USB2 RCV Top level pin multip...

Page 1020: ...ansceiver VBUS control Host port 2 TLL USB function controller CLK32K _OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUT USB1 TXD MCSI1 SYNC USB1 VP MCSI1 CLK USB1 VM MCSI1 DIN USB1 RCV MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM UART2 CTS USB2 RCV Top level pin multiplexing Assumes pins hav...

Page 1021: ... transceiver Host port 2 TLL USB function controller CLK3 2K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUT USB1 TXD MCSI1 SYNC USB1 VP MCSI1 CLK USB1 VM MCSI1 DIN USB1 RCV MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM UART2 CTS USB2 RCV Top level pin multiplexing Assumes pins have configur...

Page 1022: ...er VBUS control USB device without transceiver VP RCV VM TXD TXD TXEN USB transceiver Host port 2 USB type A receptacle Transient suppressor On board CLK32K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUT USB1 TXD MCSI1 SYNC USB1 VP MCSI1 CLK USB1 VM MCSI1 DIN USB1 RCV MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN U...

Page 1023: ...control USB device transceiver VP RCV VM TXD TXD TXEN Host port 2 UART 1 Serial transceiver Serial device On board without CLK3 2K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1TXEN MCSI1 DOUTUART1_TX MCSI1 SYNC USB1 VP MCSI1 CLK UART1_RX MCSI1 DIN UART1_CTS MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCSI2 DIN USB2 VP UART2 RX USB2 VM UA...

Page 1024: ...eiver VBUS control USB device transceiver VP RCV VM TXD TXD TXEN USB Transceiver USB type B receptacle Transient suppressor Level translator On board without CLK32K_OUT USB1 SPEED MPU_BOOT USB1 SUSP RST_HOST_OUT USB1 SE0 MCBSP3 CLKX USB1 TXEN MCSI1 DOUT USB1 TXD MCSI1 SYNC USB1 VP MCSI1 CLK USB1 VM MCSI1 DIN USB1 RCV MCSI2 CLK USB2 SUSP UART2 RTS USB2 SE0 MCSI2 DOUT USB2 TXEN UART2 TX USB2 TXD MCS...

Page 1025: ...een USB Signal Multiplexing and Top Level Multiplexing When OMAP5910 top level signal multiplexing selects non USB functionality for a pin but USB signal multiplexing is set to use that pin as an output the signal from the USB signal multiplexing is ignored and the source selected by the OMAP5910 top level signal multiplexing is used When OMAP5910 top level signal multiplexing selects non USB func...

Page 1026: ...ure 14 32 OMAP5910 USB Host Controller Data Path to System Memory USB signal multiplexing Local bus interface MPU MPU public peripheral bus interface USB host controller Peripheral Peripheral USB transceiver USB transceiver ESD protection MPU s MMU OHCI controller OMAP5910 USB connector ESD protection USB transceiver ESD protection Internal memory External memory USB function controller USB power ...

Page 1027: ... 14 33 Figure 14 33 Relationships Between Processor Virtual Address Processor Physical Address and Local Bus Virtual Address with Local Bus MMU Disabled Processor physical address Local bus virtual address Local bus MMU disabled 0x00000000 0x30000000 0x3FFFFFFF 0x2FFFFFFF 0x40000000 0xFFFFFFFF 0x00000000 0xFFFFFFFF Processor virtual address Processor MMU 0x00000000 0xFFFFFFFF 0x0FFFFFFF 0x10000000...

Page 1028: ...cal bus virtual addresses and physical addresses A system implementation that does not implement any physical RAM in the physical address range 0x00000000 to 0x0FFFFFFF must enable the local bus MMU in order to use the OMAP5910 USB host controller Initialization of the local bus MMU is done using the same sorts of operations as are used for initializing the MPU MMU except addressing the local bus ...

Page 1029: ...ller could read stale data that has not been updated by a cache writeback Similarly if the data structure is in memory that is currently in the MPU cache either writeback or writethrough mode and the OHCI controller modifies the information in physical memory the MPU can read stale data from the cache Cache coherency problems can be avoided by allocating the OHCI data struc tures HCCA EDs and TDs ...

Page 1030: ...amming pointers within the ED TD and HCCA data structures This function must understand the MPU MMU and local bus MMU program ming and local bus virtual address restrictions This routine is generally imple mented in a two step process MPU virtual address to physical address then physical address to local bus virtual address Those two steps are described in section 14 6 3 3 MPUVAtoPA MPU Virtual Ad...

Page 1031: ...nters to indicate the end of lists Some convention must be used to indicate an MPU null pointer and properly convert a local bus virtual address of 0x000000 to that MPU null pointer value 14 6 3 3 MPUVAtoPA MPU Virtual Address to Physical Address Conversion Function This function converts an MPU virtual address to the equivalent system physi cal address This function must understand the way that t...

Page 1032: ...al bus interface locks up and the USB host controller is not able to access the system memory data structures needed to issue USB packets 14 6 3 6 PAtoMPUVA Physical Address to MPU Virtual Address Conversion Function This function is a reverse version of the MPU virtual address to physical address conversion It accepts a physical address as an argument and returns the equivalent MPU virtual addres...

Page 1033: ...st TD on first ED of control list 0x00013423 The corresponding physical addresses for these OHCI structures are shown in Table 14 33 Table 14 33 Physical Addresses for Address Conversion Example OHCI Structure MPU Virtual Address Physical Address HHCA base address 0x00000700 0x0005E700 First bulk ED on the ED list 0x00000140 0x0005E140 First control ED on the ED list 0x00000150 0x0005E150 First TD...

Page 1034: ...address to physical address mapping the local bus virtual addresses in Table 14 35 are needed to program the USB host controller OHCI registers and some of the pointers in the ED and TD structures Table 14 35 Local Bus Virtual Addresses for Address Conversion Example OHCI Structure MPU Virtual Address Physical Address Local Bus Virtual Address HHCA base address 0x00000700 0x0005E700 0x30F00700 Fir...

Page 1035: ... address and places that value into the data structure pointer field For example if the USB host controller driver must add a TD to the TD list in the first bulk ED it must locate the last TD on the TD list and update it with the new TD information It must then change the NextP pointer of the last TD to point to the local bus virtual address of a newly allocated empty TD To traverse the TD list to...

Page 1036: ...inter for local bus virtual address 0x30000000 which may point to a valid location in physical system memory 14 6 5 Endianism and USB Host Controller Access to System Memory The OHCI Specification for USB defines a little endian controller Since the OMAP5910 USB host controller is OHCI compliant it is defined for use in little endian systems The OMAP5910 MPU core and subsystem are also little endi...

Page 1037: ...32 bit aligned 32 bit data value in memory as shown in Table 14 37 Table 14 37 Little Endian Data Alignment Within 32 Bit Word Bit Position Within 32 Bit Word Address Offset Data Size 31 24 23 16 15 8 7 0 0x0 1 First byte 0x0 2 Second byte First byte 0x0 3 Third byte Second byte First byte 0x0 4 Fourth byte Third byte Second byte First byte 0x1 1 First byte 0x1 2 Second byte First byte 0x1 3 Third...

Page 1038: ...f the USB host controller to access OMAP5910 system memory The remaining OMAP5910 local bus control and status registers have no direct effect because they con trol MPU DSP and DMA controller accesses to slave peripherals addressed via local bus and there are no slave peripherals on the OMAP5910 local bus The local bus memory management unit and its registers are discussed separately in section 14...

Page 1039: ... 31 8 Reserved Reserved R 0 7 0 TIMEOUT Local bus slave access time out Number of local bus clocks to wait for completion of a local bus cycle initiated by the MPU DSP or DMA before signaling a local bus abort This time out does not apply to local bus cycles initiated by the OMAP5910 USB host controller Because there are no local bus slave peripherals in the OMAP5910 device this register can be se...

Page 1040: ... timer enable Because there are no local bus slave peripherals on OMAP5910 it is recommended that this register be set to 1 to enable the HOLD timer This helps prevent lockup of the local bus R W 0 7 0 HOLD_TIMER Local bus hold timer value Because there are no local bus slave peripherals on OMAP5910 it is recommended that this register be set to a small number like 5 so that the hold timer does no...

Page 1041: ...eserved Reserved R 0 7 LB_ABORT_MASK Local bus abort interrupt mask R W 1 0 Local bus abort interrupt is enabled 1 Local bus abort interrupt is disabled When enabled and the DSP MPU or DMA controller attempts to access a local bus slave peripheral the local bus time out counter counts down to zero and then signal a local bus abort When disabled and the DSP MPU or DMA controller attempts to access ...

Page 1042: ...y 6 Other values Reserved These bits control the local bus clock rate The clock for the local bus is derived from the OMAP5910 traffic controller clock The local bus clock can be set to be transfer controller clock divided by 2 divided by 4 or divided by 6 All other values are reserved and must not be used This field must be set to a suitable value to allow USB host controller access to system mem...

Page 1043: ...When the DMA controller MPU or DSP attempts to access a local bus slave peripheral and a local bus abort occurs the address of the cycle is captured to this register R 0xFFFF FFFF 14 7 7 LB Abort Data Register LB_ ABORT_DATA This register reports the data bus value for the last DMA controller DSP or MPU local bus cycle that was aborted This register is not affected by OMAP5910 USB host controller ...

Page 1044: ...Cycle type from aborted local bus access Indicates when 1 that the last aborted local bus access was a read When 0 indicates that the last aborted local bus access was a write R 0 2 LB_DMA DMA sourced aborted local bus access When 1 indicates that the last aborted local bus access was sourced by the DMA controller R 0 1 LB_DSP DSP sourced aborted local bus access When high indicates that the last ...

Page 1045: ..._ABORT_MASK bit of the LB_CLOCK_DIV register is set to 0 Because the DMA controller DSP and MPU could mistakenly attempt to access a local bus slave peripheral address it is recommended that system software trap the local bus abort interrupt and signal a system error should one occur R 1 3 0 IRQ_IN_STAT Reserved for future expansion These bits can be ignored R 0xF 14 7 11 Local Bus Initialization ...

Page 1046: ...tailed functional description of the MMU architecture can be found in Chapter 2 MPU Subsystem The local bus MMU includes the following basic blocks A 32 entry translation look aside buffer TLB Walking table logic Registers for recording fault status and fault address When properly configured and enabled the walking table logic automatically performs the address conversion from local bus virtual ad...

Page 1047: ...EG LB MMU fault status R R 16 FFFE C214h LB_MMU_IT_ACK_REG LB MMU interrupt acknowledge W W 16 FFFE C218h LB_MMU_TTB_H_REG LB MMU TTB high R R W 16 FFFE C21Ch LB_MMU_TTB_L_REG LB MMU TTB low R R W 16 FFFE C220h LB_MMU_LOCK_REG LB MMU lock counter R W R W 16 FFFE C224h LB_MMU_LD_TLB_REG LB MMU TLB load read R W R W 16 FFFE C228h LB_MMU_CAM_H_REG LB MMU CAM high R W R W 16 FFFE C22Ch LB_MMU_CAM_L_RE...

Page 1048: ...MU RAM read high R W R W 16 FFFE C24Ch LB_MMU_READ_RAM_ L_REG LB MMU RAM read low R W R W 16 FFFE C250h This register reports the local bus MMU walking table status Table 14 49 LB MMU Walking Status Register LB_MMU_WALKING_ST_REG Access Hardware Reset Bit Name Function User Sup Reset Value 15 2 Reserved Reserved 1 Wtl_working When 1 the walking table is active R R W 0 0 Reserved Reserved ...

Page 1049: ...led When 0 the local bus MMU is disabled and local bus virtual addresses in the range 0000 0000h to 0FFF FFFF are mapped directly to physical address range 0000 0000h to 00FF FFFFh R R W 0 0 Reset_sw When 0 holds the local bus MMU in reset When 1 the local bus MMU is not held in reset Software must set this bit to allow the MMU to function R R W 0 The LB MMU fault address registers report the loca...

Page 1050: ...d Reserved 2 Perm_fault Permission fault Active high R R 0 1 Tlb_miss TLB miss when WTB disabled Active high R R 0 0 Trans_fault Translation fault invalid descriptor Active high R R 0 The LB MMU register is used to acknowledge the local bus MMU interrupt at the local bus MMU interrupt generator Acknowledging the interrupt at the local bus MMU interrupt generator causes the generator to deassert it...

Page 1051: ...cess Hardware Reset Bit Name Function User Sup Reset Value 15 0 TTB_REG_H Most significant 16 bits of physical address of translation table base address R R W 0 Table 14 56 LB MMU TTB Address Low Register LB_MMU_TTB_L_REG Access Hardware Reset Bit Name Function User Sup Reset Value 15 0 TTB_REG_L Least significant 16 bits of physical address of translation table base address Bits 9 0 must always b...

Page 1052: ...to 31 7 Write the LD_TLB_REG register with the Ld_tlb_item bit set 8 Enable the table walking logic if necessary To read one local bus MMU TLB entry use the following procedure 1 Disable the table walking logic if not already disabled 2 Write the TLB entry number of the TLB entry to be read into Current_ victim number must be equal to or greater than the current value of Base_value and must be les...

Page 1053: ...d against the local bus virtual address when a local bus access occurs Bits 31 28 of the local bus virtual address are ignored in the address comparison Note The USB host controller can malfunction if the local bus MMU is programmed with tiny pages See Section 14 8 2 1 Local Bus MMU Page Size and the USB Host Controller for more information Table 14 59 Local Bus MMU CAM High Register Access Hardwa...

Page 1054: ... Bits of the local bus virtual address to be used for the level 2 table index lookup depending on page size For tiny pages bits 13 4 of this register are compared against local bus virtual address bits 19 10 For small pages bits 13 6 are compared against local bus virtual address bits 19 12 For large pages bits 13 10 are compared against local bus virtual address bits 19 16 For sections this field...

Page 1055: ...R W R W 0 Table 14 62 Local Bus MMU RAM Low Register Access Hardware Reset Bit Name Value Function User Sup Reset Value 15 10 Ram_LSB Least significant six bits of the physical address that corresponds to a local bus virtual address R W R W 0 9 8 AP Access permission bits R W R W 0 00 No access Any local bus access to this page causes a permission fault 01 No access Any local bus access to this pa...

Page 1056: ...lush When written with a 1 all nonprotected TLB entries are flushed Has no effect when written with a 0 Always returns 0 on read R W R W 0 The LB MMU entry flush register allows flushing of individual local bus MMU TLB entries Table 14 64 Local Bus MMU Entry Flush Register Access Hardware Reset Bit Name Function User Sup Reset Value 15 1 Reserved Reserved 0 flush_entry When written with a 1 flushe...

Page 1057: ...the local bus virtual address which are used for this entry level 1 table index R W R W 0 13 4 VA_tag_l2 Bits of the local bus virtual address which may be used for the level 2 table index lookup depending on page size For tiny pages bits 13 4 are used For small pages bits 13 6 are used For large pages bits 13 10 are used For sections this field is ignored R W R W 0 3 P Preserved bit When 1 CAM en...

Page 1058: ...ble 14 67 Local Bus MMU RAM Read Low Register Access Hardware Reset Bit Name Function User Sup Reset Value 15 10 Ram_LSB Least significant six bits of the physical address that corresponds to a local bus virtual address R W R W 0 9 8 AP Access permission bits R W R W 0 00 No access Any local bus access to this page causes a permission fault 01 No access Any local bus access to this page causes a p...

Page 1059: ...ess space with the first of the tiny pages aligned on a 4K byte boundary in both processor physical address space and local bus virtual address space When using local bus MMU tiny pages failure to allocate and align groups of four tiny pages as described here results in malfunction of the USB host controller memory access operations 14 8 2 2 Local Bus MMU and Page Protection The access protection ...

Page 1060: ...ocal bus must be operating 14 9 2 Initializing ULPD to Generate the 48 MHz Clock The ULPD module generates 48 MHz for the USB host controller using either a digital PLL DPLL or an analog PLL APLL The USB host controller receives a clock from the ULPD module when the CONF_MOD_USB_HOST_ HHC_UHOST_EN_R bit is set This register bit provides the clock request from the USB host controller to the ULPD Th...

Page 1061: ...er software read the HcRevision and HcHCCA registers after deasserting reset to verify the proper reset values If the read values for both HcRevision and HcHCCA are not the correct reset the values and continue reading until the proper reset values are seen The CONF_MOD_USB_HOST_HHC_UHOST_EN_R bit when cleared also holds the USB host controller in a hardware reset While the USB host control ler is...

Page 1062: ...ltiplexing controlled by CONF_MOD_USB_HOST _HMC_MODE_R is not affected so a CONF_MOD_USB_HOST_HMC _MODE_R setting that multiplexes USB function controller and or UART1 signals to OMAP5910 top level multiplexing can still make use of the USB function controller and or UART1 When the OMAP5910 host controller s 48 MHz clock is disabled all USB host controller OHCI registers and the HostUEAddr HostUES...

Page 1063: ...Instruments web site 14 10 3 VBUS Monitoring for USB Function Controller A USB function controller must be capable of monitoring the VBUS voltage provided by the upstream USB host controller The OMAP5910 device pro vides the input pin USB_VBUSI which is provided to the OMAP5910 USB function controller This input is a CMOS input that is not rated for the full VBUS range specified by the USB specifi...

Page 1064: ...an be connected directly between the OMAP5910 USB PUEN and the D signal 14 10 5 Port Passthrough Mode When MOD_CONF_CTRL_0 register CONF_MOD_USB_HOST_HMC_ MODE_R is 7 with appropriate top level signal multiplexing settings the signals from six OMAP5910 input pins are passed to six OMAP5910 output pins This mode is described in Table 14 68 Table 14 68 CONF_MOD_USB_HOST_HMC_MODE_R 7 Internal Connect...

Page 1065: ...reset If low the MPU processor boots from memory connected to CS0 on the EMIFS if high the MPU processor enters the boot overlay mode causing it to boot from memory connected to CS3 on the EMIFS After reset the pin may be config ured for other functionality such as the USB1 SUSP output The MPU_BOOT signal has an internal pulldown resistor that is enabled by default The boot overlay mode requires a...

Page 1066: ... This chapter describes clock generation and system reset for the OMAP5910 multimedia processor Topic Page 15 1 Introduction 15 2 15 2 Clock Generation 15 8 15 3 Power Management 15 21 15 4 Clock Generation and Reset Control Registers 15 50 Chapter 15 ...

Page 1067: ...celerators MPU peripheral bridge LCD I F MPU Interface SRAM SDRAM memories Flash and SRAM memories DSP MMU 16 16 32 16 32 32 32 32 32 32 16 MPU privatePeripherals bus DSP public shared pheripheral bus 32 MPU public 16 DSP DSP public peripherals McBSP1 McBSP3 MPU public peripherals USB Host I F JTAG emulation I F OSC 12 MHz Clock OSC OMAP5910 ETM9 Timers 3 MPU DSP shared peripherals Mailbox MPU pri...

Page 1068: ...ACK_R EQ ARM_IDLECT1 SETARM_IDLE ARM_CKCTL ARM_INTHCK_SEL DSP_IDLCT 1 IDLWDT_DSP DSP_IDLCT2 EN_WDTCK IDL E EN Mux DSP_CK CTL GPIOXO sdw_mclk_req bclkreq com_mclk_r eq mclkreq periph_nr e q cam_dpll_mclk_r eq IDL E EN ARM_IDLCT1 IDLLB_ARM ARM_IDLCT2 EN_LBCK LB_CK EN Autogating_ on IDLE EMIFS_CONFIG PDE EMIFS_CONFIG P WD_EN EMIFF_CONFIG clk SDRAM_CK IMIF_CK MOD_CONF_CTRL_0 DPLL1_out mmc_dpll_clk 48M...

Page 1069: ... request 48 MHz 48 MHz clock mode state machine CLKIN 12 MHz CHIP_IDLE Chip reset WAKEUP_nREQ CHIP_nWAKEUP IRQs and interrupts Reset Generator MPU reset DSP reset MPU peripheral reset DSP peripheral reset Power on reset MPU watchdog reset DSP watchdog reset Chip idle wakeup control DPLL1 CLKM1 Clocks to MPU and peripherals CLKM2 Clocks to DSP and peripherals CLKM3 Clocks to traffic controller and ...

Page 1070: ...ates an external quartz based oscillator 32 kHz Performs the wake up of the 12 MHz OSC1 oscillator to provide the OSC1 clock to an external device An external clock request or peripheral wake up request turns on the OSC1 oscillator but is not treated as an interrupt Performs a 12 MHz 32 kHz switch for peripherals that need to switch to 32 kHz Generates the functional reset signal used by the reset...

Page 1071: ...capability to the DSP and its subsystem J GPIO J Timers J Other peripherals Programmable clock from CLKM3 with clock and idle control capability to the memory interface traffic controller TC including the following modules J MPU interface MPUI J System DMA controller J LCD controller J Local bus J MPU peripheral bridges J Two internal MPU TI peripheral bridges to minimize access latency Programmab...

Page 1072: ...registers for the DSP subsystem These registers are accessible by the MPU or the DSP processors The MPU is the master of the OMAP5910 device at all times and it controls the activities in the MPU DSP and TC domains The DSP controls DSP peripheral activities 15 1 1 5 Clock Domains The OMAP5910 is partitioned into three clock domains each with its own clock manager MPU domain CLKM1 DSP domain CLKM2 ...

Page 1073: ...synthesizers frequency lock but not phase lock Control register file CLKREG clock generator system reset idle and wake up controls Three CLKMs clock generation and wake up controls Figure 15 4 Clock Generation and System Reset Module CLKIN 12 MHz clock DPLL1 CLKM1 Clocks to MPU and peripherals CLKM2 Clocks to DSP and peripherals CLKM3 Clocks to traffic controller and peripherals ...

Page 1074: ...Use FIFO logic between MPU and TC DSP MMU and TC Others Reserved Do not use this settings Note In all the above cases the frequency of the DSP can be 1x or 2x that of DSP MMU Table 15 2 CLKM Source Selection Set via the MPU System Status Register Clock Select Operating Mode CLKM1 Input Clock Source CLKM2 Input Clock Source CLKM3 Input Clock Source Remarks 000 Fully synchronous DPLL1 N DPLL1 O DPLL...

Page 1075: ...at the clocks are synchronous but are multiples of each other The input clock is from DPLL1 and the clock is multiplied divided by the CLKM 1 2 3 as in the following example assuming the output of DPLL1 is 120 MHz J CLKM1 output 120 MHz 2 J CLKM2 output 120 MHz 1 J CLKM3 output 120 MHz 4 Divider circuitry is implemented in each CLKM Note In synchronous scalable mode the traffic controller clock mu...

Page 1076: ...ode is as follows 1 During power on reset OMAP5910 is in deep sleep J 12 MHz on chip oscillator is disabled J MCLKREQ pin is an input 2 After power on reset OMAP5910 is awake J 12 MHz oscillator is bypassed J MCLKREQ pin is an input J 12 Mhz clock is provided externally 3 Switch to external master mode by setting FUNC_MUX_CTRL_B 20 18 001 J The 12 MHz oscillator is bypassed disabled J MCLKREQ pin ...

Page 1077: ...EG EN PLL_MULT PLL_DIV PLL_ENABLE CK_GEN1 ARMDIV ARM_CKCTL ARM_TIMXO ARM_CKCTL MPUTIM_CK PERDIV ARM_CKCTL ARM_CK MPUPER_CK CLKIN CK_GEN1 CK_GEN1 CK_GEN1 IDLE SETARM_IDLE ARM_IDLECT1 IDLE EN ARM_IDLECT2 EN_GPIOCLK ARM_GPIO_CK CK_GEN1 EN ARM_IDLECT1 IDLXORP_ARM ARM_IDLECT2 EN_XORPCK MPUXOR_CK IDLE EN GPIO I F McBSP ARM_IDLECT1 IDLWDT_ARM ARM_IDLECT2 EN_WDTCK MPUWD_CK IDLE EN MPU watchdog timer CLKIN...

Page 1078: ... OR_CK clock by the EN_XORPCK bit MPU watchdog timer clock low frequency derived from CK_REF 14 Called either CK_CLKIN14 or MPUWD_CK This clock is enabled by the EN_WDTCK bit of the MPU idle mode entry 2 register ARM_IDLECT2 The IDLE mode is controlled by the IDLWDT_ARM bit of the MPU idle mode entry 1 register ARM_IDLECT1 The clock cannot be disabled or idled while in the watchdog mode MPU intern...

Page 1079: ...ibution CLKIN 12 MHz CK_GEN2 1 2 4 or 8 ARM_CKCTL DSPDIV TIMXO DSP_CKCTL DSPTIM_CK DSP_CK CLKIN CK_GEN2 CK_GEN2 EN DSP_IDLECT1 DSP_IDLECT2 EN_GPIOCK DSP_GPIO_CK IDLE EN DSP_IDLECT1 IDLXORP_DSP DSP _IDLECT2 EN_XORPCK DSPXOR_CK IDLE EN DSP GPIO DSP_IDLECT1 IDLWDT_ARM DSP_IDLECT2 EN_WDTCK DSPWD_CK IDLE EN DSP watchdog timer CLKIN 14 CLKIN 0 857 MHz DSP_IDLECT1 IDLTIM_DSP DSP_IDLECT2 EN_TIMCK IDLE EN ...

Page 1080: ...he clock is enabled by the EN_GPIOCLK bit of the DSP idle mode entry 2 register DSP_IDLECT2 The IDLE mode is controlled by the IDLG PIO_DSP bit of the DSP idle mode entry 1 register DSP_IDLECT1 J DSP public peripherals McBSPs MCSIs DSPXOR_CK which is derived from CLKIN The clock is enabled by the EN_XORPCK bit of the DSP idle mode entry 2 register DSP_IDLECT2 The IDLE mode is controlled by the IDL...

Page 1081: ...er the global reset period the MPU application program can change the clock frequency through the CK_GEN2 control register DSP_CK is enabled at reset until the DSP is in reset state The EN_DSPCK bit located in the clock control register ARM_CKCTL allows the MPU to turn off the DSP_CK while the DSP is held in a reset state A free running counter divider receives the CK_GEN2 signal and makes avail a...

Page 1082: ...ck Distribution CLKIN 12 MHz CK_GEN3 CLKM3 DPLL1 output ARM_SYSSR CLOCK_SELECT Traffic controller 1 2 4 or 8 ARM_CKCTL TCDIV 1 2 4 or 8 ARM_CKCTL LCDDIV ARM_IDLECT1 IDLIF_ARM IDLE TC_CK TIPB_CK ARM_IDLECT1 IDLLB_ARM ARM_IDLECT2 EN_LBCK IDLE EN LB_CK ARM_IDLECT1 IDLLCD_ARM ARM_IDLECT2 EN_LCDCK IDLE EN LCD_CK Local bus ARM_IDLECT2 DMACK_REQ EN DMA_CK ARM_IDLECT1 IDLAPI_ARM ARM_IDLECT2 EN_APICK IDLE ...

Page 1083: ...by the EN_LBCK bit of the MPU idle mode entry 2 register ARM_IDLECT2 MPU port interface MPUI clock is dependent not only on the IDLAPI_ARM bit of the MPU idle mode entry 1 register ARM_IDLECT1 but also on DSP_IDLE The system DMA controller clock DMA_CK is the same as TC_CK The IDLE mode is controlled by the IDLIF_ARM bit of the MPU idle mode entry 1 register ARM_IDLECT1 and the clock is enabled by...

Page 1084: ...Thus this buffering can be bypassed if it is not needed that is when domains are running at the same speeds For the fully synchronous clocking scheme MPU_CK DSPMMU_CK TC_CK the FIFO logic is bypassed between TC and MPU TC and DSPMMU For the synchronous scalable clocking scheme FIFO logic is used for both processors Note TC_CK clock must be slower than or equal to the MPU_CK and DSP MMU clock speed...

Page 1085: ...re support of the low voltage operational mode The LOW_PWR signal is multiplexed on the MPUIO5 ball To get it on this ball you must set bits 14 12 of the FUNC_MUX_CTRL_7 register to 001 Figure 15 9 Low Voltage Mode Low_pwr 1 5 V Awake big sleep Deep sleep Analog wait timer Big sleep awake 1 1 V ULPD state LOW_PWR VDD ULPD analog wait state timer delays deep sleep to big sleep transition while regu...

Page 1086: ... the 12 MHz clock is stable the ULPD brings the device into awake mode To reduce the wake up time a special hardware request is implemented in parallel to interrupts to wake up the ULPD whenever an interrupt occurs This request is generated by peripherals as USB or UART When receiving the hardware request the ULPD brings the device out of the deep sleep mode to wakeup the 12 MHz clock When the clo...

Page 1087: ...clock CK_REF is off If a 48 MHz clock is requested it is generated by ULPD DPLL or APLL If an external 12 MHz clock is requested it is enabled Deep sleep mode 32 kHz clock is on 12 MHz and PLLs are off Internal 12 MHz clock CK_REF is off No 48 MHz or external 12 MHz clocks Wait for 12 MHz clock to be stable PWRON_RESET power on reset Wake up request No request for 48 MHz or 12 MHz clock 12 MHz clo...

Page 1088: ... MPUIO keyboard MPU interrupt AWAKE MPUIO GPIO MPU interrupt AWAKE Timer32K MPU interrupt AWAKE UART2 RX detection Peripheral request generated to ULPD AWAKE RTC MPU interrupt AWAKE USB cable insertion USB request to ULPD which generates MPU interrupt BIG SLEEP then AWAKE via the MPU interrupt UART1 2 3 wait for a falling edge on the RX DSR or CTS signals MPU DSP interrupt AWAKE MCLK_REQ external ...

Page 1089: ...anagement module CLKM To maximize power conservation seven different peripheral idle modes are defined UART GPIO timers watchdog timer Each one can be individually activated and deactivated by software Two different strategies are used to control the clock that feeds the DSP peripherals J The clock is shut off activated according to the DSP idle mode or ap plication specific environment disable th...

Page 1090: ...bus is owned exclusively by the MPU usually because the DSP is in idle mode or about to go to idle mode 8 Execute the IDLE instruction DSP goes to sleep If INTM is set ISR is not executed after wake up the interrupt simply wakes the DSP up The program continues just after the IDLE instruction otherwise ISR is executed When the DSP is awakened by an enabled interrupt or an external event such as re...

Page 1091: ...upt request or system reset Wait For Interrupt Instruction When the MPU CP15 instruction is used the system software does not need to take care of adding any extra cycles to wait after the instruction being exe cuted the MPU itself takes care of this When this instruction is executed the MPU stops its ongoing operations and sends a sleep acknowledge signal to the OMAP clock reset module to request...

Page 1092: ...s to make sure there is no request coming from the MPU by considering the worst case scenario This scenario is MMU and I cache enabled a MMU TLB miss requiring a L1 and L2 fetch and an I cache miss as follows J Four read strobes for the instruction fetch a line load of 4 words J One read strobe for TLB Miss L1 descriptor fetch J One read strobe for TLB Miss L2 descriptor fetch This requires six re...

Page 1093: ...LSL 11 MOV R2 0 LDR R0 R1 ORR R0 R0 R3 This is the loop that will wait for at least 100 cycles before issuing next request from ARM On the first run of the loop only Icache gets loaded with the loop and the next 2 instructions but write to SYSST does not occur In the 2nd run of the loop only write to IDLE_CT1 happens and after that ARM runs the loop from Icache so no request goes out LOOP CMP R2 1...

Page 1094: ... state16 into_16_bis nop nop nop nop nop nop nop nop nop nop pop r1 r7 pop pc CONSTANT TABLE ARM_IDLECT1 long 0xFFFECE04 Example If the reference clock speed 12 MHz then MPU clock speed 96 MHz If the above routine is used after the write to ARM_IDLECT1 register you need 4 96 12 2 3 37 clock cycles To achieve this run the loop seven times ...

Page 1095: ...he MPU peripherals The clock that is shut off activated according to the MPU idle mode Peripherals connected to this clock cannot request DMA transfers during the MPU idle mode The clock that is never shut off input reference clock In either case the MPU peripheral clocks are directly shut off activated by the MPU software 15 3 3 Traffic Controller Idle Modes A clock management register ARM_IDLECT...

Page 1096: ...mode and there is no DMA transfer when the clock is required to be shut off the memory interface completes the current memory transaction before notifying the CLKM3 to shut off the clock The MPUI clock can also be forced off with the enable bit the MPUI clock can only be shut off by the enable bit in current implementation Note To idle the traffic controller the system software must ensure that th...

Page 1097: ...en to stop CLKIN CK_REF to the clock generation module and it uses the WAKEUP_nREQ signal to restart the clock see Figure 15 13 Figure 15 13 Chip Idle and Wake Up Control External clock requests ULPD sleep mode state machine Internal clock request CHIP_IDLE WAKEUP_nREQ CHIP_nWAKEUP IRQs and interrupts Clock management chip idle and wakeup control SDCLK_EN SDRAM clock enable NFRP flash power down P...

Page 1098: ...is high Note that WAKEUP_nREQ is asserted by OMAP whenever there any wake up condition occurs even when OMAP is not in CHIP_IDLE FLASH RP and SDRAM CKE Power control for external devices for example flash and SDRAM Power on reset Must be valid until power and input clock are stable CHIP_IDLE Chip idle mode Indicates that all internal clocks are stopped This internal signal is active regardless the...

Page 1099: ...EG 0x0C618800 2 Disable the MPU watchdog timer by first writing 0x00f5 to the WDTIM ER_TIMER_MODE_REG and then writing 0x00A0 this is to prevent a watchdog reset from being generated that results in a global reset 3 Set up the MPU interface write to the MPUI control setup and DSP boot registers 4 Set API_SIZE_REG 0x0000 only need to set the bits that correspond to the SARAMs with DSP code to 0 5 E...

Page 1100: ...entry 2 register ARM_IDLECT2 0x0087 can also write 0x0000 which disables the MPU peripheral clocks instead of letting them go to IDLE only after MPU goes to IDLE using the MPU idle mode entry 1 register ARM_IDLECT1 IDL_ARM Put the MPU into IDLE by writing MPU idle mode entry 1 register ARM_IDLECT1 0x0FFF which sets the SETARM_IDLE bit This also sets the IDLIF bits which allow the MPU peripherals t...

Page 1101: ...start of the ARM_CK ARM_INTH_CK TIPB_CKs DMA_CK and TC_CK clocks depending on the setting of the MPU idle mode entry 1 2 registers ARM_IDLECT1 2 peripherals clocks can also restart If the idle mode was entered from the SETARM_IDLE bit then the bit is cleared to 0 2 DSP_nIRQ Upon an interrupt request the DSP interrupt handler initiates the restarting of the MPUI clock if MPUICK_EN is not set to 0 D...

Page 1102: ...t least one of the internal clocks is running the CHIP_nWAKEUP signal is disabled and a single wake up con dition not ULPD controlled brings the DSP or MPU system out of idle mode A global system reset brings the OMAP5910 device out of idle mode regard less of the WAKEUP_MODE bit value ULPD control or the interrupt status Figure 15 14 illustrates an ULPD controlled wake up sequence assuming the DS...

Page 1103: ...tive J System DMA controller is not active Mode 4 The MPU the DSP and traffic controller are stopped the traffic controller can be stopped only if both the MPU and the DSP are in idle for both J Peripheral modules are individually stopped J All peripherals are stopped Mode 5 The MPU the DSP peripherals and DPLL 1 are stopped how ever the timer watchdog or OS timer is still active Mode 6 chip idle ...

Page 1104: ...USB clock is handled in the ULPD module ULPD DPLL is a x4 digital PLL APLL is a x48 analog PLL The input clock ref is 1 MHz based on either a 12 MHz system clock divided by 12 or optionally on a 13 MHz system clock divided by 13 The switch between DPLL and APLL is controlled by software through a TIPB register of ULPD 15 3 6 1 Gauging the 32 kHz Oscillator As the 32 kHz oscillator exact frequency ...

Page 1105: ...of high frequency counter J counter_hi_freq_lsb is the LSB value of high frequency counter Use the following procedure to gauge the 32 kHz clock versus the high frequency clock 1 Select gauging versus high frequency clock J Write gauging_ctrl 0 0 to select gauging versus 12 MHz clock or J Write gauging_ctrl 0 1 to select gauging versus external or DPLL clock 2 Start gauging by writing gauging_ctrl...

Page 1106: ...atus register 15 3 6 3 Control of 32 kHz Oscillator The 32 kHz oscillator start up time is configurable via the bits MOD_32KOSC_SW_R bits of the module configuration control 0 register MOD_CONF_CTRL_0 in OMAP5910 configuration The 32kHz clock source can come from either the on chip 32 kHz oscillator or from an external 32 kHz clock oscillator providing a clock onto the CLK32K_IN input pin Clock so...

Page 1107: ... idle state it informs power management to enter into sleep mode by setting the CHIP_IDLE signal The state machine cuts the 12 MHz OSC1 oscillator only if external devices do not request the oscillator clock 15 3 6 6 Power On Reset The PWRON_RESET signal is used to reset the entire device This signal is resynchronized on the 32 kHz to achieve a clean reset Then the ULPD module initiates the intern...

Page 1108: ...ed as the input clock of the ULPD The 12 MHz oscillator is on during awake and big sleep mode It is off during deep sleep mode The power management module handles the wake up sequence When using the on chip oscillator normal mode either a 12 MHz crystal or a 13 MHz crystal can be connected to the OSC1_IN and OSC1_OUT pins so that the on chip oscillator generates a 12 MHz or a 13 MHz clock referenc...

Page 1109: ...after 20 REF_ CK cycles and warm reset is released after 30 additional cycles When the device is awake MPU_RST controls the warm reboot of the MPU The external reset signal must be asserted for 30 REF_CK cycles to be recognized The reset signal is synchronized before feeding to the reset manager module RSTM that generates the internal reset signals within the OMAP5910 device The internal reset is ...

Page 1110: ... reset is in response to the assertion of the external reset signal PWRON_RESET When the reset is initiated from the pin the OMAP5910 device is held in reset until the pin goes inactive The reset module generates reset signals to the respective modules All modules are put to a known state and the RAM data is in an unknown state During the power up reset the DSP and the DSP subsystem are held in re...

Page 1111: ...pheral interrupt priority encoder registers and part of the MPUI control logic 15 3 9 3 Watchdog Reset DSP and MPU MPU watchdog A system reset global reset is generated when the down counter underflows assuming the MPU watchdog timer is configured as a watchdog timer DSP watchdog A DSP reset reset the DSP and the DSP MMU is gener ated when the down counter underflows assuming the DSP watchdog time...

Page 1112: ...sibly survive the warm reset and become posted again after the reset condition J DPLL register is not reset J SETUP_ANALOG_CELL3_ULPD1_REG is not reset ARMIO_CTL and DATA_OUT registers associated with MPUIO logic are NOT reset and retain their previous values The appropriate bits within the ARM_SYSST register are set to indicate that the reset event was due to a warm boot the MPU can read ARM_SYSS...

Page 1113: ...AP5910 is in low power or deep sleep mode Multiplexing logic responsible for driving LOW_PWR onto the correct pin is not reset The LOW_PWR pin transitions from high to low OMAP5910 implements a deep sleep mode wherein the 12 MHz oscillator is powered down A MPU_RESET event will alert the ULPD module which will turn on the 12 MHz oscillator When this oscillator s clock is stable the re boot of the ...

Page 1114: ...ning at the CK_REF frequency Set the domains to operate at the desired frequencies as follows Select the desired clocking mode via the CLOCK_SELECT bit of the MPU system status register ARM_SYSST Program each of the division modes for the DPLLs for the clock domains Program the DPLLs and enable them Program each domain defined enable bit discussed in section 15 4 Clock Generation and Reset Control...

Page 1115: ...supervisor mode only Some registers are dedicated to the DSP subsystem and can be moni tored by the DSP only Those registers are mapped to the DSP memory space starting at DSP word address hex 004000 They can also be accessed by the MPU through the MPUI interface The remaining registers are controlled by the MPU only They are memory mapped to the MPU memory space starting at address hex FFFECE00 T...

Page 1116: ...ch as reset status flags processor state R W 16 bits x18 0x0000 0038 ARM_CKOUT2 Reserved 0x20 The MPU clock control register ARM_CKCTL defines the frequency for ARM_CK DSPMMU_CK TC_CK DSP_CK LCD_CK and MPUPER_CK Table 15 6 MPU Clock Control Register ARM_CKCTL Bit Name Value Description Type Reset Value 15 RESERVED Reading this bit gives an undefined value and writing to it has no effect 14 ARM_INT...

Page 1117: ...clock domain clock DSPMMU_CK R W 0 9 8 TCDIV 1 0 These read write bits define prescaler value from frequency of CK_GEN3 to TC clock domain clock TC_CK R W 0 7 6 DSPDIV 1 0 These read write bits define prescaler value from frequency of CK_GEN2 to DSP clock domain clock DSP_CK R W 0 5 4 ARMDIV 1 0 These read write bits define prescaler value from frequency of CK_GEN1 to MPU clock domain clock ARM_CK...

Page 1118: ...so that ARMDIV DSPDIV DSPMMUDIV and TCDIV are all equal At reset these divide down bits are all defaulted to divide by 1 In any mode the DSPDIV and DSPMMUDIV must be set so that the DSPMMU_CK is either to DSP_CK or DSP_CK 2 In synchronous scalable mode you must make sure that the DSPMMUDIV and ARMDIV are greater than or equal to TCDIV Table 15 7 lists the frequency selections for TC_CK and LCD_CK ...

Page 1119: ...ach clock domain Table 15 10 MPU Idle Mode Entry 1 Register ARM_IDLECT1 Bit Name Value Description Type Reset Value 15 12 RESERVED Reading these bits gives undefined value Writing them has no effect 11 SETARM_IDLE Initiates MPU idle mode when written to a logical 1 and is cleared by a global reset or an interrupt request nIRQ_SET from interrupt handler to MPU processor R W 1 0 MPU active or in idl...

Page 1120: ...n CHIP_nWAKEUP signal 9 IDLTIM_ARM Selects idle entry mode for internal MPU timer clock R W 0 0 Clock supplied to timers remains active when MPU enters idle mode ARM_CK stopped 1 Timer clock stopped in conjunction with MPU clock when idle mode entered 8 RESERVED Reserved To prevent errant behavior always write this bit as 0 R W 0 7 IDLDPLL_ARM Enables DPLL1 to enter idle mode when following condit...

Page 1121: ...LPER_ARM Selects idle entry mode for peripheral clock MPUPER_CK R W 0 0 Clock remains active when MPU enters idle mode 1 Clock stopped in conjunction with MPU idle mode entry 1 IDLXORP_ARM Selects idle entry mode for 32 k or gp timer MPU TIPB and peripheral clock MPUXOR_CK R W 0 0 OS timer and MPUXOR_CK clock remain active when MPU enters idle mode 1 OS timer and MPUXOR_CK clock are stopped in con...

Page 1122: ... permanently supplied clock to system DMA controller to function on a clock request basis R W 1 0 DMA clock shutdown when idle mode is entered if IDLIF_ARM 1 1 DMA clock stopped by default reactivated upon DMA requests only 7 EN_ TIMCK Enables clock of MPU timer connected to MPU TIPB R W 0 0 MPU timer clock is stopped bit must be set to logic 1 to enable clock activity 1 MPU timer clock active and...

Page 1123: ... MPU idle mode entry 1 register ARM_IDLECT1 1 EN_XORPCK Enables clock of OS timer connected to MPU TIPB and CLKIN reference peripheral clock XORP_CK P R W 0 0 OS timer clock and external XORP_CK clock stopped bit must be set to logic 1 to authorize clock activity 1 OS timer clock and external XORP_CK clock active and can be stopped depending on IDLXORP_ARM bit of MPU idle mode entry 1 register ARM...

Page 1124: ...p Register ARM_EWUPCT Bit Name Value Description Type Reset Value 15 6 RESERVED Reading these bits gives undefined values Writing them has no effect 5 REPWR_EN Enables external power control feature R W 1 0 FLASH RP pin is set to logic low Vol when traffic controller TC is in idle mode 1 FLASH RP pin is not activated when TC idle mode is entered 4 0 EXTPW 4 0 Define delay from PWRON_RESET pin goin...

Page 1125: ...y registers TIPB module EMIF configuration registers and MPUI control logic partially in DSP This bit is set by external reset pins and is released by writing a logic 1 in register use for MPUI boot R W 0 0 Priority EMIF configuration registers and MPUI are reset 1 Priority and EMIF configuration registers can be programmed 1 DSP_EN Resets DSP R W 0 0 Resets DSP excluding configuration setting and...

Page 1126: ...ate chip configuration and reset status flags Table 15 15 MPU System Status Register ARM_SYSST Bit Name Value Description Type Reset Value 15 14 RESERVED Reading these bits gives undefined values Writing to them has no effect 13 11 CLOCK_SELECT 2 0 The CLOCK_SELECT bits indicate the current clocking scheme selection the application can switch OMAP5910 clocking scheme by writing to these bits These...

Page 1127: ...et 1 MPU has been reset 2 ARM_WDRST Indicates whether or not reset has been asserted due to an MPU timer watchdog underflow This bit is cleared to logic 0 upon a reset pulse asserted at CHIP_nRESET signal or by writing it to logic 0 This bit cannot be written to logic 1 from peripheral bus interface R C 0 0 MPU timer watchdog underflow has not occurred 1 MPU timer watchdog underflow has generated ...

Page 1128: ...upon an reset pulse asserting at CHIP_nRESET signal or by writing it to logic 0 This bit cannot be written to logic 1 from peripheral bus interface R C 0 0 DSP timer watchdog underflow has not occurred 1 DSP timer watchdog underflow has generated reset Table 15 16 lists the clocking schemes for the MPU system status register ARM_SYSST Table 15 16 Clocking Schemes for OMAP5910 CLOCK_SELECT 2 CLOCK_...

Page 1129: ... 8018 0x0000 Reserved 00 400E 0x0000 Reserved 00 4010 0x0000 The DSP domain peripheral clock setup and the external module reset functions are controlled by the DSP through these registers The DSP clock control register DSP_CKCTL defines the frequency selection for the DSP_GPIO_CK and the DSPTIM_CK Table 15 18 DSP Clock Control Register DSP_CKCTL Offset Address 0x00 Bit Name Value Description Type...

Page 1130: ...ipheral R W 1 0 The DSP_GPIO_CK clock frequency is the input reference clock 1 DSP_GPIO_CK frequency is issued from CK_GEN2 and defined by the GPIODIV field value 6 5 GPIODIV 1 0 These read write bits define prescaler value from CK_GEN2 to the GPIO clock signal GPIO_CK R W 0 4 0 RESERVED Reserved These bits should always be written as 0 Table 15 19 lists the selection for the DSP_GPIO_CK GPIOXO 1 ...

Page 1131: ...RVED R W 0 6 RESERVED Reserved To prevent errant behavior this bit should always be written as 1 R W 1 5 2 RESERVED Reserved To prevent errant behavior these bits should always be written as o R W 0 1 IDLXORP_DSP Selects idle entry mode for reference peripheral clock DSPXOR_CK R W 0 0 The DSPXOR_CK clock remains active when DSP enters idle mode 1 The DSPXOR_CK clock is stopped in conjunction with ...

Page 1132: ...ng on DSP_IDLECT1 IDLTIM_DSP bit 4 EN_GPIOCK Enables GPIO peripheral clock GPIO_CK R W 0 0 GPIO_CK clock is stopped The bit must be set to logic 1 to enable clock activity 1 GPIO_CK clock is active The GPIO_CK clock must be disabled by setting EN_GPIOCK 0 before sleep modes can be entered 3 2 RESERVED Reserved These bits should always be written as 0 1 EN_XORPCK Enables DSPXOR_CK reference clock R...

Page 1133: ..._nRST signal to inactive The DSP system status register DSP_SYSST contains the system information Table 15 23 DSP System Status Register DSP_SYSST Offset Address 0x18 Bit Name Value Description Type Reset Value 15 14 RESERVED Reading these bits gives undefined values Writing to them has no effect 13 11 CLOCK_SELECT 2 0 These read only bits reflect CLOCK_SELECT and indicate current clocking scheme ...

Page 1134: ... interface R C 0 0 No external reset detected 1 An external reset has been asserted 3 DSP_ARM_RST This read write bit is used by DSP to hold MPU in reset R C 0 0 The MPU is enabled This is default value after reset 1 Reset MPU 2 ARM_WDRST This read clear only status bit indicates whether or not reset has been asserted due to a MPU timer watchdog underflow This bit is cleared to logic 0 upon an ext...

Page 1135: ... DSP timer watchdog underflow has not occurred 1 DSP timer watchdog underflow has generated reset Notes 1 This bit is only to be used for test debug purposes only 2 In the OMAP5910 device the DSP_EN and ARM_RST bits located in ARM_RSTCT1 must be set together to activate the global software reset Setting the SW_RST bit only DSP_RSTCT1 results in global software reset flag 15 4 1 DPLL Operation Mode...

Page 1136: ...xited the DPLL is set in bypass mode and the output clock signal is valid after a maximum of 10 input reference clock cycles If the DPLL was synthesizing a frequency prior to enter the idle state then the DPLL switches from the bypass mode frequency set BYPASS_DIV to the synthesizer mode frequency set PLL_MULT and PLL_DIV when the lock state is reacquired Table 15 24 lists the DPLL control registe...

Page 1137: ...OUT frequency is 0 25 CLKREF When PLL_MULT 4 0 is equal to 0 or 1 CLKOUT is not synthesized by DPLL but by simply a divided down version of CLKREF Affects lock mode only 4 PLL_ENABLE Setting PLL_ENABLE bit to 1 requests DPLL to enter LOCK mode It enters LOCK mode only after it has synthesized desired frequency Clearing bit to 0 causes DPLL to switch back to bypass mode 3 2 BYPASS_DIV 1 0 Determine...

Page 1138: ... number of ticks from high frequency clock R 16 bits x0C 0x0000 GAUGING_CTRL_REG Drives gauging functionality R W 16 bits 0x10 0x0000 IT_STATUS_REG Interrupt status register R 16 bits 0x14 0x0000 Reserved 8 bits 0x18 0x01 Reserved 8 bits 0x1C 0x01 Reserved 8 bits 0x20 0x01 SETUP_ANALOG_CELL3_ULPD1_REG Number of 32 kHz clocks to wake up R W 16 bits 0x24 0x03FF Reserved 8 bits 0x2C 0x01 Reserved 8 b...

Page 1139: ... ticks from the 32 kHz clock during gauging time Table 15 27 Counter 32 LSB Register COUNTER_32_LSB_REG Bit Name Type Reset Value 15 0 COUNTER_32_LSB R 0x0001 The counter 32 MSB register COUNTER_32_MSB_REG represents the upper value of the number of ticks from the 32 kHz clock during gauging time Table 15 28 Counter 32 MSB Register COUNTER_32_MSB_REG Bit Name Type Reset Value 15 0 COUNTER_32_LSB R...

Page 1140: ...y It start stops it and selects the clock used as the high frequency clock Table 15 31 Gauging Control Register GAUGING_CTRL_REG Bit Name Value Description Type Reset Value 1 SELECT_HI_ FREQ_CLOCK 0 Use 12 MHz clock for high frequency clock R W 0 1 Reserved Do not use this setting 0 GAUGING_EN 0 Stop gauging R W 0 1 Enable gauging The setup analog cell3 ULPD1 register SETUP_ANA LOG_CELL3_ULPD1_REG...

Page 1141: ...errupt Informs the MPU that gauging is stopped and that it can read value of high and low frequency counters R 0x0 The clock control register CLOCK_CTRL_REG manages clock output and inactive values Table 15 34 Clock Control Register CLOCK_CTRL_REG Bit Name Value Description Type Reset Value 5 DIS_USB_PVCI_ CLK 0 Enables USB function clock for FAC counter R W 0x0 1 Disables USB function clock for F...

Page 1142: ...g on USB CLK0 2 SOFT_SDW_REQ 0 No software request for clocking on BCLK R W 0 1 Software request for clocking on BCLK 1 SOFT_COM_REQ 0 No software request for clocking on MCLK R W 0 1 Software request for clocking on MCLK 0 SOFT_DPLL_REQ 0 Software request for clocking on 48 MHz DPLL R W 0 1 Software request for clocking on 48 MHz DPLL except no software request possible when PLL_ENABLE 0 in DPLL_...

Page 1143: ... sequence if DPLL core ever indicates that it lost lock When set low DPLL continues to output synthesized clock even if core indicates it has lost lock but BREAKLN is active low The power on value is 1 R W 1 12 RESERVED This bit is reserved and set to 0 11 7 PLL_MULT 4 0 This bit is reserved and always written to its reset value R W 0x0 6 5 PLL_DIV 1 0 This bit is reserved and always written to it...

Page 1144: ...k for DPLL wake up requested by USB host R 7 CAM_DPLL_ MCLK_REQ 0 No request for 48 MHz DPLL wake up by camera interface R 1 Indicates request for 48 MHz DPLL wake up by camera interface 6 USB_DPLL_ MCLK_REQ 0 No request for 48 MHz DPLL wake up by USB interface R 1 Indicates request for 48 MHz DPLL wake up by USB interface 5 USB_ MCLK_REQ 0 No clock request by USB host R 1 Indicates clock request ...

Page 1145: ... the DPLL It controls all the input of the APLL Table 15 40 APLL Control Register APLL_CTRL_REG Bit Name Function R W Reset Value 15 4 Reserved Reserved These bits should always be writ ten as 0 R 0xx 3 SEL Bit used to select correct divider so the APLL can generate a 48 mHz clock from either a 12 mHz or 13 mHz reference source Bit de faults to the 12 mHz reference setting 0 Divide by 13 provides ...

Page 1146: ...HOST_OUT is inactive high 2 SW_RST Released hardware generation of RST_HOST_OUT R W 0x0 0 State of RST_HOST_OUT pin depends on BFAIL EXT_FIQ and 32k counter 1 State of RST_HOST_OUT pin is equal to level of SW_NSHUTDOWN bit 1 LOW_PWR_REQ Low power software request When this bit and the LOW_PWR_EN bit are high the LOW_PWR pin is driven active high R W 0x0 0 LOW_PWR_EN Low power enable bit Disable by...

Page 1147: ...ister ICR Bit Name Value Description Type Reset Value 15 6 RESERVED 0 5 EMIF_IDLE_DOMAIN 0 No request to idle DSP EMIF R W 0 1 Request to place DSP EMIF in idle 4 DPLL_IDLE_DOMAIN 0 No request to idle DSP DPLL R W 0 1 Request to place DSP DPLL in idle 3 PER_IDLE_DOMAIN 0 No request to idle DSP peripherals R W 0 1 Request to place DSP peripherals in idle 2 CACHE_IDLE_DOMAIN 0 No request to idle DSP...

Page 1148: ...6 RESERVED 5 EMIF_IDLE_STATUS 0 DSP EMIF not in idle R 0 1 DSP EMIF in idle 4 DPLL_IDLE_STATUS 0 DSP DPLL not in idle R 0 1 DSP DPLL in idle 3 PER_IDLE_STATUS DSP peripherals not in idle R 0 1 DSP peripherals in idle 2 CACHE_IDLE_STATUS 0 No request to idle DSP I cache not in idle R 0 1 DSP I cache in idle 1 DMA_IDLE_STATUS 0 DSP DMA controller not in idle R 0 1 DSP DMA controller in idle 0 CPU_ID...

Page 1149: ... by their functions Table A 1 Functional multiplexing control bits for each ball Table A 2 Consult the OMAP5910 Data Manual literature number SPRS197 for addi tional information including I O pad reset status buffer types and boundary scan pullup pulldown and gating inhibiting information Topic Page A 1 I O Signals A 2 A 2 I O Functional Multiplexing A 15 Appendix A ...

Page 1150: ...FLASH output enable U4 FLASH D 15 FLASH data bit 15 V3 FLASH D 14 FLASH data bit 14 T4 FLASH D 13 FLASH data bit 13 U3 FLASH D 12 FLASH data bit 12 U1 FLASH D 11 FLASH data bit 11 P8 FLASH D 10 FLASH data bit 10 T3 FLASH D 9 FLASH data bit 9 T2 FLASH D 8 FLASH data bit 8 R4 FLASH D 7 FLASH data bit 7 R3 FLASH D 6 FLASH data bit 6 R2 FLASH D 5 FLASH data bit 5 P7 FLASH D 4 FLASH data bit 4 P4 FLASH...

Page 1151: ...ess bit 22 K4 FLASH A 21 FLASH address bit 21 L8 FLASH A 20 FLASH address bit 20 J1 FLASH A 19 FLASH address bit 19 J3 FLASH A 18 FLASH address bit 18 J4 FLASH A 17 FLASH address bit 17 J2 FLASH A 16 FLASH address bit 16 K7 FLASH A 15 FLASH address bit 15 H3 FLASH A 14 FLASH address bit 14 H4 FLASH A 13 FLASH address bit 13 K8 FLASH A 12 FLASH address bit 12 G2 FLASH A 11 FLASH address bit 11 G3 F...

Page 1152: ...ddress srtobe A2 SDRAM DQMU SDRAM upper byte mask D4 SDRAM DQML SDRAM lower byte mask B3 SDRAM D 15 SDRAM data bit 15 D5 SDRAM D 14 SDRAM data bit 14 C4 SDRAM D 13 SDRAM data bit 13 B4 SDRAM D 12 SDRAM data bit 12 D6 SDRAM D 11 SDRAM data bit 11 C5 SDRAM D 10 SDRAM data bit 10 H8 SDRAM D 9 SDRAM data bit 9 C6 SDRAM D 8 SDRAM data bit 8 B6 SDRAM D 7 SDRAM data bit 7 D7 SDRAM D 6 SDRAM data bit 6 C7...

Page 1153: ...10 C11 SDRAM A 9 SDRAM address bit 9 D11 SDRAM A 8 SDRAM address bit 8 G11 SDRAM A 7 SDRAM address bit 7 C12 SDRAM A 6 SDRAM address bit 6 D12 SDRAM A 5 SDRAM address bit 5 H11 SDRAM A 4 SDRAM address bit 4 C13 SDRAM A 3 SDRAM address bit 3 D13 SDRAM A 2 SDRAM address bit 2 G12 SDRAM A 1 SDRAM address bit 1 C14 SDRAM A 0 SDRAM address bit 0 B14 LCD Interface LCD VS LCD vertical synchronization D14...

Page 1154: ...a bit 6 B19 LCD P 5 LCD pixel data bit 5 A20 LCD P 4 LCD pixel data bit 4 H13 LCD P 3 LCD pixel data bit 3 G14 LCD P 2 LCD pixel data bit 2 C19 LCD P 1 LCD pixel data bit 1 B21 LCD P 0 LCD pixel data bit 0 D18 McBSP1 Interface MCBSP1 CLKS McBSP1 clock input G20 MBSP1 CLKX McBSP1 bit clock G21 MCBSP1 FSX McBSP1 frame synchronization H15 H18 MCBSP1 DX McBSP1 data ouput H18 H15 MCBSP1 DR McBSP1 data ...

Page 1155: ...CSI2 clock Y10 MCSI2 DIN MCSI2 data input AA9 MCSI2 DOUT MCSI2 data output W9 MCSI2 SYNC MCSI2 frame synchronization V9 UART1 Interface UART1 RX UART1 receive data V14 UART1 TX UART1 transmit data Y14 UART1 RTS UART1 request to send AA15 UART1 CTS UART1 clear to send R14 UART1 DSR UART1 data set ready U18 R13 UART1 DTR UART1 data terminal ready W21 Y13 UART3 Interface UART3 RX UART3 receive data L...

Page 1156: ...REQ Request for the M CLK R10 BCLK BCLK general purpose clock output Y13 BCLKREQ BCLK request input R13 GPIO GPIO15 General purpose I O 15 M20 GPIO14 General purpose I O 14 N21 GPIO13 General purpose I O 13 N19 GPIO12 General purpose I O 12 N18 W6 GPIO11 General purpose I O 11 N20 V7 GPIO9 General purpose I O 9 W8 GPIO8 General purpose I O 8 Y8 GPIO7 General purpose I O 7 M15 Y5 V9 GPIO6 General p...

Page 1157: ...U input output 2 N15 MPUIO1 MPU input output 1 U19 MPUIO0 MPU input output 0 Y12 I2C Interface SCL I2C master serial clock T18 SDA I2C serial bidirectional data V20 UWIRE Interface UWIRE SDI UWIRE serial data input U18 J14 UWIRE SDO UWIRE serial data output W21 H19 UWIRE SCLK UWIRE serial clock V19 J15 UWIRE CS0 UWIRE serial chip select 0 N14 J18 UWIRE CS3 UWIRE serial chip select 3 P15 J19 McBSP3...

Page 1158: ...XT_DMA_REQ0 External DMA request 0 N15 LOW_PWR Low power request T20 BFAIL EXT_FIQ Battery voltage failure detection and or external FIQ input W19 IRQ_OBS Interrupt observability output M18 DMA_REQ_OBS DMA request observability output L14 USB Integrated Transceiver Pins USB DP USB differential line P9 USB DM USB differential line R8 USB PUEN USB clock output 6 MHz W4 USB CLKO USB pullup enable W4 ...

Page 1159: ... Camera horizontal synchronization L15 CAM RSTZ Camera module reset M19 MMC SD Interface MMC DAT3 SD card data bit 3 W11 MMC DAT2 SD card data bit 2 W10 M15 MMC DAT1 SD card data bit 1 V10 MMC DAT0_SPI DI MMC or SD card data bit 0 SPI serial input R11 MMC CLK MMC SD clock V11 MMC CMD_SPI DO MMC SD command SPI serial output P11 SPI CS3 SPI chip select 3 P18 SPI CS2 SPI chip select 2 P20 SPI CS1 SPI...

Page 1160: ...rd matrix column 4 C21 KB C 3 Keyboard matrix column 3 E18 KB C 2 Keyboard matrix column 2 D19 KB C 1 Keyboard matrix column 1 D20 KB C 0 Keyboard matrix column 0 F18 KB R 7 Keyboard matrix row 7 M20 KB R 6 Keyboard matrix row 6 N21 KB R 5 Keyboard matrix row 5 N19 KB R 4 Keyboard matrix row 4 E19 KB R 3 Keyboard matrix row 3 E20 KB R 2 Keyboard matrix row 2 H14 KB R 1 Keyboard matrix row 1 F19 KB...

Page 1161: ...6 J19 ETM D 5 ETM9 trace packet bit 5 J14 ETM D 4 ETM9 trace packet bit 4 K18 ETM D 3 ETM9 trace packet bit 3 K19 ETM D 2 ETM9 trace packet bit 2 K15 ETM D 1 ETM9 trace packet bit 1 K14 ETM D 0 ETM9 trace packet bit 0 L19 ETM PSTAT 2 ETM9 trace pipe state bit 2 L18 ETM PSTAT 1 ETM9 trace pipe state bit 1 L15 ETM PSTAT 0 ETM9 trace pipe state bit 0 M19 HDQ 1 Wire Interface HDQ HDQ 1 Wire interface ...

Page 1162: ...USB1 TXEN USB 1 transmit enable W16 USB1 SPEED USB 1 bus segment speed control Y12 USB1 VP USB 1 Vplus receive data V13 USB1 TXD USB 1 transmit data W14 USB1 RCV USB 1 receive data W13 USB Pin Group 2 USB2 VP USB 2 Vplus receive data AA9 USB2 VM USB 2 Vminus receive data R9 USB2 SE0 USB 2 single ended zero W5 USB2 TXEN USB 2 transmit enable W9 USB2 SUSP USB 2 bus segment suspend control Y10 USB2 R...

Page 1163: ...ors on each pin Table A 2 Configuration Programming Ballout Pin by Pin Multiplexing OMAP5910 Configuration Register Register Offset Register Field Value Signal on the Top Pin by Pin Pullup Down OMAP5910 Configuration Register Register Offset Register Field A1 B2 C3 A2 D4 B3 A3 D5 C4 B4 D6 C5 B5 A5 H8 C6 B6 D7 C7 B7 Note When a row is empty it means that there is no Functional multiplexing on this ...

Page 1164: ...Configuration Register Signal on the Top Value Register Field Register Offset Pin by Pin Multiplexing OMAP5910 Configuration Register A7 G8 D8 B8 C8 G9 B9 D9 A9 C9 B10 H9 D10 C10 G10 H10 A11 C11 D11 G11 C12 D12 H11 Note When a row is empty it means that there is no Functional multiplexing on this pin Software configurable pullup pulldown on this pin ...

Page 1165: ...MAP5910 Configuration Register Signal on the Top Value Register Field Register Offset Pin by Pin Multiplexing OMAP5910 Configuration Register B12 A13 C13 D13 B13 G12 C14 B14 A15 D14 H12 B15 C15 D15 B16 C16 A17 G13 B17 C17 D16 B18 D17 Note When a row is empty it means that there is no Functional multiplexing on this pin Software configurable pullup pulldown on this pin ...

Page 1166: ...guration Register Signal on the Top Value Register Field Register Offset Pin by Pin Multiplexing OMAP5910 Configuration Register A19 C18 B19 A20 H13 G14 A21 B20 C19 B21 D18 C20 C21 E18 D19 D20 F18 E19 E20 E21 H14 F19 F20 Note When a row is empty it means that there is no Functional multiplexing on this pin Software configurable pullup pulldown on this pin ...

Page 1167: ...9 G20 G21 H15 FUNC_MUX_ CTRL_4 0x14 14 12 000 MCBSP1 FSX 001 MCBSP1 DX H18 FUNC_MUX_ CTRL_4 0x14 17 15 000 MCBSP1 DX 001 MCBSP1 FSX H20 PULL_DOWN_ CTRL_0 0x40 16 H19 FUNC_MUX_ CTRL_4 0x14 23 21 000 CAM EXCLK 001 ETM SYNC 010 UWIRE SDO J15 FUNC_MUX_ CTRL_4 0x14 26 24 000 CAM LCLK 001 ETM CLK 010 UWIRE SCLK J20 J18 FUNC_MUX_ CTRL_4 0x14 29 27 000 CAM D 7 001 ETM D 7 010 UWIRE CS0 Note When a row is ...

Page 1168: ...0 J14 FUNC_MUX_ CTRL_5 0x18 5 3 000 CAM D 5 PULL_DOWN_ CTRL_0 0x40 21 001 ETM D 5 010 UWIRE SDI K18 FUNC_MUX_ CTRL_5 0x18 8 6 000 CAM D 4 001 ETM D 4 010 UART3 TX K19 FUNC_MUX_ CTRL_5 0x18 11 9 000 CAM D 3 PULL_DOWN_ CTRL_0 0x40 23 001 ETM D 3 010 UART3 RX K15 FUNC_MUX_ CTRL_5 0x18 14 12 000 CAM D 2 PULL_DOWN_ CTRL_0 0x40 24 001 ETM D 2 010 UART3 CTS K14 FUNC_MUX_ CTRL_5 0x18 17 15 000 CAM D 1 001...

Page 1169: ...NC_MUX_ CTRL_5 0x18 20 18 000 CAM D 0 001 ETM D 0 010 MPUIO12 L18 FUNC_MUX_ CTRL_5 0x18 23 21 000 CAM VS 001 ETM PSTAT 2 L15 FUNC_MUX_ CTRL_5 0x18 26 24 000 CAM HS PULL_DOWN_ CTRL_0 0x40 28 001 ETM PSTAT 1 010 UART2 CTS M19 FUNC_MUX_ CTRL_5 0x18 29 27 000 CAM RSTZ 001 ETM PSTAT 0 010 UART2 RTS M18 FUNC_MUX_ CTRL_6 0x1C 2 0 000 UART3 TX 001 UART3 TX 010 PWT 011 Reserved 100 UART2 TX Note When a row...

Page 1170: ...1C 8 6 000 GPIO15 PULL_DOWN_ CTRL_1 0x44 0 001 KB R 7 N21 FUNC_MUX_ CTRL_6 0x1C 11 9 000 GPIO14 PULL_DOWN_ CTRL_1 0x44 1 001 KB R 6 N19 FUNC_MUX_ CTRL_6 0x1C 14 12 000 GPIO13 PULL_DOWN_ CTRL_1 0x44 2 001 KB R 5 N18 FUNC_MUX_ CTRL_6 0x1C 17 15 000 GPIO12 PULL_DOWN_ CTRL_1 0x44 3 001 MCBSP3 FSX N20 FUNC_MUX_ CTRL_6 0x1C 20 18 000 GPIO11 PULL_DOWN_ CTRL_1 0x44 4 001 HDQ M15 FUNC_MUX_ CTRL_6 0x1C 23 2...

Page 1171: ...O6 PULL_DOWN_ CTRL_1 0x44 6 001 SPI CS1 010 MCBSP3 FSX P20 FUNC_MUX_ CTRL_6 0x1C 29 27 000 GPIO4 PULL_DOWN_ CTRL_1 0x44 7 001 SPI CS2 010 MCBSP3 FSX R21 P18 FUNC_MUX_ CTRL_7 0x20 2 0 000 GPIO3 PULL_DOWN_ CTRL_1 0x44 8 001 SPI CS3 010 MCBSP3 FSX 011 LED1 M14 FUNC_MUX_ CTRL_7 0x20 5 3 000 GPIO2 PULL_DOWN_ CTRL_1 0x44 9 001 SPI CLK R20 R19 FUNC_MUX_ CTRL_7 0x20 8 6 000 GPIO1 PULL_DOWN_ CTRL_1 0x44 10...

Page 1172: ...1 SPI RDY 010 USB VBUS T20 FUNC_MUX_ CTRL_7 0x20 14 12 000 MPUIO5 PULL_DOWN_ CTRL_1 0x44 12 001 LOW_PWR T19 FUNC_MUX_ CTRL_7 0x20 17 15 000 MPUIO4 PULL_DOWN_ CTRL_1 0x44 13 001 EXT_DMA_ REQ0 010 LED2 U21 N15 FUNC_MUX_ CTRL_7 0x20 20 18 000 MPUIO2 PULL_DOWN_ CTRL_1 0x44 14 001 EXT_DMA_ REQ0 U20 U19 T18 V20 U18 FUNC_MUX_ CTRL_8 0x24 2 0 000 UWIRE SDI PULL_DOWN_ CTRL_1 0x44 18 001 UART3 DSR 010 UART1...

Page 1173: ...ration Register W21 FUNC_MUX_ CTRL_8 0x24 5 3 000 UWIRE SDO 001 UART3 DTR 010 UART1 DTR 011 MCBSP3 DX V19 FUNC_MUX_ CTRL_8 0x24 8 6 000 UWIRE SCLK 001 KB C 7 W20 Y21 N14 FUNC_MUX_ CTRL_8 0x24 11 9 000 UWIRE CS0 001 UWIRE CS0 010 MCBSP3 CLKX P15 FUNC_MUX_ CTRL_8 0x24 14 12 000 UWIRE CS3 001 UWIRE CS3 010 KB C 6 AA21 Y20 W19 AA20 V18 PULL_DOWN_ CTRL_3 0x4C 9 Note When a row is empty it means that th...

Page 1174: ...C 11 W18 PULL_DOWN_ CTRL_3 0x4C 12 Y18 PULL_DOWN_ CTRL_3 0x4C 13 V16 PULL_DOWN_ CTRL_1 0x44 25 W17 PULL_DOWN_ CTRL_1 0x44 26 Y17 AA17 FUNC_MUX_ CTRL_8 0x24 29 27 000 MPU_BOOT PULL_DOWN_ CTRL_1 0x44 27 001 MCBSP3 DR 010 USB1_SUSP P14 FUNC_MUX_ CTRL_9 0x28 2 0 000 RST_HOST_ OUT 001 MCBSP3 DX 010 USB1_SE0 W16 FUNC_MUX_ CTRL_9 0x28 5 3 000 MCBSP3 CLKX PULL_DOWN_ CTRL_1 0x44 29 001 MCBSP3 CLKX 010 USB1...

Page 1175: ...X_ CTRL_9 0x28 14 12 000 UART1 RTS 001 UART1 RTS R14 PULL_DOWN_ CTRL_2 0x48 1 V14 PULL_DOWN_ CTRL_2 0x48 2 Y14 FUNC_MUX_ CTRL_9 0x28 23 21 000 UART1 TX 001 UART1 TX W14 FUNC_MUX_ CTRL_9 0x28 26 24 000 MCSI1 DOUT 001 USB1 TXD R13 FUNC_MUX_ CTRL_9 0x28 29 27 000 UART3 CLKREQ PULL_DOWN_ CTRL_2 0x48 5 001 UART3 CTS 010 UART1 DSR Y13 FUNC_MUX_ CTRL_A 0x2C 2 0 000 UART3 BCLK 001 UART3 RTS 010 UART1 DTR ...

Page 1176: ...DOWN_ CTRL_2 0x48 7 001 USB1 VP AA13 FUNC_MUX_ CTRL_A 0x2C 8 6 000 MCSI1 CLK PULL_DOWN_ CTRL_2 0x48 8 001 USB1 VM W13 FUNC_MUX_ CTRL_A 0x2C 11 9 000 MCSI1 DIN PULL_DOWN_ CTRL_2 0x48 9 001 USB1 RCV Y12 FUNC_MUX_ CTRL_A 0x2C 14 12 000 CLK32K_ OUT 001 MPUIO0 010 USB1 SPEED P13 V12 W12 R12 P12 AA11 W11 FUNC_MUX_ CTRL_D 0x38 14 12 000 MMC DAT3 PULL_DOWN_ CTRL_3 0x4C 8 001 ms_remove 010 MPUIO6 V11 R11 N...

Page 1177: ...orced to Z 010 MPUIO11 V10 FUNC_MUX_ CTRL_A 0x2C 26 24 000 MMC DAT1 PULL_DOWN_ CTRL_2 0x48 14 001 ms_ins 010 MPUIO7 P11 PULL_DOWN_ CTRL_2 0x48 15 Y10 FUNC_MUX_ CTRL_B 0x30 5 3 000 MCSI2 CLK PULL_DOWN_ CTRL_2 0x48 17 001 USB2 SUSP AA9 FUNC_MUX_ CTRL_B 0x30 8 6 000 MCSI2 DIN PULL_DOWN_ CTRL_2 0x48 18 001 USB2 VP W9 FUNC_MUX_ CTRL_B 0x30 11 9 000 MCSI2 DOUT 001 USB2 TXEN V9 FUNC_MUX_ CTRL_B 0x30 14 1...

Page 1178: ... 001 EXT_ MASTER_ REQ W8 PULL_DOWN_ CTRL_2 0x48 23 Y8 PULL_DOWN_ CTRL_2 0x48 24 AA7 V8 PULL_DOWN_ CTRL_2 0x48 25 P10 FUNC_MUX_ CTRL_C 0x34 2 0 000 MCBSP2 DR PULL_DOWN_ CTRL_2 0x48 26 001 MCBSP2 DX Y7 W7 PULL_DOWN_ CTRL_2 0x48 27 V7 FUNC_MUX_ CTRL_C 0x34 8 6 000 MCBSP2 CLKR PULL_DOWN_ CTRL_2 0x48 28 001 GPIO11 Y6 PULL_DOWN_ CTRL_2 0x48 29 W6 FUNC_MUX_ CTRL_C 0x34 14 12 000 MCBSP2 FSR PULL_DOWN_ CTR...

Page 1179: ...WN_ CTRL_2 0x48 31 001 MCBSP2 DR R9 FUNC_MUX_ CTRL_C 0x34 20 18 000 UART2 RX PULL_DOWN_ CTRL_3 0x4C 0 001 USB2 VM Y5 FUNC_MUX_ CTRL_C 0x34 23 21 000 UART2 CTS PULL_DOWN_ CTRL_3 0x4C 1 001 USB2 RCV 010 GPIO7 W5 FUNC_MUX_ CTRL_C 0x34 26 24 000 UART2 RTS 001 UART2 RTS 010 USB2 SE0 011 MPUIO5 V6 FUNC_MUX_ CTRL_C 0x34 29 27 000 UART2 TX 001 UART2 TX 010 USB2 TXD Y4 V5 AA3 W4 FUNC_MUX_ CTRL_D 0x38 5 3 0...

Page 1180: ...5910 Configuration Register Signal on the Top Value Register Field Register Offset Pin by Pin Multiplexing OMAP5910 Configuration Register AA2 P9 R8 AA1 Y2 W3 Y1 V4 W2 W1 U4 V3 V2 T4 U3 U2 U1 P8 T3 T2 R4 R3 R2 Note When a row is empty it means that there is no Functional multiplexing on this pin Software configurable pullup pulldown on this pin ...

Page 1181: ...uration Register Signal on the Top Value Register Field Register Offset Pin by Pin Multiplexing OMAP5910 Configuration Register R1 P7 P4 P2 P3 N7 N2 N4 N1 N3 M2 N8 M4 FUNC_MUX_ CTRL_D 0x38 8 6 000 FLASH CS2 001 FLASH BAA M3 M7 M8 L1 L3 L4 L7 K3 K4 Note When a row is empty it means that there is no Functional multiplexing on this pin Software configurable pullup pulldown on this pin ...

Page 1182: ...P5910 Configuration Register Signal on the Top Value Register Field Register Offset Pin by Pin Multiplexing OMAP5910 Configuration Register L8 K2 J1 J3 J4 J2 K7 H3 H2 G1 H4 K8 G2 G3 G4 F2 F3 E1 J7 E2 E3 F4 D2 Note When a row is empty it means that there is no Functional multiplexing on this pin Software configurable pullup pulldown on this pin ...

Page 1183: ...er Offset Pin by Pin Pullup Down OMAP5910 Configuration Register Signal on the Top Value Register Field Register Offset Pin by Pin Multiplexing OMAP5910 Configuration Register E4 C1 D3 C2 B1 J8 H7 E5 Note When a row is empty it means that there is no Functional multiplexing on this pin Software configurable pullup pulldown on this pin ...

Page 1184: ...A Switching Clock Modes This appendix describes the programming guidelines for switching clock modes in the OMAP5910 device Topic Page B 1 Switching Procedure B 2 B 2 Main Code B 3 B 3 Delay Procedure B 4 Appendix B ...

Page 1185: ...de i Make sure that the frequency of the traffic controller is always less than the maximum frequency of the traffic controller ii Change the clock mode iii Program the clock dividers iv Program DPLL to frequency desired b Switch from SYNCSCALE to SYNC mode i Program the DPLL to the desired frequency in synchronous mode ii Program all clock dividers to be equal iii Change the clock mode to SYNC mo...

Page 1186: ...ck Modes B 2 Main Code The following is the main code for switching modes main Enable Icache INT_SetSupervisor ARM_WRITE_REG1 I_bit INT_SetUser Enable DSP Clock MCU_CKCTL 0x2000 switch_mode CLOCK_MODE_SYNC_SCALE Passing in 0x1000 ...

Page 1187: ...o_32_bis bx r4 nop nop nop state32 arm mode into_32_bis LDR R1 ARM_SYSST MOV R3 0 MOV R2 0 This is the loop that will wait for at least 100 cycles before issuing next request from MPU On the first run of the loop only Icache gets loaded with the loop and the next 2 instructions but write to SYSST does not occur In the 2nd run of the loop only write to SYSST happens and after that MPU runs the loop...

Page 1188: ...Delay Procedure B 5 Switching Clock Modes adr r2 into_16_bis 1 bx r2 state16 into_16_bis nop nop nop nop nop nop nop nop nop nop pop r1 r7 pop pc CONSTANT TABLE ARM_SYSST long 0xFFFECE18 ...

Page 1189: ... display 11 19 display mode 11 17 address checking UART IrDA 12 87 index management DMA controller 5 13 spaces TI925T 4 7 translation MPU MMU 2 28 addressing algorithm LCD 5 27 mode DMA controller constant 5 15 DMA controller double indexed 5 16 DMA controller generic channels 5 13 DMA controller post incremented 5 16 DMA controller single indexed 5 16 units LCD 5 27 alignment fault 2 44 allocatio...

Page 1190: ...er 7 9 data validation 7 5 DMA procedure 7 10 FIFO buffer 7 8 interrupt generator 7 10 MPU public peripherals 7 3 registers 7 12 set of order 7 7 channel configuration constraint DMA controller 5 21 MCSI multichannel enable 9 29 usage restrictions 5 28 characteristics 32 bit timers 8 5 chip idle power management 15 32 15 34 procedure 15 34 clear commands DSP private peripherals level sensitive int...

Page 1191: ...4 4 TI925 4 4 connections external system DMA controller 5 8 constant addressing mode DMA controller generic channels 5 15 continuous mode MCSI 9 29 control read transfer autodecoded 13 70 non autodecoded 13 73 transfer data stage length 13 78 endpoint 0 13 65 write transfer autodecoded 13 69 non autodecoded 13 71 required local host actions for non autodecoded 13 72 coprocessor See coprocessor 15...

Page 1192: ...quest limit on active requests USB 13 124 MMC SD host controller 7 124 USB function 13 5 system generic channels 5 9 transfer threshold level 7 166 transmit public peripherals 9 36 USB isochronous IN transactions 13 124 isochronous OUT transactions 13 119 non isochronous IN transactions 13 120 non isochronous OUT transactions 13 114 transmit channels 13 120 DMA controller channel physical 5 4 comp...

Page 1193: ...al memory 3 10 peripheral register addresses 3 14 system 3 12 types 3 9 MMU endianism conversion 2 72 overview 2 47 translation 3 37 MPU interface HOM SAM mode change 3 34 overview 3 33 MPUI port 2 55 onchip memory overview 3 6 power conservation 3 7 peripherals 1 8 public peripherals 3 39 description 9 2 DMA channel operation 9 36 DMA transmit 9 36 subsystem overview 3 2 peripherals 3 4 system bo...

Page 1194: ...g control 4 17 not ready 4 24 operation 4 15 priority handler 4 14 signal list 4 13 traffic controller external memory 4 4 encoder UART IrDA 12 86 endianism and OHCI data buffers 14 92 and USB host controller access to system memory 14 91 conversion big endian format 2 71 DSP data format 2 72 EMIFF 4 30 little endian format 2 71 MPU subsystem 2 71 through DSP MMU 2 72 through MPUI 2 74 DMA control...

Page 1195: ...flow control hardware UART 12 46 software UART 12 47 FOSCMOD clock dividers MPU public peripherals 7 9 frame buffer LCD controller 11 9 duration error MCSI 9 34 exclusive LCD 5 28 mode MCSI continuous burst 9 29 size MCSI 9 30 structure MCSI multichannel 9 28 single channel 9 28 synchronization MPU public peripherals 7 199 synchronization MCSI normal alternate 9 29 normal inverted 9 29 short long ...

Page 1196: ... MMC SD clocks 7 124 MMC SD DMA request 7 124 MMC SD features 7 122 MMC SD interrupt 7 124 MMC SD reset 7 124 MMC SD signal pads 7 122 OHCI reset 14 116 power management 14 117 USB 14 2 USB access to system memory 14 81 USB hardware reset 14 116 USB reset 14 115 host only mode See HOM 3 29 HSW description 11 35 I I O clocks MPU 7 17 configuration USB function 13 2 interrupts MPU 7 17 MPU keyboard ...

Page 1197: ... peripherals edge triggered 8 26 level sensitive 8 28 generation DMA controller 5 23 generator camera interface architecture 7 3 camera interface interrupts 7 10 handler DSP private peripherals overview 8 15 endpoint 0 receive 13 91 endpoint 0 transmit 13 91 MPU private peripherals 6 14 non isochronous non control IN endpoint transmit 13 105 non isochronous non control OUT endpoint receive 13 105 ...

Page 1198: ...andwidth break 5 28 channel usage restrictions 5 28 color passive mode 11 7 constant register values 5 28 dedicated channel description 5 26 display specifications 11 7 dual frame operation 5 28 enable 11 31 exclusive frames 5 28 FIFO out of data 5 28 horizontal back porch 11 33 horizontal front porch 11 33 lines per panel 11 39 mono passive mode 11 7 mono passive panels 11 18 panel signals reset ...

Page 1199: ...ty identification code 6 70 mapping DMA request 5 32 peripherals DSP 3 14 maskable interrupt DSP private peripherals interrupt handler 8 15 master I2C controller 7 64 mode MCSI 9 28 master slave control MCSI 9 28 McBSP memory mapping 9 56 overview 9 3 peripheral mapping 9 56 McBSP1 application 9 7 I2S audio codec interface 9 7 interrupt mapping 9 6 overview 9 4 request mapping 9 6 McBSP2 communica...

Page 1200: ...7 microprocessing unit interface See MPUI 2 55 MicroWire interface MPU public peripherals 7 30 MMC DMA receive mode 7 166 transmit mode 7 167 MMC SD command flow 7 161 host controller clocks 7 124 description 7 120 DMA request 7 124 features 7 122 interrupt 7 124 reset 7 124 signal pads 7 122 internal pullups 7 125 pin multiplexing 6 26 MMU accessible registers 2 28 domain access control 2 42 DSP ...

Page 1201: ...ding 32 kHz clock 7 47 overriding 32 kHz timer 7 47 reset FIFO 7 6 real time clock oscillator drift compensation 7 175 TIPB access factor 2 66 access time out 2 66 strobe frequencies 2 66 time out 2 66 TIPB bridge abort 2 67 allocation 2 66 overview 2 65 pipeline mode 2 67 posted write 2 67 word accesses 2 65 write buffer operation 2 9 overview 2 8 SWAP instruction 2 9 MPU private peripherals 32 b...

Page 1202: ...See MCSI 9 27 multiplexing conflicts 14 80 N NAK See non acknowledged 13 55 noise filter I2C prescaler 7 65 non acknowledged transaction OUT 13 55 USB IN 13 59 not ready EMIFS functionality 4 24 null pointers 14 91 O OHCI controller overview 14 5 data buffers and endianism 14 92 differences from OMAP1510 14 5 interrupts 14 46 null pointers 14 91 OMAP1510 implementation 14 7 reset USB host controll...

Page 1203: ...red 1 8 DSP MPU 3 40 permission access MPU MMU 2 43 fault 2 45 physical channel 5 24 status register 5 24 transfers DMA controller 5 4 pin multiplexing generic 6 25 MMC SD 6 26 USB 14 48 pipeline mode TIPB bridge 2 67 pixel clock divider 11 44 frequency 11 5 refresh rate 11 44 pixels per line 11 35 port passthrough mode USB 14 119 post incremented addressing mode DMA controller generic channels 5 ...

Page 1204: ...itch clock switching 7 16 communication DSP public peripherals 9 28 Intel 4 16 LCD controller example 7 42 MicroWire interface 7 38 serial EEPROM example 7 39 synchronous flash burst configuration 4 16 PTV divisors 32 bit timers DSP private peripherals 8 4 public peripherals DSP subsystem overview 9 2 system operation 3 39 MPU 7 2 autostart 7 6 frame adjustment counter 7 198 frame synchronization ...

Page 1205: ...hort long framing MCSI 9 28 signal pads MMC SD host controller 7 122 signal sharing ARM_BOOT 14 120 single channel frame structure MCSI 9 28 single indexed addressing mode DMA controller generic channels 5 16 single panel mode LCD controller 11 2 single transfer mode DMA channel description 5 12 SIR mode UART IrDA 12 83 slave I2C controller 7 64 slave mode MCSI 9 28 slave master control MCSI 9 28 ...

Page 1206: ...ming DSP private peripherals 8 5 MPU private peripherals 6 5 registers DSP private peripherals 8 6 MPU private peripherals 6 6 watchdog DSP private peripherals 8 10 MPU private peripherals 6 8 tiny page access 2 26 TIPB access time out MPU 2 66 MPU access factor 2 66 strobe frequencies 2 66 time out 2 66 pipeline mode 2 67 private 2 65 public 2 65 switch for UARTs 12 13 TIPB bridge aborts 2 67 all...

Page 1207: ...U 2 29 section 2 34 table MPU MMU 2 27 translation look aside buffer 289 pin MPU MMU 2 26 lockdown operations 2 22 operation 2 21 transmission baud rate MCSI 9 45 clock frequency MCSI 9 30 9 45 transmit interrupt MCSI 9 33 transmitter I2C master 7 61 slave 7 61 trigger levels UART 12 39 IrDA 12 88 U UART autobauding mode 12 48 break conditions 12 45 FIFO configuration 12 102 DMA mode 12 42 polled ...

Page 1208: ... host controller 14 2 interrupt sources 14 46 access to system memory 14 81 clock control 14 115 description 7 185 hardware reset 14 116 null pointers 14 91 OHCI reset 14 116 power management 14 117 reset 14 115 host controller access to system memory and endianism 14 91 interrupt operation 13 86 parsing 13 87 parsing non isochronous endpoint specific 13 100 summary 13 113 interrupt handler setup ...

Page 1209: ... 42 procedure 15 36 warm reset 15 46 watchdog reset 15 46 timer DSP private peripherals 8 10 interrupt 8 10 MPU private peripherals 6 8 program in timer mode 8 12 program in timer mode MPU 6 11 program in watchdog mode 8 12 program in watchdog mode MPU 6 10 word access TIPB bridge 2 65 size MCSI 9 30 write asynchronous with WE operation 4 23 buffer MPU subsystem 2 8 synchronization DSP DMA control...

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