Inter-Integrated Circuit Controller
7-64
7.8.2
OMAP5910 I
2
C (Master/Slave I
2
C Controller)
The multimaster I
2
C peripheral provides an interface between TIPB bus and
any I
2
C-bus compatible devices that connect via the I
2
C serial bus. External
components attached to the I
2
C bus can serially transmit/receive up to 8-bit
data to/from the local host device through the two-wire I
2
C interface. All refer-
ences to a local host in this section refer to the MPU processor.
This I
2
C peripheral supports any slave or master I
2
C-compatible device.
Figure 7–23 shows an example of a system with multiple I
2
C-compatible de-
vices in which the I
2
C serial ports are all connected together for a two-way
transfer from one device to other devices.
7.8.2.1
I
2
C Controller Features
The main features of the I
2
C controller are as follows:
-
Compliant with Philips I
2
C specification version 2.1 [1]
-
Support standard mode (up to 100 kbit/s) and Fast mode (up to 400 kbit/s)
-
7-bit and 10-bit device addressing modes
-
General call
-
Start/Restart/Stop
-
Multimaster transmitter/slave receiver mode
-
Multimaster receiver/slave transmitter mode
-
Combined master transmit/receive and receive/transmit mode
-
Built-in FIFO for buffered read or write
-
Module enable/disable capability
-
Programmable clock generation
-
16-bit wide access to maximize bus throughput
-
Designed for low power
-
Two DMA channels
-
Wide interrupt capability
The present I
2
C does not support:
-
High-speed (HS) mode for transfer up to 3.4M bits
-
C-bus compatibility mode.